Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	223126	1		T2	1		T3	584		T4	247
auto[FlashEraseBank]	234704	1		T1	7		T2	1		T3	468

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	253159	1		T2	1		T3	1052		T4	11
auto[FlashOpProgram]	185994	1		T1	7		T4	224		T20	1
auto[FlashOpErase]	14677	1		T2	1		T4	12		T22	52
auto[FlashOpInvalid]	4000	1		T99	200		T82	200		T223	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	253159	1		T2	1		T3	1052		T4	11
op[FlashOpProgram]	185994	1		T1	7		T4	224		T20	1
op[FlashOpErase]	14677	1		T2	1		T4	12		T22	52
read_erase_read	727	1		T4	1		T22	3		T25	1
read_prog_read	1240	1		T8	9		T6	7		T41	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	321938	1		T1	1		T2	2		T3	821
auto[FlashPartInfo]	131676	1		T1	6		T3	225		T4	247
auto[FlashPartInfo1]	1023	1		T3	3		T8	2		T24	13
auto[FlashPartInfo2]	3193	1		T3	3		T8	17		T24	30

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	191863	1		T2	1		T3	821		T8	1154
auto[FlashPartData]	auto[FlashOpProgram]	122390	1		T1	1		T20	1		T8	703
auto[FlashPartData]	auto[FlashOpErase]	3765	1		T2	1		T22	38		T25	3
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T99	198		T82	196		T223	194
auto[FlashPartInfo]	auto[FlashOpRead]	58469	1		T3	225		T4	11		T8	366
auto[FlashPartInfo]	auto[FlashOpProgram]	62326	1		T1	6		T4	224		T8	326
auto[FlashPartInfo]	auto[FlashOpErase]	10823	1		T4	12		T22	14		T25	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T82	2		T223	6		T224	2
auto[FlashPartInfo1]	auto[FlashOpRead]	873	1		T3	3		T8	2		T24	13
auto[FlashPartInfo1]	auto[FlashOpProgram]	133	1		T81	32		T99	1		T82	1
auto[FlashPartInfo1]	auto[FlashOpErase]	7	1		T99	1		T82	1		T85	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	10	1		T99	2		T82	2		T102	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1954	1		T3	3		T8	3		T24	30
auto[FlashPartInfo2]	auto[FlashOpProgram]	1145	1		T8	14		T41	1		T25	6
auto[FlashPartInfo2]	auto[FlashOpErase]	82	1		T84	1		T373	12		T86	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T102	2		T374	2		T375	2