Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28199	1		T6	32		T22	16		T56	20
auto[1]	63	1		T34	1		T376	48		T220	1
auto[2]	206	1		T274	22		T221	1		T141	8
auto[3]	319	1		T55	1		T59	2		T61	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7245	1		T6	8		T22	4		T56	5
evic_idx[1]	7190	1		T6	8		T22	4		T56	5
evic_idx[2]	7187	1		T6	8		T22	4		T56	5
evic_idx[3]	7165	1		T6	8		T22	4		T56	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27698	1		T195	124		T138	1		T99	400
evic_op[2]	473	1		T6	32		T34	1		T95	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6832	1		T195	31		T99	100		T196	97
evic_idx[0]	evic_op[1]	auto[1]	23	1		T376	23		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	13	1		T274	7		T377	6		-	-
evic_idx[0]	evic_op[1]	auto[3]	98	1		T274	5		T377	11		T378	22
evic_idx[0]	evic_op[2]	auto[0]	71	1		T6	8		T95	1		T186	1
evic_idx[0]	evic_op[2]	auto[1]	7	1		T220	1		T379	1		T380	1
evic_idx[0]	evic_op[2]	auto[2]	34	1		T221	1		T381	4		T382	10
evic_idx[0]	evic_op[2]	auto[3]	13	1		T55	1		T59	1		T383	1
evic_idx[1]	evic_op[1]	auto[0]	6842	1		T195	31		T99	100		T196	97
evic_idx[1]	evic_op[1]	auto[1]	12	1		T376	12		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	13	1		T274	6		T377	7		-	-
evic_idx[1]	evic_op[1]	auto[3]	67	1		T274	5		T377	7		T378	5
evic_idx[1]	evic_op[2]	auto[0]	68	1		T6	8		T95	1		T186	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T384	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	22	1		T381	2		T382	4		T385	3
evic_idx[1]	evic_op[2]	auto[3]	11	1		T59	1		T386	1		T387	1
evic_idx[2]	evic_op[1]	auto[0]	6839	1		T195	31		T138	1		T99	100
evic_idx[2]	evic_op[1]	auto[1]	8	1		T376	8		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	8	1		T274	4		T377	4		-	-
evic_idx[2]	evic_op[1]	auto[3]	56	1		T274	4		T377	6		T378	15
evic_idx[2]	evic_op[2]	auto[0]	68	1		T6	8		T95	1		T186	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T34	1		T388	1		T389	1
evic_idx[2]	evic_op[2]	auto[2]	33	1		T381	1		T382	13		T385	2
evic_idx[2]	evic_op[2]	auto[3]	17	1		T390	1		T391	1		T392	1
evic_idx[3]	evic_op[1]	auto[0]	6833	1		T195	31		T99	100		T196	97
evic_idx[3]	evic_op[1]	auto[1]	5	1		T376	5		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T274	5		T377	2		-	-
evic_idx[3]	evic_op[1]	auto[3]	42	1		T274	4		T377	8		T378	7
evic_idx[3]	evic_op[2]	auto[0]	66	1		T6	8		T95	1		T186	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T393	1		T394	1		T395	1
evic_idx[3]	evic_op[2]	auto[2]	40	1		T381	1		T382	14		T396	7
evic_idx[3]	evic_op[2]	auto[3]	15	1		T61	1		T281	1		T275	1