Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	57334	1		T52	5113		T53	5579		T54	3414
prog_lvl[2]	820	1		T54	1		T397	1		T398	1
prog_lvl[3]	1	1		T399	1		-	-		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	4353	1		T24	15		T51	11		T57	2
rd_lvl[2]	6402	1		T51	37		T57	11		T58	8
rd_lvl[3]	7625	1		T51	48		T57	9		T58	12
rd_lvl[4]	16408	1		T51	380		T57	13		T58	35
rd_lvl[5]	15332	1		T51	4		T57	352		T228	3
rd_lvl[6]	18223	1		T51	1197		T228	328		T400	804
rd_lvl[7]	10924	1		T51	586		T228	1123		T401	762
rd_lvl[8]	9692	1		T135	999		T228	458		T402	23
rd_lvl[9]	3969	1		T135	301		T400	7		T403	230
rd_lvl[10]	5166	1		T401	34		T404	256		T405	631
rd_lvl[11]	5163	1		T57	565		T228	3		T406	622
rd_lvl[12]	3547	1		T57	394		T58	469		T406	389
rd_lvl[13]	4942	1		T58	458		T372	681		T407	527
rd_lvl[14]	5142	1		T372	467		T407	429		T408	200
rd_lvl[15]	8555	1		T24	618		T57	19		T136	568