Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	316310	1		T48	5		T49	5		T50	1
all_pins[1]	316310	1		T48	5		T49	5		T50	1
all_pins[2]	316310	1		T48	5		T49	5		T50	1
all_pins[3]	316310	1		T48	5		T49	5		T50	1
all_pins[4]	316310	1		T48	5		T49	5		T50	1
all_pins[5]	316310	1		T48	5		T49	5		T50	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1530879	1		T48	19		T49	25		T50	6
values[0x1]	366981	1		T48	11		T49	5		T119	5
transitions[0x0=>0x1]	342881	1		T48	3		T49	3		T119	4
transitions[0x1=>0x0]	342891	1		T48	4		T49	3		T119	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	254094	1		T48	3		T49	5		T50	1
all_pins[0]	values[0x1]	62216	1		T48	2		T128	1		T131	2
all_pins[0]	transitions[0x0=>0x1]	62203	1		T128	1		T131	2		T203	1
all_pins[0]	transitions[0x1=>0x0]	63844	1		T49	3		T119	1		T128	2
all_pins[1]	values[0x0]	252453	1		T48	3		T49	2		T50	1
all_pins[1]	values[0x1]	63857	1		T48	2		T49	3		T119	1
all_pins[1]	transitions[0x0=>0x1]	63832	1		T49	1		T129	1		T203	1
all_pins[1]	transitions[0x1=>0x0]	13642	1		T48	2		T119	1		T120	3
all_pins[2]	values[0x0]	302643	1		T48	1		T49	3		T50	1
all_pins[2]	values[0x1]	13667	1		T48	4		T49	2		T119	2
all_pins[2]	transitions[0x0=>0x1]	10142	1		T48	3		T49	2		T119	2
all_pins[2]	transitions[0x1=>0x0]	126707	1		T119	1		T129	1		T131	1
all_pins[3]	values[0x0]	186078	1		T48	4		T49	5		T50	1
all_pins[3]	values[0x1]	130232	1		T48	1		T119	1		T128	1
all_pins[3]	transitions[0x0=>0x1]	109725	1		T119	1		T128	1		T129	1
all_pins[3]	transitions[0x1=>0x0]	76444	1		T120	2		T131	2		T203	2
all_pins[4]	values[0x0]	219359	1		T48	4		T49	5		T50	1
all_pins[4]	values[0x1]	96951	1		T48	1		T120	2		T131	2
all_pins[4]	transitions[0x0=>0x1]	96939	1		T120	2		T131	2		T254	1
all_pins[4]	transitions[0x1=>0x0]	46	1		T119	1		T128	3		T203	3
all_pins[5]	values[0x0]	316252	1		T48	4		T49	5		T50	1
all_pins[5]	values[0x1]	58	1		T48	1		T119	1		T128	3
all_pins[5]	transitions[0x0=>0x1]	40	1		T119	1		T128	3		T203	3
all_pins[5]	transitions[0x1=>0x0]	62208	1		T48	2		T128	1		T131	2