Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T48	4		T49	4		T119	7
all_values[1]	278	1		T48	4		T49	4		T119	7
all_values[2]	278	1		T48	4		T49	4		T119	7
all_values[3]	278	1		T48	4		T49	4		T119	7
all_values[4]	278	1		T48	4		T49	4		T119	7
all_values[5]	278	1		T48	4		T49	4		T119	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	908	1		T48	13		T49	16		T119	20
auto[1]	760	1		T48	11		T49	8		T119	22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	653	1		T48	7		T49	10		T119	24
auto[1]	1015	1		T48	17		T49	14		T119	18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	984	1		T48	14		T49	16		T119	30
auto[1]	684	1		T48	10		T49	8		T119	12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	64	1		T48	1		T49	1		T119	1
all_values[0]	auto[0]	auto[0]	auto[1]	30	1		T49	1		T128	1		T306	2
all_values[0]	auto[0]	auto[1]	auto[0]	49	1		T49	1		T119	6		T120	3
all_values[0]	auto[0]	auto[1]	auto[1]	20	1		T48	1		T131	1		T203	1
all_values[0]	auto[1]	auto[0]	auto[1]	68	1		T48	2		T49	1		T120	1
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T128	1		T131	1		T203	1
all_values[1]	auto[0]	auto[0]	auto[0]	48	1		T48	1		T119	2		T120	2
all_values[1]	auto[0]	auto[0]	auto[1]	28	1		T119	2		T203	2		T254	1
all_values[1]	auto[0]	auto[1]	auto[0]	49	1		T48	1		T119	1		T128	3
all_values[1]	auto[0]	auto[1]	auto[1]	37	1		T48	1		T49	2		T119	1
all_values[1]	auto[1]	auto[0]	auto[1]	72	1		T49	1		T119	1		T120	2
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T48	1		T49	1		T128	1
all_values[2]	auto[0]	auto[0]	auto[0]	53	1		T49	1		T119	2		T128	2
all_values[2]	auto[0]	auto[0]	auto[1]	28	1		T203	1		T307	1		T306	1
all_values[2]	auto[0]	auto[1]	auto[0]	53	1		T119	1		T129	1		T254	1
all_values[2]	auto[0]	auto[1]	auto[1]	31	1		T48	2		T49	1		T120	2
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T48	1		T49	1		T120	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T48	1		T49	1		T119	4
all_values[3]	auto[0]	auto[0]	auto[0]	68	1		T48	1		T49	3		T119	1
all_values[3]	auto[0]	auto[0]	auto[1]	29	1		T119	2		T128	1		T129	1
all_values[3]	auto[0]	auto[1]	auto[0]	40	1		T48	2		T49	1		T119	1
all_values[3]	auto[0]	auto[1]	auto[1]	30	1		T254	3		T308	2		T204	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T48	1		T119	1		T128	2
all_values[3]	auto[1]	auto[1]	auto[1]	51	1		T119	2		T128	1		T203	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1		T48	1		T49	2		T119	4
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T48	1		T49	1		T203	1
all_values[4]	auto[0]	auto[1]	auto[0]	54	1		T119	2		T120	1		T128	3
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T120	1		T131	1		T203	2
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T48	1		T49	1		T119	1
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T48	1		T120	1		T129	1
all_values[5]	auto[0]	auto[0]	auto[0]	57	1		T119	2		T120	2		T128	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T48	2		T49	1		T128	1
all_values[5]	auto[0]	auto[1]	auto[0]	57	1		T49	1		T119	1		T128	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T119	1		T128	2		T203	3
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T48	1		T49	2		T119	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T48	1		T119	2		T128	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal