Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20644572	1		T16	56		T42	2852		T43	15
full_word	7434172	1		T16	1		T42	945		T43	1133

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28078494	1		T16	57		T42	3787		T43	1148
auto[TlIntgErrCmd]	74	1		T42	5		T194	5		T252	3
auto[TlIntgErrData]	83	1		T42	1		T194	4		T252	4
auto[TlIntgErrBoth]	93	1		T42	4		T194	1		T252	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	23831029	1		T16	57		T42	2763		T43	568
auto[1]	4247715	1		T42	1034		T43	580		T46	45

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20045021	1		T16	56		T42	2485		T43	15
auto[TlIntgErrNone]	partial	auto[1]	599317	1		T42	357		T46	6		T45	7
auto[TlIntgErrNone]	full_word	auto[0]	3785881	1		T16	1		T42	272		T43	553
auto[TlIntgErrNone]	full_word	auto[1]	3648275	1		T42	673		T43	580		T46	39
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T42	2		T194	3		T237	4
auto[TlIntgErrCmd]	partial	auto[1]	37	1		T42	3		T194	2		T252	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T252	1		T310	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T241	1		T296	1		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1		T42	1		T194	2		T252	2
auto[TlIntgErrData]	partial	auto[1]	25	1		T194	1		T252	2		T237	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T239	1		T310	1		T312	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T194	1		T237	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T42	3		T252	1		T237	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T42	1		T194	1		T252	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T313	2		T314	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T310	1		T315	1		T314	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19249	1		T42	9		T45	106		T50	1098
full_word	4342892	1		T45	26		T50	352		T111	295

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4361906	1		T45	132		T50	1450		T111	1564
auto[TlIntgErrCmd]	76	1		T42	6		T194	2		T252	2
auto[TlIntgErrData]	80	1		T42	3		T194	5		T252	4
auto[TlIntgErrBoth]	79	1		T194	3		T252	3		T237	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4337623	1		T45	8		T50	119		T111	65
auto[1]	24518	1		T42	9		T45	124		T50	1331

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1336	1		T45	7		T50	105		T111	59
auto[TlIntgErrNone]	partial	auto[1]	17698	1		T45	99		T50	993		T111	1210
auto[TlIntgErrNone]	full_word	auto[0]	4336187	1		T45	1		T50	14		T111	6
auto[TlIntgErrNone]	full_word	auto[1]	6685	1		T45	25		T50	338		T111	289
auto[TlIntgErrCmd]	partial	auto[0]	23	1		T194	2		T252	1		T237	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T42	6		T252	1		T237	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T237	2		T316	1		T317	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T315	1		T318	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T194	2		T252	2		T237	2
auto[TlIntgErrData]	partial	auto[1]	39	1		T42	3		T194	3		T252	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T310	1		T312	1		T313	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T252	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T194	2		T237	2		T239	1
auto[TlIntgErrBoth]	partial	auto[1]	37	1		T194	1		T252	3		T237	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T241	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T237	2		T239	1		T240	1