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 LINE       12810
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T111,T123,T126
1	1	1	Covered	T42,T43,T44

 LINE       12813
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T42,T43
1	0	1	Covered	T42,T43,T45
1	1	0	Not Covered
1	1	1	Covered	T42,T43,T45

 LINE       12814
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T111,T126,T127
1	1	1	Covered	T42,T43,T44

 LINE       12819
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T50,T111,T114
1	1	1	Covered	T42,T43,T44

 LINE       12824
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T42,T43
1	0	1	Covered	T42,T43,T45
1	1	0	Not Covered
1	1	1	Covered	T42,T43,T45

 LINE       12825
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T126,T266,T264
1	1	1	Covered	T42,T43,T44

 LINE       12842
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T50,T114,T123
1	1	1	Covered	T42,T43,T44

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T43,T45,T48
1	1	0	Covered	T50,T111,T126
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T50,T111,T123
1	1	1	Covered	T42,T43,T44

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T50,T111,T252
1	1	1	Covered	T42,T43,T44

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T43,T46
1	0	1	Covered	T42,T43,T45
1	1	0	Covered	T111,T114,T123
1	1	1	Covered	T42,T43,T44

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T42,T43
1	0	1	Covered	T42,T43,T45
1	1	0	Not Covered
1	1	1	Covered	T42,T43,T45

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T16,T42,T43