Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	328926	1		T1	1		T2	2		T3	2
all_values[1]	328926	1		T1	1		T2	2		T3	2
all_values[2]	328926	1		T1	1		T2	2		T3	2
all_values[3]	328926	1		T1	1		T2	2		T3	2
all_values[4]	328926	1		T1	1		T2	2		T3	2
all_values[5]	328926	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9394	1		T1	6		T2	12		T3	12
auto[1]	1964162	1		T8	14976		T9	16548		T26	18294

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1600042	1		T1	6		T2	9		T3	10
auto[1]	373514	1		T2	3		T3	2		T4	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1148	1		T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	416	1		T2	1		T3	1		T4	1
all_values[0]	auto[1]	auto[0]	261982	1		T8	2496		T9	2758		T26	3049
all_values[0]	auto[1]	auto[1]	65380	1		T57	2392		T176	4400		T177	4676
all_values[1]	auto[0]	auto[0]	1509	1		T1	1		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	57	1		T271	2		T248	1		T241	1
all_values[1]	auto[1]	auto[0]	273035	1		T8	2496		T9	2758		T26	3049
all_values[1]	auto[1]	auto[1]	54325	1		T57	6155		T58	3428		T59	6407
all_values[2]	auto[0]	auto[0]	1446	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	124	1		T5	1		T61	1		T62	1
all_values[2]	auto[1]	auto[0]	322543	1		T8	2477		T9	2758		T26	3021
all_values[2]	auto[1]	auto[1]	4813	1		T8	19		T26	28		T27	6
all_values[3]	auto[0]	auto[0]	1424	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	137	1		T5	1		T61	1		T62	1
all_values[3]	auto[1]	auto[0]	177725	1		T8	304		T9	906		T26	70
all_values[3]	auto[1]	auto[1]	149640	1		T8	2192		T9	1852		T26	2979
all_values[4]	auto[0]	auto[0]	1054	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	503	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	229450	1		T8	1596		T9	1804		T26	1959
all_values[4]	auto[1]	auto[1]	97919	1		T8	900		T9	954		T26	1090
all_values[5]	auto[0]	auto[0]	1436	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	140	1		T2	1		T7	1		T47	1
all_values[5]	auto[1]	auto[0]	327290	1		T8	2496		T9	2758		T26	3049
all_values[5]	auto[1]	auto[1]	60	1		T271	1		T240	3		T241	1