Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8530 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| others[1] |
1005 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T34 |
2 |
| others[2] |
1080 |
1 |
|
T4 |
15 |
|
T6 |
18 |
|
T66 |
4 |
| others[3] |
1758 |
1 |
|
T3 |
1 |
|
T4 |
39 |
|
T9 |
1 |
| false |
539 |
1 |
|
T4 |
9 |
|
T6 |
12 |
|
T34 |
1 |
| true |
1376 |
1 |
|
T8 |
1 |
|
T24 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
5 |
|
T61 |
12 |
|
T201 |
1 |
| others[1] |
219 |
1 |
|
T4 |
12 |
|
T61 |
14 |
|
T229 |
6 |
| others[2] |
233 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T9 |
1 |
| others[3] |
368 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T370 |
1 |
| false |
123 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T47 |
1 |
| true |
13120 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
60 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T61 |
9 |
| others[1] |
221 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T23 |
1 |
| others[2] |
225 |
1 |
|
T4 |
13 |
|
T61 |
14 |
|
T67 |
1 |
| others[3] |
315 |
1 |
|
T4 |
17 |
|
T124 |
1 |
|
T61 |
14 |
| false |
115 |
1 |
|
T4 |
6 |
|
T61 |
6 |
|
T229 |
5 |
| true |
13208 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8689 |
1 |
|
T4 |
20 |
|
T17 |
2 |
|
T6 |
14 |
| others[1] |
1209 |
1 |
|
T4 |
15 |
|
T6 |
17 |
|
T34 |
1 |
| others[2] |
1247 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T6 |
24 |
| others[3] |
2100 |
1 |
|
T3 |
1 |
|
T4 |
32 |
|
T23 |
1 |
| false |
620 |
1 |
|
T4 |
17 |
|
T6 |
10 |
|
T66 |
1 |
| true |
423 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8670 |
1 |
|
T4 |
16 |
|
T17 |
2 |
|
T6 |
20 |
| others[1] |
1225 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
9 |
| others[2] |
1256 |
1 |
|
T3 |
1 |
|
T4 |
28 |
|
T6 |
20 |
| others[3] |
2101 |
1 |
|
T3 |
1 |
|
T4 |
31 |
|
T6 |
33 |
| false |
632 |
1 |
|
T4 |
7 |
|
T6 |
11 |
|
T66 |
1 |
| true |
404 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T4 |
6 |
|
T61 |
3 |
|
T229 |
4 |
| others[1] |
122 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T124 |
1 |
| others[2] |
98 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T23 |
1 |
| others[3] |
166 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
9 |
| false |
47 |
1 |
|
T4 |
4 |
|
T61 |
1 |
|
T157 |
1 |
| true |
13745 |
1 |
|
T2 |
1 |
|
T4 |
76 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T4 |
17 |
|
T24 |
1 |
|
T61 |
13 |
| others[1] |
214 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T370 |
1 |
| others[2] |
229 |
1 |
|
T4 |
9 |
|
T61 |
7 |
|
T229 |
8 |
| others[3] |
392 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T124 |
1 |
| false |
134 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T26 |
1 |
| true |
13104 |
1 |
|
T3 |
1 |
|
T4 |
55 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8478 |
1 |
|
T4 |
20 |
|
T17 |
2 |
|
T9 |
1 |
| others[1] |
1086 |
1 |
|
T4 |
21 |
|
T6 |
15 |
|
T34 |
2 |
| others[2] |
1054 |
1 |
|
T4 |
23 |
|
T6 |
24 |
|
T34 |
1 |
| others[3] |
1761 |
1 |
|
T3 |
1 |
|
T4 |
29 |
|
T8 |
1 |
| false |
559 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
8 |
| true |
1350 |
1 |
|
T24 |
1 |
|
T18 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T4 |
9 |
|
T61 |
7 |
|
T68 |
1 |
| others[1] |
223 |
1 |
|
T4 |
11 |
|
T61 |
11 |
|
T67 |
1 |
| others[2] |
212 |
1 |
|
T4 |
9 |
|
T370 |
1 |
|
T61 |
11 |
| others[3] |
382 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T23 |
1 |
| false |
111 |
1 |
|
T4 |
9 |
|
T9 |
1 |
|
T61 |
4 |
| true |
13139 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T4 |
8 |
|
T124 |
1 |
|
T61 |
13 |
| others[1] |
210 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T67 |
1 |
| others[2] |
218 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T61 |
10 |
| others[3] |
364 |
1 |
|
T4 |
15 |
|
T61 |
16 |
|
T249 |
1 |
| false |
114 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T61 |
3 |
| true |
13179 |
1 |
|
T3 |
1 |
|
T4 |
50 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8678 |
1 |
|
T4 |
21 |
|
T17 |
2 |
|
T6 |
16 |
| others[1] |
1228 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
18 |
| others[2] |
1274 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
18 |
| others[3] |
2049 |
1 |
|
T4 |
34 |
|
T23 |
1 |
|
T6 |
30 |
| false |
635 |
1 |
|
T4 |
10 |
|
T6 |
11 |
|
T66 |
1 |
| true |
424 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T4 |
24 |
|
T6 |
17 |
|
T34 |
2 |
| others[1] |
1256 |
1 |
|
T4 |
15 |
|
T6 |
13 |
|
T66 |
1 |
| others[2] |
1219 |
1 |
|
T3 |
2 |
|
T4 |
22 |
|
T6 |
11 |
| others[3] |
2086 |
1 |
|
T4 |
29 |
|
T23 |
1 |
|
T6 |
42 |
| false |
642 |
1 |
|
T4 |
11 |
|
T6 |
10 |
|
T34 |
1 |
| true |
401 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T61 |
5 |
| others[1] |
82 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T61 |
5 |
| others[2] |
101 |
1 |
|
T4 |
1 |
|
T61 |
3 |
|
T229 |
1 |
| others[3] |
174 |
1 |
|
T4 |
6 |
|
T23 |
1 |
|
T61 |
7 |
| false |
55 |
1 |
|
T4 |
2 |
|
T124 |
2 |
|
T61 |
1 |
| true |
6312 |
1 |
|
T2 |
1 |
|
T4 |
87 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T8 |
1 |
| others[1] |
235 |
1 |
|
T4 |
6 |
|
T61 |
14 |
|
T229 |
9 |
| others[2] |
222 |
1 |
|
T4 |
12 |
|
T124 |
1 |
|
T61 |
5 |
| others[3] |
376 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T23 |
1 |
| false |
119 |
1 |
|
T4 |
5 |
|
T370 |
1 |
|
T61 |
2 |
| true |
5635 |
1 |
|
T2 |
1 |
|
T4 |
59 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
21 |
| others[1] |
1022 |
1 |
|
T4 |
29 |
|
T24 |
1 |
|
T6 |
18 |
| others[2] |
1101 |
1 |
|
T4 |
21 |
|
T6 |
21 |
|
T34 |
3 |
| others[3] |
1706 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T6 |
30 |
| false |
540 |
1 |
|
T4 |
11 |
|
T23 |
1 |
|
T6 |
9 |
| true |
1396 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T370 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T7 |
1 |
| others[1] |
249 |
1 |
|
T4 |
10 |
|
T124 |
1 |
|
T61 |
11 |
| others[2] |
218 |
1 |
|
T4 |
10 |
|
T61 |
9 |
|
T26 |
1 |
| others[3] |
359 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T61 |
18 |
| false |
115 |
1 |
|
T4 |
4 |
|
T61 |
5 |
|
T201 |
1 |
| true |
5660 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
| others[1] |
215 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T61 |
5 |
| others[2] |
195 |
1 |
|
T4 |
9 |
|
T61 |
14 |
|
T229 |
14 |
| others[3] |
321 |
1 |
|
T4 |
11 |
|
T370 |
1 |
|
T61 |
14 |
| false |
107 |
1 |
|
T4 |
6 |
|
T61 |
6 |
|
T229 |
3 |
| true |
5762 |
1 |
|
T4 |
56 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T4 |
23 |
|
T6 |
20 |
|
T34 |
1 |
| others[1] |
1249 |
1 |
|
T3 |
1 |
|
T4 |
27 |
|
T6 |
16 |
| others[2] |
1225 |
1 |
|
T4 |
15 |
|
T23 |
1 |
|
T6 |
14 |
| others[3] |
2045 |
1 |
|
T4 |
25 |
|
T6 |
31 |
|
T34 |
3 |
| false |
616 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T6 |
12 |
| true |
430 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
18 |
| others[1] |
1228 |
1 |
|
T4 |
19 |
|
T6 |
21 |
|
T66 |
3 |
| others[2] |
1254 |
1 |
|
T4 |
17 |
|
T6 |
15 |
|
T34 |
2 |
| others[3] |
2059 |
1 |
|
T3 |
1 |
|
T4 |
30 |
|
T6 |
25 |
| false |
666 |
1 |
|
T4 |
12 |
|
T23 |
1 |
|
T6 |
14 |
| true |
405 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T23 |
1 |
| others[1] |
87 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T372 |
2 |
| others[2] |
91 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T124 |
1 |
| others[3] |
156 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T61 |
6 |
| false |
58 |
1 |
|
T4 |
2 |
|
T124 |
1 |
|
T61 |
3 |
| true |
6342 |
1 |
|
T4 |
83 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T61 |
11 |
| others[1] |
230 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
5 |
| others[2] |
222 |
1 |
|
T4 |
10 |
|
T370 |
1 |
|
T61 |
6 |
| others[3] |
405 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| false |
131 |
1 |
|
T4 |
6 |
|
T23 |
1 |
|
T124 |
1 |
| true |
5585 |
1 |
|
T4 |
47 |
|
T9 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1045 |
1 |
|
T3 |
2 |
|
T4 |
15 |
|
T9 |
1 |
| others[1] |
1053 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T24 |
1 |
| others[2] |
1043 |
1 |
|
T4 |
13 |
|
T8 |
1 |
|
T6 |
15 |
| others[3] |
1792 |
1 |
|
T4 |
42 |
|
T6 |
27 |
|
T34 |
3 |
| false |
518 |
1 |
|
T4 |
11 |
|
T6 |
10 |
|
T34 |
1 |
| true |
1382 |
1 |
|
T2 |
1 |
|
T370 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T4 |
8 |
|
T8 |
1 |
|
T61 |
8 |
| others[1] |
224 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T61 |
6 |
| others[2] |
227 |
1 |
|
T4 |
6 |
|
T61 |
8 |
|
T52 |
1 |
| others[3] |
394 |
1 |
|
T4 |
16 |
|
T9 |
1 |
|
T61 |
21 |
| false |
106 |
1 |
|
T4 |
8 |
|
T124 |
2 |
|
T61 |
7 |
| true |
5653 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
43 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T4 |
8 |
|
T370 |
1 |
|
T61 |
8 |
| others[1] |
227 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T61 |
9 |
| others[2] |
196 |
1 |
|
T3 |
2 |
|
T4 |
7 |
|
T61 |
9 |
| others[3] |
329 |
1 |
|
T4 |
14 |
|
T124 |
2 |
|
T61 |
12 |
| false |
124 |
1 |
|
T4 |
4 |
|
T61 |
6 |
|
T229 |
5 |
| true |
5733 |
1 |
|
T2 |
1 |
|
T4 |
56 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T6 |
23 |
| others[1] |
1258 |
1 |
|
T4 |
24 |
|
T6 |
20 |
|
T34 |
2 |
| others[2] |
1279 |
1 |
|
T4 |
19 |
|
T6 |
20 |
|
T34 |
1 |
| others[3] |
2049 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T23 |
1 |
| false |
632 |
1 |
|
T4 |
10 |
|
T6 |
9 |
|
T172 |
1 |
| true |
432 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1297 |
1 |
|
T4 |
23 |
|
T6 |
17 |
|
T34 |
2 |
| others[1] |
1259 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T6 |
17 |
| others[2] |
1216 |
1 |
|
T4 |
19 |
|
T6 |
19 |
|
T66 |
1 |
| others[3] |
2005 |
1 |
|
T3 |
1 |
|
T4 |
27 |
|
T23 |
1 |
| false |
640 |
1 |
|
T4 |
10 |
|
T6 |
10 |
|
T34 |
1 |
| true |
416 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T61 |
2 |
| others[1] |
98 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T61 |
3 |
| others[2] |
97 |
1 |
|
T4 |
5 |
|
T124 |
1 |
|
T61 |
5 |
| others[3] |
154 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T124 |
1 |
| false |
54 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T229 |
4 |
| true |
6324 |
1 |
|
T4 |
77 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T61 |
9 |
| others[1] |
257 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T23 |
1 |
| others[2] |
238 |
1 |
|
T4 |
11 |
|
T9 |
1 |
|
T124 |
1 |
| others[3] |
384 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T61 |
19 |
| false |
118 |
1 |
|
T4 |
7 |
|
T61 |
3 |
|
T26 |
1 |
| true |
5618 |
1 |
|
T4 |
49 |
|
T8 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T4 |
15 |
|
T6 |
22 |
|
T7 |
1 |
| others[1] |
1075 |
1 |
|
T4 |
22 |
|
T9 |
1 |
|
T6 |
17 |
| others[2] |
1000 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T23 |
1 |
| others[3] |
1786 |
1 |
|
T3 |
1 |
|
T4 |
32 |
|
T6 |
38 |
| false |
587 |
1 |
|
T4 |
8 |
|
T6 |
3 |
|
T66 |
1 |
| true |
1323 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T4 |
12 |
|
T61 |
8 |
|
T47 |
1 |
| others[1] |
234 |
1 |
|
T4 |
13 |
|
T7 |
1 |
|
T61 |
6 |
| others[2] |
201 |
1 |
|
T4 |
9 |
|
T61 |
7 |
|
T67 |
1 |
| others[3] |
349 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T23 |
1 |
| false |
129 |
1 |
|
T4 |
3 |
|
T61 |
7 |
|
T229 |
7 |
| true |
5670 |
1 |
|
T3 |
2 |
|
T4 |
47 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T4 |
10 |
|
T124 |
1 |
|
T61 |
8 |
| others[1] |
204 |
1 |
|
T4 |
7 |
|
T61 |
12 |
|
T249 |
1 |
| others[2] |
192 |
1 |
|
T4 |
9 |
|
T61 |
4 |
|
T229 |
10 |
| others[3] |
355 |
1 |
|
T4 |
18 |
|
T61 |
12 |
|
T68 |
1 |
| false |
132 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T7 |
1 |
| true |
5717 |
1 |
|
T3 |
2 |
|
T4 |
50 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |