Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T4 |
20 |
|
T6 |
16 |
|
T34 |
1 |
| others[1] |
1285 |
1 |
|
T3 |
2 |
|
T4 |
20 |
|
T6 |
15 |
| others[2] |
1191 |
1 |
|
T4 |
21 |
|
T23 |
1 |
|
T6 |
17 |
| others[3] |
2038 |
1 |
|
T4 |
35 |
|
T6 |
39 |
|
T34 |
1 |
| false |
685 |
1 |
|
T4 |
5 |
|
T6 |
6 |
|
T61 |
12 |
| true |
421 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T4 |
14 |
|
T6 |
18 |
|
T34 |
2 |
| others[1] |
1260 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T6 |
17 |
| others[2] |
1260 |
1 |
|
T4 |
20 |
|
T6 |
26 |
|
T34 |
1 |
| others[3] |
2049 |
1 |
|
T3 |
2 |
|
T4 |
34 |
|
T6 |
26 |
| false |
641 |
1 |
|
T4 |
13 |
|
T6 |
6 |
|
T34 |
1 |
| true |
397 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T23 |
1 |
| others[1] |
93 |
1 |
|
T4 |
6 |
|
T61 |
4 |
|
T229 |
5 |
| others[2] |
110 |
1 |
|
T124 |
1 |
|
T61 |
5 |
|
T157 |
2 |
| others[3] |
162 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T61 |
7 |
| false |
58 |
1 |
|
T4 |
3 |
|
T124 |
1 |
|
T61 |
3 |
| true |
6302 |
1 |
|
T2 |
1 |
|
T4 |
78 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T4 |
8 |
|
T24 |
1 |
|
T61 |
8 |
| others[1] |
214 |
1 |
|
T4 |
9 |
|
T23 |
1 |
|
T61 |
10 |
| others[2] |
217 |
1 |
|
T4 |
7 |
|
T370 |
1 |
|
T61 |
7 |
| others[3] |
397 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T61 |
24 |
| false |
109 |
1 |
|
T4 |
1 |
|
T61 |
4 |
|
T229 |
3 |
| true |
5672 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
60 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1105 |
1 |
|
T3 |
1 |
|
T4 |
25 |
|
T6 |
22 |
| others[1] |
999 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T6 |
18 |
| others[2] |
1058 |
1 |
|
T4 |
22 |
|
T6 |
21 |
|
T34 |
1 |
| others[3] |
1770 |
1 |
|
T4 |
27 |
|
T9 |
1 |
|
T6 |
22 |
| false |
544 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T23 |
1 |
| true |
1357 |
1 |
|
T8 |
1 |
|
T24 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T4 |
7 |
|
T61 |
11 |
|
T125 |
1 |
| others[1] |
225 |
1 |
|
T4 |
10 |
|
T8 |
1 |
|
T23 |
1 |
| others[2] |
219 |
1 |
|
T4 |
5 |
|
T61 |
11 |
|
T229 |
12 |
| others[3] |
369 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T124 |
1 |
| false |
124 |
1 |
|
T4 |
5 |
|
T61 |
5 |
|
T229 |
5 |
| true |
5676 |
1 |
|
T3 |
2 |
|
T4 |
56 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T4 |
7 |
|
T61 |
10 |
|
T229 |
10 |
| others[1] |
227 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
7 |
| others[2] |
212 |
1 |
|
T4 |
9 |
|
T61 |
11 |
|
T229 |
6 |
| others[3] |
326 |
1 |
|
T4 |
13 |
|
T23 |
1 |
|
T370 |
1 |
| false |
108 |
1 |
|
T4 |
5 |
|
T61 |
8 |
|
T229 |
5 |
| true |
5741 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
58 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T6 |
15 |
| others[1] |
1271 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
22 |
| others[2] |
1222 |
1 |
|
T4 |
17 |
|
T23 |
1 |
|
T6 |
16 |
| others[3] |
2028 |
1 |
|
T4 |
32 |
|
T6 |
28 |
|
T172 |
1 |
| false |
630 |
1 |
|
T4 |
7 |
|
T6 |
12 |
|
T66 |
2 |
| true |
418 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
12 |
| others[1] |
1256 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T6 |
23 |
| others[2] |
1236 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
25 |
| others[3] |
2087 |
1 |
|
T4 |
28 |
|
T6 |
24 |
|
T34 |
2 |
| false |
620 |
1 |
|
T4 |
17 |
|
T6 |
9 |
|
T124 |
1 |
| true |
411 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T4 |
2 |
|
T61 |
3 |
|
T229 |
2 |
| others[1] |
117 |
1 |
|
T4 |
7 |
|
T61 |
4 |
|
T157 |
1 |
| others[2] |
100 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T124 |
1 |
| others[3] |
156 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T23 |
1 |
| false |
50 |
1 |
|
T4 |
2 |
|
T124 |
1 |
|
T229 |
2 |
| true |
6319 |
1 |
|
T2 |
1 |
|
T4 |
81 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
12 |
|
T24 |
1 |
|
T61 |
14 |
| others[1] |
222 |
1 |
|
T4 |
5 |
|
T9 |
1 |
|
T124 |
1 |
| others[2] |
208 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T7 |
1 |
| others[3] |
403 |
1 |
|
T4 |
22 |
|
T61 |
17 |
|
T249 |
1 |
| false |
104 |
1 |
|
T4 |
3 |
|
T61 |
2 |
|
T229 |
2 |
| true |
5678 |
1 |
|
T3 |
2 |
|
T4 |
45 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T4 |
17 |
|
T6 |
10 |
|
T34 |
2 |
| others[1] |
1043 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
24 |
| others[2] |
1019 |
1 |
|
T4 |
24 |
|
T18 |
1 |
|
T6 |
16 |
| others[3] |
1810 |
1 |
|
T4 |
25 |
|
T8 |
1 |
|
T24 |
1 |
| false |
537 |
1 |
|
T4 |
11 |
|
T6 |
13 |
|
T61 |
8 |
| true |
1372 |
1 |
|
T9 |
1 |
|
T7 |
1 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T61 |
14 |
| others[1] |
217 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T9 |
1 |
| others[2] |
203 |
1 |
|
T4 |
8 |
|
T370 |
1 |
|
T61 |
4 |
| others[3] |
342 |
1 |
|
T4 |
13 |
|
T61 |
15 |
|
T47 |
1 |
| false |
125 |
1 |
|
T4 |
4 |
|
T61 |
9 |
|
T229 |
7 |
| true |
5731 |
1 |
|
T3 |
1 |
|
T4 |
55 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T4 |
7 |
|
T61 |
10 |
|
T67 |
1 |
| others[1] |
204 |
1 |
|
T4 |
8 |
|
T61 |
16 |
|
T157 |
1 |
| others[2] |
207 |
1 |
|
T4 |
3 |
|
T61 |
7 |
|
T229 |
13 |
| others[3] |
365 |
1 |
|
T4 |
20 |
|
T124 |
1 |
|
T61 |
14 |
| false |
116 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T370 |
1 |
| true |
5730 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T6 |
15 |
| others[1] |
1241 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
23 |
| others[2] |
1174 |
1 |
|
T4 |
23 |
|
T6 |
22 |
|
T34 |
1 |
| others[3] |
2078 |
1 |
|
T4 |
28 |
|
T23 |
1 |
|
T6 |
25 |
| false |
688 |
1 |
|
T4 |
7 |
|
T6 |
8 |
|
T34 |
1 |
| true |
423 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1179 |
1 |
|
T4 |
16 |
|
T6 |
22 |
|
T34 |
1 |
| others[1] |
1279 |
1 |
|
T4 |
11 |
|
T6 |
15 |
|
T66 |
2 |
| others[2] |
1210 |
1 |
|
T4 |
28 |
|
T23 |
1 |
|
T6 |
11 |
| others[3] |
2110 |
1 |
|
T3 |
2 |
|
T4 |
33 |
|
T6 |
28 |
| false |
652 |
1 |
|
T4 |
13 |
|
T6 |
17 |
|
T34 |
1 |
| true |
403 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T4 |
6 |
|
T370 |
1 |
|
T61 |
3 |
| others[1] |
106 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T124 |
1 |
| others[2] |
104 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T124 |
1 |
| others[3] |
146 |
1 |
|
T4 |
6 |
|
T61 |
3 |
|
T157 |
1 |
| false |
59 |
1 |
|
T4 |
1 |
|
T61 |
3 |
|
T67 |
1 |
| true |
6322 |
1 |
|
T2 |
1 |
|
T4 |
80 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T61 |
8 |
| others[1] |
226 |
1 |
|
T4 |
5 |
|
T9 |
1 |
|
T370 |
1 |
| others[2] |
236 |
1 |
|
T4 |
16 |
|
T61 |
12 |
|
T47 |
1 |
| others[3] |
365 |
1 |
|
T4 |
21 |
|
T23 |
1 |
|
T61 |
10 |
| false |
115 |
1 |
|
T4 |
7 |
|
T7 |
1 |
|
T61 |
6 |
| true |
5652 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T24 |
1 |
| others[1] |
1031 |
1 |
|
T4 |
22 |
|
T23 |
1 |
|
T6 |
9 |
| others[2] |
1123 |
1 |
|
T4 |
14 |
|
T6 |
23 |
|
T66 |
1 |
| others[3] |
1719 |
1 |
|
T3 |
2 |
|
T4 |
37 |
|
T18 |
1 |
| false |
571 |
1 |
|
T4 |
9 |
|
T6 |
11 |
|
T34 |
1 |
| true |
1346 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T4 |
7 |
|
T61 |
10 |
|
T229 |
12 |
| others[1] |
209 |
1 |
|
T4 |
8 |
|
T9 |
1 |
|
T61 |
10 |
| others[2] |
251 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T7 |
1 |
| others[3] |
343 |
1 |
|
T4 |
15 |
|
T61 |
21 |
|
T249 |
1 |
| false |
118 |
1 |
|
T4 |
5 |
|
T61 |
7 |
|
T229 |
3 |
| true |
5698 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T4 |
9 |
|
T61 |
4 |
|
T229 |
9 |
| others[1] |
218 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T61 |
9 |
| others[2] |
194 |
1 |
|
T4 |
6 |
|
T23 |
1 |
|
T61 |
12 |
| others[3] |
381 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T61 |
18 |
| false |
106 |
1 |
|
T4 |
1 |
|
T61 |
8 |
|
T229 |
3 |
| true |
5731 |
1 |
|
T2 |
1 |
|
T4 |
51 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T4 |
24 |
|
T6 |
11 |
|
T172 |
1 |
| others[1] |
1253 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T23 |
1 |
| others[2] |
1203 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T6 |
21 |
| others[3] |
2086 |
1 |
|
T4 |
30 |
|
T6 |
33 |
|
T66 |
3 |
| false |
605 |
1 |
|
T4 |
9 |
|
T6 |
12 |
|
T66 |
1 |
| true |
423 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T4 |
21 |
|
T6 |
10 |
|
T34 |
1 |
| others[1] |
1217 |
1 |
|
T4 |
19 |
|
T6 |
24 |
|
T66 |
2 |
| others[2] |
1256 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
21 |
| others[3] |
2057 |
1 |
|
T3 |
1 |
|
T4 |
40 |
|
T23 |
1 |
| false |
627 |
1 |
|
T4 |
8 |
|
T6 |
11 |
|
T66 |
1 |
| true |
411 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T61 |
5 |
| others[1] |
96 |
1 |
|
T4 |
5 |
|
T23 |
1 |
|
T124 |
2 |
| others[2] |
77 |
1 |
|
T4 |
4 |
|
T61 |
2 |
|
T229 |
2 |
| others[3] |
171 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T61 |
6 |
| false |
48 |
1 |
|
T61 |
2 |
|
T229 |
2 |
|
T373 |
2 |
| true |
6332 |
1 |
|
T2 |
1 |
|
T4 |
81 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T4 |
6 |
|
T9 |
1 |
|
T124 |
1 |
| others[1] |
204 |
1 |
|
T4 |
10 |
|
T61 |
14 |
|
T229 |
5 |
| others[2] |
254 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T8 |
1 |
| others[3] |
394 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T61 |
17 |
| false |
120 |
1 |
|
T4 |
2 |
|
T23 |
1 |
|
T7 |
1 |
| true |
5630 |
1 |
|
T3 |
1 |
|
T4 |
54 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T23 |
1 |
| others[1] |
1015 |
1 |
|
T4 |
20 |
|
T9 |
1 |
|
T6 |
19 |
| others[2] |
1095 |
1 |
|
T4 |
21 |
|
T18 |
1 |
|
T6 |
25 |
| others[3] |
1748 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T24 |
1 |
| false |
541 |
1 |
|
T4 |
10 |
|
T6 |
3 |
|
T34 |
1 |
| true |
1372 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T370 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T4 |
12 |
|
T61 |
10 |
|
T157 |
1 |
| others[1] |
201 |
1 |
|
T4 |
10 |
|
T61 |
12 |
|
T26 |
1 |
| others[2] |
240 |
1 |
|
T4 |
14 |
|
T8 |
1 |
|
T61 |
10 |
| others[3] |
377 |
1 |
|
T3 |
2 |
|
T4 |
18 |
|
T23 |
1 |
| false |
108 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T61 |
2 |
| true |
5679 |
1 |
|
T4 |
43 |
|
T24 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
189 |
1 |
|
T4 |
9 |
|
T61 |
11 |
|
T67 |
1 |
| others[1] |
188 |
1 |
|
T4 |
13 |
|
T61 |
7 |
|
T47 |
1 |
| others[2] |
218 |
1 |
|
T4 |
6 |
|
T124 |
1 |
|
T370 |
1 |
| others[3] |
368 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T7 |
1 |
| false |
117 |
1 |
|
T4 |
7 |
|
T61 |
3 |
|
T229 |
7 |
| true |
5753 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1197 |
1 |
|
T4 |
22 |
|
T6 |
10 |
|
T34 |
2 |
| others[1] |
1249 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
21 |
| others[2] |
1220 |
1 |
|
T4 |
21 |
|
T6 |
27 |
|
T34 |
1 |
| others[3] |
2161 |
1 |
|
T3 |
1 |
|
T4 |
33 |
|
T6 |
29 |
| false |
593 |
1 |
|
T4 |
12 |
|
T23 |
1 |
|
T6 |
6 |
| true |
413 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
20 |
| others[1] |
1251 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
11 |
| others[2] |
1264 |
1 |
|
T4 |
21 |
|
T6 |
19 |
|
T34 |
2 |
| others[3] |
2051 |
1 |
|
T3 |
1 |
|
T4 |
26 |
|
T6 |
31 |
| false |
630 |
1 |
|
T4 |
14 |
|
T6 |
12 |
|
T34 |
1 |
| true |
400 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T23 |
1 |
| others[1] |
93 |
1 |
|
T4 |
5 |
|
T124 |
1 |
|
T61 |
2 |
| others[2] |
99 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T68 |
1 |
| others[3] |
159 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T124 |
1 |
| false |
63 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T61 |
3 |
| true |
6319 |
1 |
|
T4 |
73 |
|
T8 |
1 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |