Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T4 |
8 |
|
T9 |
1 |
|
T61 |
8 |
| others[1] |
228 |
1 |
|
T4 |
7 |
|
T8 |
1 |
|
T124 |
1 |
| others[2] |
222 |
1 |
|
T4 |
9 |
|
T24 |
1 |
|
T61 |
8 |
| others[3] |
364 |
1 |
|
T4 |
14 |
|
T370 |
1 |
|
T61 |
12 |
| false |
108 |
1 |
|
T4 |
4 |
|
T61 |
3 |
|
T229 |
6 |
| true |
5675 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
59 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T4 |
19 |
|
T6 |
19 |
|
T34 |
3 |
| others[1] |
1037 |
1 |
|
T4 |
21 |
|
T6 |
16 |
|
T34 |
1 |
| others[2] |
1073 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| others[3] |
1734 |
1 |
|
T4 |
36 |
|
T8 |
1 |
|
T6 |
31 |
| false |
540 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T23 |
1 |
| true |
1397 |
1 |
|
T24 |
1 |
|
T9 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T370 |
1 |
| others[1] |
261 |
1 |
|
T4 |
9 |
|
T8 |
1 |
|
T61 |
10 |
| others[2] |
223 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T61 |
7 |
| others[3] |
360 |
1 |
|
T4 |
18 |
|
T9 |
1 |
|
T7 |
1 |
| false |
105 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T61 |
2 |
| true |
5680 |
1 |
|
T4 |
52 |
|
T23 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T4 |
8 |
|
T61 |
11 |
|
T157 |
1 |
| others[1] |
208 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T61 |
13 |
| others[2] |
190 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
6 |
| others[3] |
345 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T61 |
11 |
| false |
118 |
1 |
|
T4 |
6 |
|
T61 |
2 |
|
T229 |
10 |
| true |
5760 |
1 |
|
T3 |
1 |
|
T4 |
50 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T34 |
2 |
| others[1] |
1266 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T6 |
14 |
| others[2] |
1180 |
1 |
|
T3 |
2 |
|
T4 |
14 |
|
T6 |
20 |
| others[3] |
2058 |
1 |
|
T4 |
38 |
|
T6 |
30 |
|
T34 |
2 |
| false |
657 |
1 |
|
T4 |
10 |
|
T6 |
11 |
|
T66 |
1 |
| true |
423 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T66 |
2 |
| others[1] |
1273 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T6 |
19 |
| others[2] |
1242 |
1 |
|
T4 |
21 |
|
T6 |
19 |
|
T34 |
4 |
| others[3] |
2019 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
25 |
| false |
657 |
1 |
|
T4 |
14 |
|
T23 |
1 |
|
T6 |
12 |
| true |
395 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T61 |
4 |
| others[1] |
122 |
1 |
|
T4 |
4 |
|
T61 |
4 |
|
T157 |
1 |
| others[2] |
101 |
1 |
|
T4 |
9 |
|
T23 |
1 |
|
T61 |
3 |
| others[3] |
151 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T124 |
2 |
| false |
51 |
1 |
|
T4 |
4 |
|
T61 |
1 |
|
T157 |
1 |
| true |
6289 |
1 |
|
T2 |
1 |
|
T4 |
72 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T8 |
1 |
| others[1] |
251 |
1 |
|
T4 |
8 |
|
T61 |
10 |
|
T229 |
10 |
| others[2] |
229 |
1 |
|
T4 |
8 |
|
T24 |
1 |
|
T61 |
8 |
| others[3] |
390 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T23 |
1 |
| false |
122 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T124 |
1 |
| true |
5614 |
1 |
|
T4 |
49 |
|
T9 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T18 |
1 |
| others[1] |
1073 |
1 |
|
T4 |
29 |
|
T9 |
1 |
|
T6 |
15 |
| others[2] |
1031 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| others[3] |
1761 |
1 |
|
T4 |
30 |
|
T23 |
1 |
|
T6 |
27 |
| false |
565 |
1 |
|
T4 |
9 |
|
T6 |
14 |
|
T34 |
1 |
| true |
1347 |
1 |
|
T8 |
1 |
|
T47 |
1 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T4 |
8 |
|
T61 |
9 |
|
T26 |
1 |
| others[1] |
218 |
1 |
|
T4 |
9 |
|
T8 |
1 |
|
T61 |
11 |
| others[2] |
233 |
1 |
|
T4 |
5 |
|
T124 |
1 |
|
T370 |
1 |
| others[3] |
330 |
1 |
|
T4 |
17 |
|
T23 |
1 |
|
T61 |
15 |
| false |
129 |
1 |
|
T4 |
7 |
|
T7 |
1 |
|
T61 |
2 |
| true |
5720 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T61 |
7 |
| others[1] |
209 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T61 |
15 |
| others[2] |
213 |
1 |
|
T4 |
6 |
|
T61 |
7 |
|
T157 |
1 |
| others[3] |
383 |
1 |
|
T4 |
14 |
|
T61 |
20 |
|
T229 |
27 |
| false |
117 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T124 |
1 |
| true |
5691 |
1 |
|
T3 |
1 |
|
T4 |
56 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T4 |
16 |
|
T23 |
1 |
|
T6 |
20 |
| others[1] |
1277 |
1 |
|
T4 |
26 |
|
T6 |
15 |
|
T34 |
2 |
| others[2] |
1245 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
15 |
| others[3] |
2037 |
1 |
|
T3 |
1 |
|
T4 |
27 |
|
T6 |
31 |
| false |
650 |
1 |
|
T4 |
9 |
|
T6 |
12 |
|
T172 |
1 |
| true |
420 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T3 |
2 |
|
T4 |
19 |
|
T6 |
23 |
| others[1] |
1266 |
1 |
|
T4 |
20 |
|
T6 |
13 |
|
T66 |
6 |
| others[2] |
1241 |
1 |
|
T4 |
18 |
|
T6 |
16 |
|
T34 |
1 |
| others[3] |
2002 |
1 |
|
T4 |
35 |
|
T6 |
29 |
|
T34 |
5 |
| false |
645 |
1 |
|
T4 |
9 |
|
T23 |
1 |
|
T6 |
12 |
| true |
403 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T4 |
2 |
|
T124 |
1 |
|
T61 |
3 |
| others[1] |
94 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T61 |
4 |
| others[2] |
107 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T229 |
7 |
| others[3] |
152 |
1 |
|
T4 |
10 |
|
T124 |
1 |
|
T61 |
6 |
| false |
53 |
1 |
|
T4 |
2 |
|
T61 |
3 |
|
T229 |
4 |
| true |
6323 |
1 |
|
T2 |
1 |
|
T4 |
83 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T7 |
1 |
| others[1] |
226 |
1 |
|
T4 |
10 |
|
T61 |
11 |
|
T157 |
1 |
| others[2] |
232 |
1 |
|
T4 |
14 |
|
T61 |
11 |
|
T157 |
1 |
| others[3] |
376 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T23 |
1 |
| false |
116 |
1 |
|
T4 |
3 |
|
T61 |
4 |
|
T47 |
1 |
| true |
5643 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1028 |
1 |
|
T4 |
16 |
|
T8 |
1 |
|
T24 |
1 |
| others[1] |
1081 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T6 |
15 |
| others[2] |
986 |
1 |
|
T4 |
20 |
|
T6 |
17 |
|
T34 |
3 |
| others[3] |
1821 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
36 |
| false |
538 |
1 |
|
T4 |
12 |
|
T6 |
10 |
|
T66 |
1 |
| true |
1379 |
1 |
|
T18 |
1 |
|
T370 |
1 |
|
T47 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T124 |
1 |
| others[1] |
208 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T61 |
14 |
| others[2] |
225 |
1 |
|
T4 |
6 |
|
T61 |
7 |
|
T229 |
12 |
| others[3] |
377 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T61 |
18 |
| false |
95 |
1 |
|
T4 |
6 |
|
T61 |
3 |
|
T229 |
3 |
| true |
5705 |
1 |
|
T2 |
1 |
|
T4 |
54 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T4 |
5 |
|
T7 |
1 |
|
T61 |
9 |
| others[1] |
217 |
1 |
|
T4 |
14 |
|
T61 |
8 |
|
T67 |
1 |
| others[2] |
210 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T61 |
10 |
| others[3] |
373 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T23 |
1 |
| false |
126 |
1 |
|
T4 |
6 |
|
T61 |
6 |
|
T229 |
4 |
| true |
5701 |
1 |
|
T3 |
1 |
|
T4 |
55 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T4 |
24 |
|
T6 |
18 |
|
T66 |
1 |
| others[1] |
1287 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
27 |
| others[2] |
1234 |
1 |
|
T4 |
19 |
|
T6 |
19 |
|
T34 |
1 |
| others[3] |
2039 |
1 |
|
T3 |
2 |
|
T4 |
27 |
|
T6 |
17 |
| false |
634 |
1 |
|
T4 |
12 |
|
T6 |
12 |
|
T34 |
1 |
| true |
426 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T4 |
18 |
|
T6 |
14 |
|
T66 |
5 |
| others[1] |
1226 |
1 |
|
T4 |
18 |
|
T6 |
12 |
|
T34 |
2 |
| others[2] |
1220 |
1 |
|
T3 |
2 |
|
T4 |
21 |
|
T6 |
18 |
| others[3] |
2080 |
1 |
|
T4 |
34 |
|
T6 |
39 |
|
T34 |
2 |
| false |
657 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T6 |
10 |
| true |
401 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T124 |
1 |
| others[1] |
106 |
1 |
|
T4 |
2 |
|
T61 |
7 |
|
T67 |
1 |
| others[2] |
107 |
1 |
|
T4 |
4 |
|
T61 |
6 |
|
T157 |
1 |
| others[3] |
159 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T124 |
1 |
| false |
50 |
1 |
|
T4 |
2 |
|
T61 |
3 |
|
T229 |
2 |
| true |
6321 |
1 |
|
T2 |
1 |
|
T4 |
84 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T4 |
12 |
|
T61 |
4 |
|
T229 |
10 |
| others[1] |
247 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T24 |
1 |
| others[2] |
232 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T61 |
9 |
| others[3] |
358 |
1 |
|
T4 |
14 |
|
T9 |
1 |
|
T124 |
1 |
| false |
125 |
1 |
|
T4 |
3 |
|
T61 |
4 |
|
T229 |
3 |
| true |
5657 |
1 |
|
T3 |
1 |
|
T4 |
55 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T6 |
16 |
| others[1] |
992 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T18 |
1 |
| others[2] |
1039 |
1 |
|
T4 |
21 |
|
T24 |
1 |
|
T6 |
18 |
| others[3] |
1827 |
1 |
|
T3 |
1 |
|
T4 |
31 |
|
T23 |
1 |
| false |
537 |
1 |
|
T4 |
5 |
|
T6 |
7 |
|
T34 |
3 |
| true |
1372 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T370 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
8 |
|
T61 |
10 |
|
T125 |
1 |
| others[1] |
243 |
1 |
|
T4 |
12 |
|
T8 |
1 |
|
T124 |
1 |
| others[2] |
214 |
1 |
|
T4 |
10 |
|
T370 |
1 |
|
T61 |
12 |
| others[3] |
377 |
1 |
|
T4 |
11 |
|
T61 |
17 |
|
T249 |
1 |
| false |
113 |
1 |
|
T4 |
5 |
|
T61 |
2 |
|
T47 |
1 |
| true |
5661 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T4 |
7 |
|
T61 |
8 |
|
T249 |
1 |
| others[1] |
244 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T370 |
1 |
| others[2] |
197 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
7 |
| others[3] |
331 |
1 |
|
T4 |
27 |
|
T61 |
20 |
|
T229 |
12 |
| false |
119 |
1 |
|
T4 |
7 |
|
T61 |
4 |
|
T229 |
4 |
| true |
5743 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
43 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T4 |
13 |
|
T6 |
22 |
|
T66 |
3 |
| others[1] |
1240 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T6 |
18 |
| others[2] |
1239 |
1 |
|
T4 |
23 |
|
T6 |
15 |
|
T34 |
1 |
| others[3] |
2067 |
1 |
|
T4 |
37 |
|
T23 |
1 |
|
T6 |
32 |
| false |
618 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T6 |
6 |
| true |
425 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T6 |
10 |
| others[1] |
1262 |
1 |
|
T4 |
17 |
|
T6 |
15 |
|
T66 |
2 |
| others[2] |
1285 |
1 |
|
T3 |
1 |
|
T4 |
25 |
|
T23 |
1 |
| others[3] |
2011 |
1 |
|
T4 |
32 |
|
T6 |
35 |
|
T34 |
3 |
| false |
620 |
1 |
|
T4 |
7 |
|
T6 |
12 |
|
T66 |
1 |
| true |
407 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T4 |
1 |
|
T61 |
3 |
|
T157 |
1 |
| others[1] |
107 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T61 |
9 |
| others[2] |
105 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T61 |
5 |
| others[3] |
177 |
1 |
|
T4 |
4 |
|
T124 |
2 |
|
T61 |
6 |
| false |
52 |
1 |
|
T4 |
3 |
|
T61 |
5 |
|
T229 |
1 |
| true |
6295 |
1 |
|
T2 |
1 |
|
T4 |
83 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T4 |
12 |
|
T61 |
3 |
|
T229 |
11 |
| others[1] |
211 |
1 |
|
T4 |
6 |
|
T61 |
9 |
|
T47 |
1 |
| others[2] |
250 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T24 |
1 |
| others[3] |
359 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
12 |
| false |
112 |
1 |
|
T4 |
4 |
|
T8 |
1 |
|
T61 |
3 |
| true |
5678 |
1 |
|
T4 |
53 |
|
T23 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1074 |
1 |
|
T4 |
20 |
|
T6 |
18 |
|
T34 |
3 |
| others[1] |
1039 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T6 |
14 |
| others[2] |
1053 |
1 |
|
T4 |
25 |
|
T6 |
21 |
|
T34 |
1 |
| others[3] |
1756 |
1 |
|
T4 |
26 |
|
T8 |
1 |
|
T23 |
1 |
| false |
547 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T6 |
9 |
| true |
1364 |
1 |
|
T2 |
1 |
|
T9 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T61 |
10 |
| others[1] |
194 |
1 |
|
T4 |
6 |
|
T61 |
10 |
|
T125 |
1 |
| others[2] |
186 |
1 |
|
T4 |
12 |
|
T61 |
8 |
|
T47 |
1 |
| others[3] |
377 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| false |
121 |
1 |
|
T4 |
3 |
|
T61 |
5 |
|
T229 |
9 |
| true |
5737 |
1 |
|
T4 |
54 |
|
T8 |
1 |
|
T23 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |