Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T4 |
7 |
|
T124 |
1 |
|
T61 |
10 |
| others[1] |
236 |
1 |
|
T4 |
11 |
|
T61 |
6 |
|
T157 |
1 |
| others[2] |
213 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T7 |
1 |
| others[3] |
355 |
1 |
|
T4 |
21 |
|
T61 |
16 |
|
T157 |
1 |
| false |
115 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T61 |
6 |
| true |
5699 |
1 |
|
T3 |
1 |
|
T4 |
48 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T6 |
21 |
| others[1] |
1210 |
1 |
|
T4 |
23 |
|
T6 |
26 |
|
T34 |
1 |
| others[2] |
1210 |
1 |
|
T4 |
13 |
|
T6 |
21 |
|
T34 |
1 |
| others[3] |
2121 |
1 |
|
T3 |
1 |
|
T4 |
35 |
|
T23 |
1 |
| false |
649 |
1 |
|
T4 |
10 |
|
T6 |
7 |
|
T34 |
1 |
| true |
421 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T4 |
21 |
|
T6 |
15 |
|
T66 |
2 |
| others[1] |
1250 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T6 |
20 |
| others[2] |
1197 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T6 |
21 |
| others[3] |
2076 |
1 |
|
T3 |
1 |
|
T4 |
35 |
|
T6 |
22 |
| false |
657 |
1 |
|
T4 |
8 |
|
T6 |
15 |
|
T34 |
1 |
| true |
416 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T61 |
6 |
| others[1] |
106 |
1 |
|
T4 |
4 |
|
T124 |
1 |
|
T61 |
5 |
| others[2] |
104 |
1 |
|
T4 |
4 |
|
T61 |
4 |
|
T68 |
1 |
| others[3] |
160 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T61 |
6 |
| false |
71 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T124 |
1 |
| true |
6295 |
1 |
|
T4 |
85 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T4 |
8 |
|
T61 |
13 |
|
T229 |
11 |
| others[1] |
233 |
1 |
|
T4 |
9 |
|
T61 |
9 |
|
T125 |
1 |
| others[2] |
242 |
1 |
|
T4 |
12 |
|
T8 |
1 |
|
T7 |
1 |
| others[3] |
354 |
1 |
|
T4 |
13 |
|
T61 |
19 |
|
T47 |
1 |
| false |
132 |
1 |
|
T4 |
2 |
|
T61 |
4 |
|
T229 |
9 |
| true |
5630 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T4 |
20 |
|
T24 |
1 |
|
T6 |
22 |
| others[1] |
1006 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T66 |
3 |
| others[2] |
1073 |
1 |
|
T2 |
1 |
|
T4 |
20 |
|
T6 |
16 |
| others[3] |
1768 |
1 |
|
T3 |
2 |
|
T4 |
32 |
|
T8 |
1 |
| false |
573 |
1 |
|
T4 |
10 |
|
T6 |
12 |
|
T34 |
3 |
| true |
1374 |
1 |
|
T9 |
1 |
|
T18 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T7 |
1 |
| others[1] |
235 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T23 |
1 |
| others[2] |
219 |
1 |
|
T4 |
10 |
|
T8 |
1 |
|
T61 |
9 |
| others[3] |
367 |
1 |
|
T4 |
11 |
|
T61 |
21 |
|
T229 |
19 |
| false |
122 |
1 |
|
T4 |
4 |
|
T61 |
6 |
|
T157 |
1 |
| true |
5679 |
1 |
|
T3 |
1 |
|
T4 |
54 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T4 |
8 |
|
T124 |
1 |
|
T61 |
9 |
| others[1] |
216 |
1 |
|
T4 |
16 |
|
T61 |
5 |
|
T229 |
9 |
| others[2] |
240 |
1 |
|
T4 |
7 |
|
T7 |
1 |
|
T124 |
1 |
| others[3] |
364 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T23 |
1 |
| false |
92 |
1 |
|
T4 |
3 |
|
T61 |
5 |
|
T157 |
1 |
| true |
5720 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T6 |
15 |
| others[1] |
1201 |
1 |
|
T4 |
18 |
|
T6 |
20 |
|
T34 |
2 |
| others[2] |
1221 |
1 |
|
T4 |
18 |
|
T23 |
1 |
|
T6 |
11 |
| others[3] |
2105 |
1 |
|
T3 |
1 |
|
T4 |
37 |
|
T6 |
30 |
| false |
659 |
1 |
|
T4 |
14 |
|
T6 |
17 |
|
T34 |
1 |
| true |
425 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T4 |
26 |
|
T23 |
1 |
|
T6 |
21 |
| others[1] |
1252 |
1 |
|
T4 |
19 |
|
T6 |
22 |
|
T34 |
1 |
| others[2] |
1243 |
1 |
|
T4 |
20 |
|
T6 |
18 |
|
T66 |
7 |
| others[3] |
2094 |
1 |
|
T3 |
1 |
|
T4 |
30 |
|
T6 |
27 |
| false |
594 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T6 |
5 |
| true |
406 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T4 |
4 |
|
T124 |
1 |
|
T61 |
3 |
| others[1] |
102 |
1 |
|
T4 |
6 |
|
T61 |
4 |
|
T229 |
4 |
| others[2] |
106 |
1 |
|
T4 |
8 |
|
T370 |
1 |
|
T61 |
2 |
| others[3] |
176 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
8 |
| false |
66 |
1 |
|
T4 |
4 |
|
T61 |
3 |
|
T229 |
2 |
| true |
6279 |
1 |
|
T4 |
71 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T4 |
8 |
|
T61 |
9 |
|
T157 |
1 |
| others[1] |
203 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T370 |
1 |
| others[2] |
229 |
1 |
|
T4 |
10 |
|
T61 |
15 |
|
T67 |
1 |
| others[3] |
371 |
1 |
|
T4 |
19 |
|
T8 |
1 |
|
T24 |
1 |
| false |
121 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T124 |
1 |
| true |
5704 |
1 |
|
T3 |
1 |
|
T4 |
50 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T4 |
14 |
|
T6 |
19 |
|
T66 |
1 |
| others[1] |
1047 |
1 |
|
T4 |
21 |
|
T8 |
1 |
|
T23 |
1 |
| others[2] |
1031 |
1 |
|
T4 |
22 |
|
T24 |
1 |
|
T6 |
23 |
| others[3] |
1735 |
1 |
|
T3 |
1 |
|
T4 |
32 |
|
T18 |
1 |
| false |
539 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T6 |
7 |
| true |
1416 |
1 |
|
T2 |
1 |
|
T9 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T61 |
10 |
| others[1] |
203 |
1 |
|
T4 |
14 |
|
T61 |
10 |
|
T229 |
12 |
| others[2] |
213 |
1 |
|
T4 |
8 |
|
T61 |
9 |
|
T67 |
1 |
| others[3] |
394 |
1 |
|
T4 |
14 |
|
T7 |
1 |
|
T61 |
15 |
| false |
121 |
1 |
|
T4 |
5 |
|
T61 |
6 |
|
T229 |
2 |
| true |
5684 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
183 |
1 |
|
T4 |
10 |
|
T61 |
8 |
|
T229 |
8 |
| others[1] |
216 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T61 |
12 |
| others[2] |
209 |
1 |
|
T4 |
10 |
|
T61 |
9 |
|
T229 |
12 |
| others[3] |
379 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T124 |
1 |
| false |
106 |
1 |
|
T4 |
5 |
|
T61 |
5 |
|
T229 |
4 |
| true |
5740 |
1 |
|
T3 |
1 |
|
T4 |
52 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1232 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T34 |
2 |
| others[1] |
1228 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T6 |
22 |
| others[2] |
1229 |
1 |
|
T4 |
19 |
|
T6 |
17 |
|
T34 |
1 |
| others[3] |
2021 |
1 |
|
T3 |
1 |
|
T4 |
30 |
|
T23 |
1 |
| false |
683 |
1 |
|
T4 |
13 |
|
T6 |
7 |
|
T66 |
1 |
| true |
440 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T4 |
16 |
|
T6 |
18 |
|
T34 |
1 |
| others[1] |
1220 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
24 |
| others[2] |
1206 |
1 |
|
T4 |
22 |
|
T23 |
1 |
|
T6 |
21 |
| others[3] |
2113 |
1 |
|
T4 |
29 |
|
T6 |
24 |
|
T66 |
5 |
| false |
666 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
6 |
| true |
406 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T4 |
6 |
|
T124 |
1 |
|
T61 |
6 |
| others[1] |
113 |
1 |
|
T4 |
1 |
|
T61 |
4 |
|
T157 |
1 |
| others[2] |
111 |
1 |
|
T4 |
8 |
|
T61 |
3 |
|
T157 |
1 |
| others[3] |
161 |
1 |
|
T3 |
2 |
|
T4 |
6 |
|
T23 |
1 |
| false |
54 |
1 |
|
T4 |
2 |
|
T61 |
2 |
|
T229 |
2 |
| true |
6276 |
1 |
|
T2 |
1 |
|
T4 |
78 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T4 |
13 |
|
T124 |
1 |
|
T61 |
9 |
| others[1] |
229 |
1 |
|
T4 |
9 |
|
T61 |
14 |
|
T157 |
1 |
| others[2] |
223 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T61 |
7 |
| others[3] |
363 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T61 |
21 |
| false |
110 |
1 |
|
T4 |
7 |
|
T370 |
1 |
|
T61 |
4 |
| true |
5650 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
999 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T24 |
1 |
| others[1] |
1021 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T6 |
10 |
| others[2] |
1057 |
1 |
|
T4 |
13 |
|
T6 |
24 |
|
T66 |
3 |
| others[3] |
1806 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T23 |
1 |
| false |
546 |
1 |
|
T4 |
9 |
|
T6 |
11 |
|
T34 |
1 |
| true |
1404 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T4 |
11 |
|
T9 |
1 |
|
T7 |
1 |
| others[1] |
225 |
1 |
|
T4 |
10 |
|
T61 |
13 |
|
T26 |
1 |
| others[2] |
230 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
11 |
| others[3] |
357 |
1 |
|
T4 |
11 |
|
T61 |
22 |
|
T125 |
1 |
| false |
115 |
1 |
|
T4 |
8 |
|
T61 |
3 |
|
T229 |
7 |
| true |
5663 |
1 |
|
T4 |
50 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
187 |
1 |
|
T4 |
6 |
|
T124 |
1 |
|
T61 |
6 |
| others[1] |
210 |
1 |
|
T4 |
11 |
|
T61 |
9 |
|
T229 |
10 |
| others[2] |
239 |
1 |
|
T4 |
17 |
|
T7 |
1 |
|
T61 |
6 |
| others[3] |
348 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T61 |
17 |
| false |
104 |
1 |
|
T4 |
4 |
|
T61 |
7 |
|
T229 |
5 |
| true |
5745 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T4 |
13 |
|
T23 |
1 |
|
T6 |
22 |
| others[1] |
1239 |
1 |
|
T4 |
24 |
|
T6 |
13 |
|
T34 |
2 |
| others[2] |
1225 |
1 |
|
T4 |
18 |
|
T6 |
18 |
|
T34 |
2 |
| others[3] |
2053 |
1 |
|
T3 |
2 |
|
T4 |
38 |
|
T6 |
26 |
| false |
657 |
1 |
|
T4 |
8 |
|
T6 |
14 |
|
T66 |
1 |
| true |
412 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T6 |
18 |
| others[1] |
1162 |
1 |
|
T3 |
1 |
|
T4 |
15 |
|
T6 |
22 |
| others[2] |
1280 |
1 |
|
T4 |
25 |
|
T6 |
19 |
|
T34 |
1 |
| others[3] |
2077 |
1 |
|
T4 |
28 |
|
T6 |
22 |
|
T34 |
1 |
| false |
640 |
1 |
|
T4 |
11 |
|
T23 |
1 |
|
T6 |
12 |
| true |
407 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T61 |
3 |
| others[1] |
99 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T124 |
1 |
| others[2] |
91 |
1 |
|
T4 |
2 |
|
T61 |
3 |
|
T229 |
4 |
| others[3] |
172 |
1 |
|
T4 |
5 |
|
T124 |
1 |
|
T61 |
4 |
| false |
51 |
1 |
|
T61 |
1 |
|
T229 |
3 |
|
T153 |
1 |
| true |
6304 |
1 |
|
T2 |
1 |
|
T4 |
87 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T4 |
12 |
|
T24 |
1 |
|
T9 |
1 |
| others[1] |
235 |
1 |
|
T4 |
7 |
|
T61 |
12 |
|
T47 |
1 |
| others[2] |
224 |
1 |
|
T4 |
6 |
|
T61 |
10 |
|
T229 |
8 |
| others[3] |
379 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T61 |
20 |
| false |
109 |
1 |
|
T4 |
8 |
|
T23 |
1 |
|
T7 |
1 |
| true |
5663 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1064 |
1 |
|
T4 |
21 |
|
T6 |
20 |
|
T34 |
1 |
| others[1] |
1004 |
1 |
|
T4 |
21 |
|
T6 |
19 |
|
T34 |
1 |
| others[2] |
1059 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T8 |
1 |
| others[3] |
1786 |
1 |
|
T3 |
1 |
|
T4 |
28 |
|
T6 |
24 |
| false |
585 |
1 |
|
T4 |
9 |
|
T23 |
1 |
|
T6 |
10 |
| true |
1335 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T4 |
9 |
|
T23 |
1 |
|
T61 |
9 |
| others[1] |
242 |
1 |
|
T4 |
10 |
|
T61 |
10 |
|
T125 |
1 |
| others[2] |
231 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T61 |
8 |
| others[3] |
351 |
1 |
|
T4 |
14 |
|
T61 |
12 |
|
T47 |
1 |
| false |
109 |
1 |
|
T4 |
6 |
|
T8 |
1 |
|
T61 |
3 |
| true |
5685 |
1 |
|
T3 |
2 |
|
T4 |
54 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T4 |
8 |
|
T61 |
11 |
|
T229 |
11 |
| others[1] |
216 |
1 |
|
T4 |
12 |
|
T23 |
1 |
|
T61 |
8 |
| others[2] |
191 |
1 |
|
T4 |
5 |
|
T61 |
10 |
|
T229 |
8 |
| others[3] |
336 |
1 |
|
T4 |
22 |
|
T124 |
1 |
|
T61 |
19 |
| false |
134 |
1 |
|
T4 |
5 |
|
T61 |
7 |
|
T229 |
4 |
| true |
5743 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
16 |
|
T6 |
14 |
|
T34 |
1 |
| others[1] |
1216 |
1 |
|
T4 |
23 |
|
T6 |
18 |
|
T34 |
1 |
| others[2] |
1186 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T23 |
1 |
| others[3] |
2135 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T6 |
30 |
| false |
640 |
1 |
|
T4 |
10 |
|
T6 |
8 |
|
T34 |
1 |
| true |
433 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T374 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
4 |
1 |
|
T352 |
1 |
|
T368 |
1 |
|
T375 |
1 |
| others[2] |
5 |
1 |
|
T376 |
1 |
|
T377 |
1 |
|
T378 |
1 |
| others[3] |
4 |
1 |
|
T116 |
1 |
|
T379 |
1 |
|
T380 |
1 |
| false |
6 |
1 |
|
T365 |
1 |
|
T381 |
1 |
|
T382 |
1 |
| true |
26 |
1 |
|
T5 |
1 |
|
T62 |
1 |
|
T168 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |