Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10564 |
1 |
|
T4 |
15 |
|
T17 |
2 |
|
T6 |
18 |
| others[1] |
791 |
1 |
|
T4 |
21 |
|
T6 |
21 |
|
T34 |
2 |
| others[2] |
762 |
1 |
|
T3 |
2 |
|
T4 |
14 |
|
T6 |
21 |
| others[3] |
1334 |
1 |
|
T4 |
38 |
|
T23 |
1 |
|
T6 |
27 |
| false |
404 |
1 |
|
T4 |
13 |
|
T6 |
6 |
|
T61 |
8 |
| true |
512 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2444 |
1 |
|
T4 |
14 |
|
T6 |
19 |
|
T25 |
19 |
| others[1] |
2469 |
1 |
|
T3 |
1 |
|
T4 |
15 |
|
T6 |
13 |
| others[2] |
2534 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T6 |
16 |
| others[3] |
4115 |
1 |
|
T4 |
17 |
|
T17 |
2 |
|
T6 |
32 |
| false |
1276 |
1 |
|
T4 |
5 |
|
T6 |
13 |
|
T25 |
9 |
| true |
1529 |
1 |
|
T2 |
1 |
|
T4 |
42 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10037 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
275 |
1 |
|
T4 |
4 |
|
T7 |
1 |
|
T34 |
1 |
| others[2] |
276 |
1 |
|
T4 |
10 |
|
T24 |
1 |
|
T34 |
1 |
| others[3] |
441 |
1 |
|
T4 |
12 |
|
T34 |
1 |
|
T61 |
20 |
| false |
127 |
1 |
|
T4 |
3 |
|
T61 |
2 |
|
T229 |
3 |
| true |
3211 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10284 |
1 |
|
T4 |
14 |
|
T24 |
1 |
|
T17 |
2 |
| others[1] |
500 |
1 |
|
T3 |
2 |
|
T4 |
12 |
|
T6 |
7 |
| others[2] |
432 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T6 |
11 |
| others[3] |
770 |
1 |
|
T4 |
13 |
|
T23 |
1 |
|
T6 |
20 |
| false |
224 |
1 |
|
T4 |
7 |
|
T6 |
2 |
|
T66 |
1 |
| true |
2157 |
1 |
|
T4 |
46 |
|
T8 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10031 |
1 |
|
T4 |
14 |
|
T8 |
1 |
|
T17 |
2 |
| others[1] |
244 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T34 |
1 |
| others[2] |
283 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T61 |
15 |
| others[3] |
410 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T34 |
2 |
| false |
127 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T127 |
1 |
| true |
3272 |
1 |
|
T3 |
1 |
|
T4 |
45 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10019 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
244 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T61 |
10 |
| others[2] |
284 |
1 |
|
T4 |
8 |
|
T61 |
8 |
|
T51 |
1 |
| others[3] |
422 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T23 |
1 |
| false |
144 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T61 |
7 |
| true |
3254 |
1 |
|
T4 |
48 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10586 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T17 |
2 |
| others[1] |
761 |
1 |
|
T4 |
17 |
|
T6 |
22 |
|
T66 |
4 |
| others[2] |
846 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T6 |
17 |
| others[3] |
1281 |
1 |
|
T4 |
33 |
|
T6 |
25 |
|
T34 |
1 |
| false |
390 |
1 |
|
T4 |
8 |
|
T6 |
10 |
|
T66 |
1 |
| true |
503 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10510 |
1 |
|
T4 |
19 |
|
T17 |
2 |
|
T6 |
16 |
| others[1] |
778 |
1 |
|
T4 |
19 |
|
T6 |
20 |
|
T66 |
3 |
| others[2] |
797 |
1 |
|
T4 |
22 |
|
T23 |
1 |
|
T6 |
18 |
| others[3] |
1301 |
1 |
|
T4 |
29 |
|
T6 |
24 |
|
T66 |
3 |
| false |
417 |
1 |
|
T4 |
12 |
|
T6 |
15 |
|
T66 |
1 |
| true |
539 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2500 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T6 |
17 |
| others[1] |
2541 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T6 |
18 |
| others[2] |
2521 |
1 |
|
T4 |
14 |
|
T17 |
1 |
|
T6 |
20 |
| others[3] |
4111 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T17 |
1 |
| false |
1281 |
1 |
|
T4 |
5 |
|
T6 |
8 |
|
T25 |
15 |
| true |
1388 |
1 |
|
T4 |
54 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10031 |
1 |
|
T4 |
5 |
|
T24 |
1 |
|
T17 |
2 |
| others[1] |
250 |
1 |
|
T4 |
14 |
|
T34 |
2 |
|
T124 |
1 |
| others[2] |
247 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T61 |
12 |
| others[3] |
424 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T9 |
1 |
| false |
150 |
1 |
|
T4 |
3 |
|
T61 |
11 |
|
T229 |
7 |
| true |
3240 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10222 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T18 |
1 |
| others[1] |
438 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T24 |
1 |
| others[2] |
466 |
1 |
|
T4 |
12 |
|
T6 |
14 |
|
T34 |
1 |
| others[3] |
794 |
1 |
|
T4 |
21 |
|
T6 |
17 |
|
T7 |
1 |
| false |
205 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T23 |
1 |
| true |
2217 |
1 |
|
T2 |
1 |
|
T4 |
50 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
249 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T34 |
1 |
| others[2] |
241 |
1 |
|
T4 |
7 |
|
T34 |
1 |
|
T61 |
8 |
| others[3] |
446 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T7 |
1 |
| false |
155 |
1 |
|
T4 |
7 |
|
T23 |
1 |
|
T61 |
7 |
| true |
3226 |
1 |
|
T3 |
1 |
|
T4 |
58 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10022 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
243 |
1 |
|
T4 |
10 |
|
T61 |
4 |
|
T38 |
2 |
| others[2] |
263 |
1 |
|
T4 |
12 |
|
T34 |
1 |
|
T61 |
14 |
| others[3] |
375 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T23 |
1 |
| false |
130 |
1 |
|
T4 |
8 |
|
T61 |
4 |
|
T127 |
1 |
| true |
3309 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10565 |
1 |
|
T4 |
21 |
|
T17 |
2 |
|
T6 |
21 |
| others[1] |
823 |
1 |
|
T4 |
20 |
|
T23 |
1 |
|
T6 |
23 |
| others[2] |
779 |
1 |
|
T4 |
18 |
|
T6 |
19 |
|
T66 |
3 |
| others[3] |
1247 |
1 |
|
T3 |
1 |
|
T4 |
30 |
|
T6 |
25 |
| false |
413 |
1 |
|
T4 |
12 |
|
T6 |
5 |
|
T61 |
13 |
| true |
515 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10533 |
1 |
|
T4 |
20 |
|
T17 |
2 |
|
T6 |
19 |
| others[1] |
788 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T6 |
13 |
| others[2] |
780 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
15 |
| others[3] |
1293 |
1 |
|
T4 |
32 |
|
T6 |
36 |
|
T34 |
3 |
| false |
411 |
1 |
|
T4 |
12 |
|
T6 |
10 |
|
T66 |
3 |
| true |
537 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2549 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T6 |
24 |
| others[1] |
2494 |
1 |
|
T4 |
14 |
|
T6 |
20 |
|
T25 |
17 |
| others[2] |
2465 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T6 |
16 |
| others[3] |
4146 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
24 |
| false |
1248 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T6 |
9 |
| true |
1440 |
1 |
|
T2 |
1 |
|
T4 |
45 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10042 |
1 |
|
T4 |
13 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
236 |
1 |
|
T4 |
11 |
|
T61 |
10 |
|
T26 |
1 |
| others[2] |
325 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T8 |
1 |
| others[3] |
420 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T34 |
1 |
| false |
126 |
1 |
|
T4 |
4 |
|
T34 |
1 |
|
T370 |
1 |
| true |
3193 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10234 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T8 |
1 |
| others[1] |
437 |
1 |
|
T3 |
2 |
|
T4 |
6 |
|
T6 |
11 |
| others[2] |
468 |
1 |
|
T4 |
10 |
|
T6 |
10 |
|
T66 |
1 |
| others[3] |
809 |
1 |
|
T4 |
13 |
|
T23 |
1 |
|
T24 |
1 |
| false |
217 |
1 |
|
T4 |
4 |
|
T6 |
3 |
|
T34 |
3 |
| true |
2177 |
1 |
|
T4 |
61 |
|
T9 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10035 |
1 |
|
T4 |
12 |
|
T23 |
1 |
|
T17 |
2 |
| others[1] |
246 |
1 |
|
T4 |
9 |
|
T8 |
1 |
|
T34 |
1 |
| others[2] |
267 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T61 |
10 |
| others[3] |
447 |
1 |
|
T4 |
18 |
|
T370 |
1 |
|
T61 |
16 |
| false |
122 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T61 |
5 |
| true |
3225 |
1 |
|
T2 |
1 |
|
T4 |
51 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T17 |
2 |
| others[1] |
240 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
9 |
| others[2] |
252 |
1 |
|
T4 |
10 |
|
T61 |
8 |
|
T173 |
1 |
| others[3] |
457 |
1 |
|
T4 |
15 |
|
T23 |
1 |
|
T34 |
2 |
| false |
124 |
1 |
|
T4 |
11 |
|
T61 |
6 |
|
T47 |
1 |
| true |
3244 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10542 |
1 |
|
T4 |
21 |
|
T17 |
2 |
|
T6 |
22 |
| others[1] |
784 |
1 |
|
T4 |
21 |
|
T23 |
1 |
|
T6 |
22 |
| others[2] |
783 |
1 |
|
T4 |
21 |
|
T6 |
7 |
|
T34 |
1 |
| others[3] |
1337 |
1 |
|
T4 |
28 |
|
T6 |
27 |
|
T66 |
6 |
| false |
385 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T6 |
15 |
| true |
511 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10571 |
1 |
|
T4 |
27 |
|
T23 |
1 |
|
T17 |
2 |
| others[1] |
781 |
1 |
|
T4 |
17 |
|
T6 |
10 |
|
T66 |
4 |
| others[2] |
784 |
1 |
|
T4 |
19 |
|
T6 |
19 |
|
T66 |
2 |
| others[3] |
1330 |
1 |
|
T3 |
1 |
|
T4 |
31 |
|
T6 |
26 |
| false |
379 |
1 |
|
T4 |
7 |
|
T6 |
10 |
|
T34 |
1 |
| true |
497 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2467 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
23 |
| others[1] |
2513 |
1 |
|
T4 |
7 |
|
T6 |
18 |
|
T25 |
21 |
| others[2] |
2492 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T17 |
1 |
| others[3] |
4053 |
1 |
|
T4 |
12 |
|
T6 |
28 |
|
T25 |
29 |
| false |
1324 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T6 |
7 |
| true |
1493 |
1 |
|
T2 |
1 |
|
T4 |
58 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10027 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T9 |
1 |
| others[1] |
242 |
1 |
|
T4 |
5 |
|
T34 |
1 |
|
T61 |
5 |
| others[2] |
266 |
1 |
|
T4 |
7 |
|
T61 |
13 |
|
T127 |
1 |
| others[3] |
480 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T34 |
2 |
| false |
142 |
1 |
|
T4 |
8 |
|
T23 |
1 |
|
T124 |
1 |
| true |
3185 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10240 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T17 |
2 |
| others[1] |
463 |
1 |
|
T4 |
7 |
|
T6 |
11 |
|
T34 |
2 |
| others[2] |
442 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T6 |
11 |
| others[3] |
760 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T18 |
1 |
| false |
266 |
1 |
|
T4 |
6 |
|
T24 |
1 |
|
T9 |
1 |
| true |
2171 |
1 |
|
T4 |
49 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10032 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T17 |
2 |
| others[1] |
240 |
1 |
|
T4 |
9 |
|
T61 |
12 |
|
T26 |
1 |
| others[2] |
240 |
1 |
|
T4 |
8 |
|
T23 |
1 |
|
T172 |
1 |
| others[3] |
432 |
1 |
|
T4 |
10 |
|
T8 |
1 |
|
T34 |
1 |
| false |
139 |
1 |
|
T4 |
7 |
|
T34 |
1 |
|
T61 |
3 |
| true |
3259 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T17 |
2 |
| others[1] |
257 |
1 |
|
T4 |
10 |
|
T34 |
1 |
|
T61 |
5 |
| others[2] |
256 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T34 |
2 |
| others[3] |
403 |
1 |
|
T4 |
17 |
|
T23 |
1 |
|
T7 |
1 |
| false |
121 |
1 |
|
T4 |
6 |
|
T61 |
4 |
|
T38 |
1 |
| true |
3280 |
1 |
|
T3 |
1 |
|
T4 |
52 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10554 |
1 |
|
T4 |
14 |
|
T17 |
2 |
|
T6 |
16 |
| others[1] |
793 |
1 |
|
T4 |
11 |
|
T6 |
16 |
|
T34 |
1 |
| others[2] |
740 |
1 |
|
T4 |
18 |
|
T6 |
21 |
|
T34 |
2 |
| others[3] |
1311 |
1 |
|
T3 |
1 |
|
T4 |
46 |
|
T6 |
32 |
| false |
425 |
1 |
|
T4 |
12 |
|
T23 |
1 |
|
T6 |
8 |
| true |
519 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10574 |
1 |
|
T4 |
19 |
|
T17 |
2 |
|
T6 |
20 |
| others[1] |
764 |
1 |
|
T4 |
25 |
|
T6 |
14 |
|
T34 |
1 |
| others[2] |
819 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
21 |
| others[3] |
1261 |
1 |
|
T4 |
31 |
|
T23 |
1 |
|
T6 |
30 |
| false |
394 |
1 |
|
T4 |
5 |
|
T6 |
8 |
|
T66 |
1 |
| true |
530 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2414 |
1 |
|
T4 |
14 |
|
T6 |
17 |
|
T25 |
15 |
| others[1] |
2480 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T17 |
2 |
| others[2] |
2481 |
1 |
|
T4 |
8 |
|
T6 |
20 |
|
T25 |
17 |
| others[3] |
4247 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
26 |
| false |
1292 |
1 |
|
T4 |
5 |
|
T6 |
5 |
|
T25 |
10 |
| true |
1428 |
1 |
|
T2 |
1 |
|
T4 |
37 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10040 |
1 |
|
T4 |
9 |
|
T8 |
1 |
|
T23 |
1 |
| others[1] |
255 |
1 |
|
T4 |
3 |
|
T61 |
14 |
|
T26 |
1 |
| others[2] |
290 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T172 |
1 |
| others[3] |
453 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T124 |
1 |
| false |
120 |
1 |
|
T4 |
4 |
|
T61 |
5 |
|
T229 |
9 |
| true |
3184 |
1 |
|
T3 |
1 |
|
T4 |
64 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |