Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10222 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T6 |
8 |
| others[1] |
472 |
1 |
|
T4 |
15 |
|
T6 |
8 |
|
T34 |
1 |
| others[2] |
487 |
1 |
|
T4 |
9 |
|
T6 |
7 |
|
T66 |
1 |
| others[3] |
768 |
1 |
|
T4 |
24 |
|
T6 |
18 |
|
T34 |
2 |
| false |
221 |
1 |
|
T3 |
2 |
|
T4 |
4 |
|
T6 |
5 |
| true |
2172 |
1 |
|
T2 |
1 |
|
T4 |
45 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10059 |
1 |
|
T4 |
14 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
253 |
1 |
|
T4 |
9 |
|
T124 |
1 |
|
T61 |
7 |
| others[2] |
261 |
1 |
|
T4 |
10 |
|
T61 |
9 |
|
T173 |
1 |
| others[3] |
393 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T23 |
1 |
| false |
145 |
1 |
|
T4 |
7 |
|
T34 |
1 |
|
T61 |
7 |
| true |
3231 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10044 |
1 |
|
T4 |
7 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
251 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T34 |
1 |
| others[2] |
254 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
| others[3] |
383 |
1 |
|
T4 |
17 |
|
T61 |
18 |
|
T47 |
1 |
| false |
130 |
1 |
|
T4 |
3 |
|
T23 |
1 |
|
T7 |
1 |
| true |
3280 |
1 |
|
T4 |
55 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10616 |
1 |
|
T4 |
27 |
|
T17 |
2 |
|
T6 |
21 |
| others[1] |
796 |
1 |
|
T4 |
20 |
|
T6 |
12 |
|
T34 |
1 |
| others[2] |
775 |
1 |
|
T4 |
17 |
|
T6 |
22 |
|
T66 |
4 |
| others[3] |
1274 |
1 |
|
T4 |
33 |
|
T23 |
1 |
|
T6 |
30 |
| false |
365 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T6 |
8 |
| true |
516 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10559 |
1 |
|
T4 |
24 |
|
T17 |
2 |
|
T6 |
16 |
| others[1] |
837 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
21 |
| others[2] |
760 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T6 |
20 |
| others[3] |
1279 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T6 |
32 |
| false |
389 |
1 |
|
T4 |
10 |
|
T6 |
4 |
|
T66 |
1 |
| true |
518 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2456 |
1 |
|
T4 |
11 |
|
T6 |
23 |
|
T25 |
18 |
| others[1] |
2457 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T6 |
26 |
| others[2] |
2478 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T6 |
19 |
| others[3] |
4162 |
1 |
|
T4 |
15 |
|
T6 |
17 |
|
T25 |
33 |
| false |
1296 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T6 |
8 |
| true |
1493 |
1 |
|
T2 |
1 |
|
T4 |
56 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10045 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T23 |
1 |
| others[1] |
258 |
1 |
|
T4 |
10 |
|
T61 |
5 |
|
T201 |
1 |
| others[2] |
252 |
1 |
|
T4 |
9 |
|
T61 |
8 |
|
T67 |
1 |
| others[3] |
428 |
1 |
|
T4 |
15 |
|
T61 |
13 |
|
T157 |
2 |
| false |
120 |
1 |
|
T4 |
8 |
|
T61 |
2 |
|
T229 |
4 |
| true |
3239 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10236 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T17 |
2 |
| others[1] |
480 |
1 |
|
T4 |
7 |
|
T6 |
13 |
|
T66 |
1 |
| others[2] |
467 |
1 |
|
T4 |
13 |
|
T6 |
9 |
|
T34 |
2 |
| others[3] |
771 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
16 |
| false |
216 |
1 |
|
T4 |
4 |
|
T6 |
4 |
|
T34 |
1 |
| true |
2172 |
1 |
|
T2 |
1 |
|
T4 |
51 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10030 |
1 |
|
T4 |
9 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
265 |
1 |
|
T4 |
6 |
|
T61 |
6 |
|
T51 |
1 |
| others[2] |
282 |
1 |
|
T4 |
8 |
|
T23 |
1 |
|
T124 |
1 |
| others[3] |
435 |
1 |
|
T4 |
21 |
|
T34 |
2 |
|
T61 |
14 |
| false |
110 |
1 |
|
T4 |
3 |
|
T61 |
3 |
|
T47 |
1 |
| true |
3220 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T17 |
2 |
| others[1] |
254 |
1 |
|
T4 |
5 |
|
T34 |
1 |
|
T61 |
8 |
| others[2] |
265 |
1 |
|
T4 |
15 |
|
T61 |
7 |
|
T126 |
1 |
| others[3] |
430 |
1 |
|
T4 |
16 |
|
T23 |
1 |
|
T61 |
15 |
| false |
126 |
1 |
|
T4 |
2 |
|
T34 |
2 |
|
T61 |
6 |
| true |
3278 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10567 |
1 |
|
T4 |
13 |
|
T17 |
2 |
|
T6 |
25 |
| others[1] |
802 |
1 |
|
T4 |
27 |
|
T23 |
1 |
|
T6 |
15 |
| others[2] |
783 |
1 |
|
T4 |
19 |
|
T6 |
22 |
|
T34 |
1 |
| others[3] |
1290 |
1 |
|
T4 |
32 |
|
T6 |
20 |
|
T66 |
6 |
| false |
393 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T6 |
11 |
| true |
507 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10598 |
1 |
|
T4 |
26 |
|
T17 |
2 |
|
T6 |
18 |
| others[1] |
791 |
1 |
|
T4 |
19 |
|
T23 |
1 |
|
T6 |
23 |
| others[2] |
803 |
1 |
|
T4 |
16 |
|
T6 |
20 |
|
T34 |
2 |
| others[3] |
1238 |
1 |
|
T4 |
33 |
|
T6 |
23 |
|
T66 |
6 |
| false |
396 |
1 |
|
T4 |
7 |
|
T6 |
9 |
|
T66 |
2 |
| true |
516 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2573 |
1 |
|
T4 |
15 |
|
T6 |
20 |
|
T25 |
20 |
| others[1] |
2376 |
1 |
|
T4 |
10 |
|
T6 |
18 |
|
T25 |
13 |
| others[2] |
2466 |
1 |
|
T3 |
2 |
|
T4 |
12 |
|
T17 |
2 |
| others[3] |
4147 |
1 |
|
T4 |
13 |
|
T6 |
30 |
|
T25 |
32 |
| false |
1295 |
1 |
|
T4 |
5 |
|
T6 |
10 |
|
T25 |
12 |
| true |
1485 |
1 |
|
T2 |
1 |
|
T4 |
46 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10027 |
1 |
|
T4 |
14 |
|
T23 |
1 |
|
T17 |
2 |
| others[1] |
283 |
1 |
|
T4 |
6 |
|
T124 |
1 |
|
T370 |
1 |
| others[2] |
265 |
1 |
|
T4 |
16 |
|
T9 |
1 |
|
T61 |
12 |
| others[3] |
424 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T8 |
1 |
| false |
145 |
1 |
|
T124 |
1 |
|
T61 |
6 |
|
T157 |
1 |
| true |
3198 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10255 |
1 |
|
T4 |
15 |
|
T17 |
2 |
|
T6 |
8 |
| others[1] |
466 |
1 |
|
T4 |
11 |
|
T6 |
18 |
|
T7 |
1 |
| others[2] |
435 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T6 |
11 |
| others[3] |
793 |
1 |
|
T4 |
10 |
|
T9 |
1 |
|
T6 |
15 |
| false |
249 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| true |
2144 |
1 |
|
T4 |
46 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10024 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T17 |
2 |
| others[1] |
246 |
1 |
|
T3 |
2 |
|
T4 |
9 |
|
T34 |
1 |
| others[2] |
256 |
1 |
|
T4 |
11 |
|
T124 |
2 |
|
T61 |
14 |
| others[3] |
424 |
1 |
|
T4 |
18 |
|
T34 |
3 |
|
T61 |
19 |
| false |
127 |
1 |
|
T4 |
4 |
|
T61 |
3 |
|
T47 |
1 |
| true |
3265 |
1 |
|
T2 |
1 |
|
T4 |
49 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10028 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
256 |
1 |
|
T4 |
14 |
|
T23 |
1 |
|
T34 |
2 |
| others[2] |
248 |
1 |
|
T4 |
15 |
|
T34 |
1 |
|
T61 |
10 |
| others[3] |
427 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T34 |
1 |
| false |
136 |
1 |
|
T4 |
3 |
|
T61 |
6 |
|
T127 |
1 |
| true |
3247 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10540 |
1 |
|
T4 |
18 |
|
T17 |
2 |
|
T6 |
14 |
| others[1] |
803 |
1 |
|
T4 |
18 |
|
T23 |
1 |
|
T6 |
19 |
| others[2] |
808 |
1 |
|
T4 |
26 |
|
T6 |
23 |
|
T66 |
2 |
| others[3] |
1314 |
1 |
|
T3 |
1 |
|
T4 |
33 |
|
T6 |
32 |
| false |
391 |
1 |
|
T4 |
6 |
|
T6 |
5 |
|
T66 |
1 |
| true |
486 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10623 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T17 |
2 |
| others[1] |
768 |
1 |
|
T4 |
30 |
|
T6 |
16 |
|
T66 |
5 |
| others[2] |
813 |
1 |
|
T4 |
20 |
|
T6 |
17 |
|
T124 |
1 |
| others[3] |
1244 |
1 |
|
T4 |
23 |
|
T6 |
29 |
|
T34 |
1 |
| false |
367 |
1 |
|
T4 |
10 |
|
T23 |
1 |
|
T6 |
7 |
| true |
527 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2546 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T17 |
1 |
| others[1] |
2460 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T6 |
22 |
| others[2] |
2440 |
1 |
|
T4 |
9 |
|
T6 |
19 |
|
T25 |
16 |
| others[3] |
4189 |
1 |
|
T4 |
16 |
|
T17 |
1 |
|
T6 |
26 |
| false |
1265 |
1 |
|
T4 |
3 |
|
T6 |
5 |
|
T25 |
11 |
| true |
1442 |
1 |
|
T2 |
1 |
|
T4 |
58 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10042 |
1 |
|
T4 |
10 |
|
T8 |
1 |
|
T17 |
2 |
| others[1] |
258 |
1 |
|
T4 |
8 |
|
T23 |
1 |
|
T34 |
1 |
| others[2] |
263 |
1 |
|
T4 |
13 |
|
T34 |
2 |
|
T61 |
10 |
| others[3] |
440 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
14 |
| false |
140 |
1 |
|
T4 |
4 |
|
T24 |
1 |
|
T61 |
5 |
| true |
3199 |
1 |
|
T3 |
1 |
|
T4 |
52 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10203 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T6 |
9 |
| others[1] |
488 |
1 |
|
T3 |
2 |
|
T4 |
10 |
|
T6 |
4 |
| others[2] |
421 |
1 |
|
T4 |
8 |
|
T6 |
11 |
|
T34 |
3 |
| others[3] |
767 |
1 |
|
T4 |
14 |
|
T9 |
1 |
|
T6 |
17 |
| false |
228 |
1 |
|
T4 |
4 |
|
T6 |
6 |
|
T34 |
1 |
| true |
2235 |
1 |
|
T2 |
1 |
|
T4 |
57 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T4 |
5 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
270 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T34 |
2 |
| others[2] |
248 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T7 |
1 |
| others[3] |
405 |
1 |
|
T4 |
23 |
|
T8 |
1 |
|
T23 |
1 |
| false |
148 |
1 |
|
T4 |
10 |
|
T34 |
1 |
|
T61 |
7 |
| true |
3309 |
1 |
|
T3 |
1 |
|
T4 |
51 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T25 |
96 |
| others[1] |
239 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T34 |
1 |
| others[2] |
260 |
1 |
|
T4 |
12 |
|
T34 |
1 |
|
T61 |
11 |
| others[3] |
358 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T23 |
1 |
| false |
147 |
1 |
|
T4 |
2 |
|
T7 |
1 |
|
T172 |
1 |
| true |
3313 |
1 |
|
T3 |
1 |
|
T4 |
53 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10530 |
1 |
|
T4 |
16 |
|
T17 |
2 |
|
T6 |
11 |
| others[1] |
797 |
1 |
|
T4 |
15 |
|
T6 |
14 |
|
T34 |
1 |
| others[2] |
752 |
1 |
|
T4 |
25 |
|
T6 |
20 |
|
T34 |
1 |
| others[3] |
1342 |
1 |
|
T3 |
1 |
|
T4 |
32 |
|
T23 |
1 |
| false |
429 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
11 |
| true |
492 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |