Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226620	1		T2	968		T3	5		T4	100
auto[FlashEraseBank]	200829	1		T2	1494		T3	3		T4	1166

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	241293	1		T2	1250		T3	4		T4	671
auto[FlashOpProgram]	165945	1		T2	1212		T3	4		T4	548
auto[FlashOpErase]	16211	1		T4	47		T5	9		T23	35
auto[FlashOpInvalid]	4000	1		T130	200		T211	200		T140	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	241293	1		T2	1250		T3	4		T4	671
op[FlashOpProgram]	165945	1		T2	1212		T3	4		T4	548
op[FlashOpErase]	16211	1		T4	47		T5	9		T23	35
read_erase_read	649	1		T4	4		T5	2		T23	7
read_prog_read	1406	1		T2	10		T3	1		T4	7

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	288946	1		T2	1816		T3	8		T4	100
auto[FlashPartInfo]	134965	1		T2	636		T4	1166		T5	247
auto[FlashPartInfo1]	721	1		T2	1		T7	3		T34	8
auto[FlashPartInfo2]	2817	1		T2	9		T8	47		T23	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	177417	1		T2	938		T3	4		T4	31
auto[FlashPartData]	auto[FlashOpProgram]	103786	1		T2	878		T3	4		T4	36
auto[FlashPartData]	auto[FlashOpErase]	3805	1		T4	33		T23	35		T66	30
auto[FlashPartData]	auto[FlashOpInvalid]	3938	1		T130	196		T211	198		T140	198
auto[FlashPartInfo]	auto[FlashOpRead]	61537	1		T2	307		T4	640		T5	14
auto[FlashPartInfo]	auto[FlashOpProgram]	61083	1		T2	329		T4	512		T5	224
auto[FlashPartInfo]	auto[FlashOpErase]	12297	1		T4	14		T5	9		T25	148
auto[FlashPartInfo]	auto[FlashOpInvalid]	48	1		T130	4		T211	2		T384	2
auto[FlashPartInfo1]	auto[FlashOpRead]	647	1		T2	1		T7	3		T34	8
auto[FlashPartInfo1]	auto[FlashOpProgram]	67	1		T136	1		T137	32		T138	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T136	1		T138	1		T385	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T136	2		T138	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1692	1		T2	4		T8	47		T9	29
auto[FlashPartInfo2]	auto[FlashOpProgram]	1009	1		T2	5		T23	1		T7	11
auto[FlashPartInfo2]	auto[FlashOpErase]	106	1		T38	1		T125	24		T127	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T140	2		T386	2		T387	2