Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31440	1		T4	8		T23	16		T25	284
auto[1]	75	1		T388	1		T389	1		T169	4
auto[2]	80	1		T66	8		T63	4		T390	1
auto[3]	274	1		T24	1		T48	1		T201	22

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7979	1		T4	2		T23	4		T25	71
evic_idx[1]	7976	1		T4	2		T23	4		T25	71
evic_idx[2]	7957	1		T4	2		T23	4		T25	71
evic_idx[3]	7957	1		T4	2		T23	4		T24	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30827	1		T25	284		T42	660		T130	400
evic_op[2]	446	1		T24	1		T48	1		T207	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7627	1		T25	71		T42	165		T130	100
evic_idx[0]	evic_op[1]	auto[1]	34	1		T391	33		T392	1		-	-
evic_idx[0]	evic_op[1]	auto[2]	5	1		T392	5		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	67	1		T201	7		T128	19		T393	8
evic_idx[0]	evic_op[2]	auto[0]	75	1		T352	1		T373	1		T394	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T169	1		T291	1		T395	1
evic_idx[0]	evic_op[2]	auto[2]	5	1		T390	1		T204	1		T205	1
evic_idx[0]	evic_op[2]	auto[3]	13	1		T64	1		T396	1		T397	1
evic_idx[1]	evic_op[1]	auto[0]	7630	1		T25	71		T42	165		T130	100
evic_idx[1]	evic_op[1]	auto[1]	11	1		T391	10		T392	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	4	1		T392	4		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	68	1		T201	6		T128	17		T393	7
evic_idx[1]	evic_op[2]	auto[0]	91	1		T207	1		T352	1		T373	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T169	1		T398	1		T395	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T204	3		T399	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	15	1		T65	1		T390	1		T400	1
evic_idx[2]	evic_op[1]	auto[0]	7638	1		T25	71		T42	165		T130	100
evic_idx[2]	evic_op[1]	auto[1]	7	1		T391	6		T392	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	3	1		T392	3		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	47	1		T201	4		T128	8		T393	5
evic_idx[2]	evic_op[2]	auto[0]	92	1		T207	3		T352	1		T373	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T169	1		T395	1		T401	2
evic_idx[2]	evic_op[2]	auto[2]	7	1		T63	1		T204	5		T399	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T48	1		T292	1		T293	1
evic_idx[3]	evic_op[1]	auto[0]	7630	1		T25	71		T42	165		T130	100
evic_idx[3]	evic_op[1]	auto[1]	6	1		T391	5		T392	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	8	1		T392	8		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	42	1		T201	5		T128	9		T393	5
evic_idx[3]	evic_op[2]	auto[0]	93	1		T352	1		T373	1		T394	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T388	1		T389	1		T169	1
evic_idx[3]	evic_op[2]	auto[2]	12	1		T63	3		T204	3		T291	1
evic_idx[3]	evic_op[2]	auto[3]	12	1		T24	1		T402	1		T403	1