Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	45449	1		T57	6155		T58	1714		T59	6407
prog_lvl[2]	948	1		T58	856		T404	27		T405	1
prog_lvl[3]	2	1		T58	1		T406	1		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	9331	1		T8	28		T9	18		T26	11
rd_lvl[2]	22711	1		T8	12		T9	42		T26	12
rd_lvl[3]	13173	1		T8	16		T9	32		T26	11
rd_lvl[4]	18867	1		T8	9		T9	11		T26	4
rd_lvl[5]	12574	1		T8	6		T9	947		T26	3
rd_lvl[6]	15439	1		T8	5		T9	779		T146	1261
rd_lvl[7]	11604	1		T8	646		T26	830		T146	652
rd_lvl[8]	7622	1		T8	985		T26	1252		T407	1
rd_lvl[9]	3642	1		T8	80		T9	23		T407	104
rd_lvl[10]	4138	1		T146	2		T284	685		T213	855
rd_lvl[11]	4346	1		T8	2		T26	4		T284	1
rd_lvl[12]	8410	1		T8	19		T26	27		T27	538
rd_lvl[13]	7705	1		T27	440		T150	360		T284	80
rd_lvl[14]	2446	1		T408	526		T409	2		T410	368
rd_lvl[15]	3350	1		T411	385		T408	585		T412	638