Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	328926	1		T1	1		T2	2		T3	2
all_pins[1]	328926	1		T1	1		T2	2		T3	2
all_pins[2]	328926	1		T1	1		T2	2		T3	2
all_pins[3]	328926	1		T1	1		T2	2		T3	2
all_pins[4]	328926	1		T1	1		T2	2		T3	2
all_pins[5]	328926	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1599157	1		T1	6		T2	12		T3	12
values[0x1]	374399	1		T8	3111		T9	2808		T26	4097
transitions[0x0=>0x1]	351817	1		T8	2515		T9	2758		T26	3077
transitions[0x1=>0x0]	351827	1		T8	2515		T9	2758		T26	3077

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	263546	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	65380	1		T57	2392		T176	4400		T177	4676
all_pins[0]	transitions[0x0=>0x1]	65361	1		T57	2392		T176	4400		T177	4676
all_pins[0]	transitions[0x1=>0x0]	54306	1		T57	6155		T58	3428		T59	6407
all_pins[1]	values[0x0]	274601	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	54325	1		T57	6155		T58	3428		T59	6407
all_pins[1]	transitions[0x0=>0x1]	54314	1		T57	6155		T58	3428		T59	6407
all_pins[1]	transitions[0x1=>0x0]	7009	1		T8	19		T26	28		T27	6
all_pins[2]	values[0x0]	321906	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	7020	1		T8	19		T26	28		T27	6
all_pins[2]	transitions[0x0=>0x1]	4735	1		T8	19		T26	28		T27	6
all_pins[2]	transitions[0x1=>0x0]	147355	1		T8	2192		T9	1852		T26	2979
all_pins[3]	values[0x0]	179286	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	149640	1		T8	2192		T9	1852		T26	2979
all_pins[3]	transitions[0x0=>0x1]	129414	1		T8	1596		T9	1802		T26	1959
all_pins[3]	transitions[0x1=>0x0]	77748	1		T8	304		T9	906		T26	70
all_pins[4]	values[0x0]	230952	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	97974	1		T8	900		T9	956		T26	1090
all_pins[4]	transitions[0x0=>0x1]	97958	1		T8	900		T9	956		T26	1090
all_pins[4]	transitions[0x1=>0x0]	44	1		T271	1		T240	1		T241	1
all_pins[5]	values[0x0]	328866	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	60	1		T271	1		T240	3		T241	1
all_pins[5]	transitions[0x0=>0x1]	35	1		T240	3		T242	1		T243	1
all_pins[5]	transitions[0x1=>0x0]	65365	1		T57	2392		T176	4400		T177	4676