Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T271	7		T272	7		T248	4
all_values[1]	266	1		T271	7		T272	7		T248	4
all_values[2]	266	1		T271	7		T272	7		T248	4
all_values[3]	266	1		T271	7		T272	7		T248	4
all_values[4]	266	1		T271	7		T272	7		T248	4
all_values[5]	266	1		T271	7		T272	7		T248	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	837	1		T271	21		T272	22		T248	15
auto[1]	759	1		T271	21		T272	20		T248	9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	627	1		T271	12		T272	16		T248	14
auto[1]	969	1		T271	30		T272	26		T248	10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	937	1		T271	20		T272	23		T248	16
auto[1]	659	1		T271	22		T272	19		T248	8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1		T248	2		T242	4		T243	1
all_values[0]	auto[0]	auto[0]	auto[1]	23	1		T240	1		T340	1		T341	1
all_values[0]	auto[0]	auto[1]	auto[0]	43	1		T271	2		T272	1		T240	3
all_values[0]	auto[0]	auto[1]	auto[1]	34	1		T271	1		T272	2		T342	1
all_values[0]	auto[1]	auto[0]	auto[1]	70	1		T271	1		T272	2		T248	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T271	3		T272	2		T248	1
all_values[1]	auto[0]	auto[0]	auto[0]	59	1		T271	1		T272	3		T240	1
all_values[1]	auto[0]	auto[0]	auto[1]	27	1		T271	2		T241	1		T243	1
all_values[1]	auto[0]	auto[1]	auto[0]	50	1		T271	1		T272	3		T240	1
all_values[1]	auto[0]	auto[1]	auto[1]	25	1		T248	1		T240	1		T241	2
all_values[1]	auto[1]	auto[0]	auto[1]	56	1		T271	3		T248	2		T242	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T272	1		T248	1		T240	4
all_values[2]	auto[0]	auto[0]	auto[0]	65	1		T271	2		T272	3		T248	4
all_values[2]	auto[0]	auto[0]	auto[1]	21	1		T271	1		T272	1		T343	1
all_values[2]	auto[0]	auto[1]	auto[0]	48	1		T271	1		T272	1		T240	2
all_values[2]	auto[0]	auto[1]	auto[1]	28	1		T240	2		T241	1		T242	1
all_values[2]	auto[1]	auto[0]	auto[1]	50	1		T271	2		T272	1		T240	1
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T271	1		T272	1		T240	2
all_values[3]	auto[0]	auto[0]	auto[0]	55	1		T242	2		T243	2		T340	2
all_values[3]	auto[0]	auto[0]	auto[1]	21	1		T272	2		T243	1		T342	2
all_values[3]	auto[0]	auto[1]	auto[0]	63	1		T248	3		T240	2		T241	1
all_values[3]	auto[0]	auto[1]	auto[1]	21	1		T271	3		T272	1		T240	2
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T271	1		T272	4		T248	1
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T271	3		T240	2		T241	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1		T271	1		T272	1		T248	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T271	1		T272	1		T242	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1		T271	1		T272	1		T240	2
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T248	1		T240	1		T241	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T271	4		T248	1		T240	1
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T272	4		T248	1		T240	2
all_values[5]	auto[0]	auto[0]	auto[0]	59	1		T272	1		T248	3		T240	2
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T243	1		T340	2		T344	1
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T271	3		T272	2		T248	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T240	2		T342	1		T340	1
all_values[5]	auto[1]	auto[0]	auto[1]	60	1		T271	2		T272	3		T240	1
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T271	2		T272	1		T240	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal