Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1338449544	1335123528	0	0
CheckNGreaterZero_A	3904	3904	0	0
GntImpliesReady_A	1338449544	385192072	0	0
GntImpliesValid_A	1338449544	385192072	0	0
GrantKnown_A	1338449544	1335123528	0	0
IdxKnown_A	1338449544	1335123528	0	0
IndexIsCorrect_A	1338449544	385192072	0	0
NoReadyValidNoGrant_A	1338449544	158005870	0	0
Priority_A	1338449544	409255352	0	0
ReadyAndValidImplyGrant_A	1338449544	385192072	0	0
ReqAndReadyImplyGrant_A	1338449544	385192072	0	0
ReqImpliesValid_A	1338449544	409255352	0	0
ValidKnown_A	1338449544	1335123528	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	1335123528	0	0
T1	16184	13512	0	0
T2	1152804	1152528	0	0
T3	10580	10300	0	0
T4	3186600	3186272	0	0
T5	218248	217896	0	0
T8	405312	404816	0	0
T13	15656	13088	0	0
T22	6464	6240	0	0
T23	1705228	1704892	0	0
T24	6912	6156	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3904	3904	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T8	4	4	0	0
T13	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0
T24	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	385192072	0	0
T1	8092	368	0	0
T2	1152804	321404	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	188318	0	0
T8	405312	61730	0	0
T9	0	31800	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	385192072	0	0
T1	8092	368	0	0
T2	1152804	321404	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	188318	0	0
T8	405312	61730	0	0
T9	0	31800	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	1335123528	0	0
T1	16184	13512	0	0
T2	1152804	1152528	0	0
T3	10580	10300	0	0
T4	3186600	3186272	0	0
T5	218248	217896	0	0
T8	405312	404816	0	0
T13	15656	13088	0	0
T22	6464	6240	0	0
T23	1705228	1704892	0	0
T24	6912	6156	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	1335123528	0	0
T1	16184	13512	0	0
T2	1152804	1152528	0	0
T3	10580	10300	0	0
T4	3186600	3186272	0	0
T5	218248	217896	0	0
T8	405312	404816	0	0
T13	15656	13088	0	0
T22	6464	6240	0	0
T23	1705228	1704892	0	0
T24	6912	6156	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	385192072	0	0
T1	8092	368	0	0
T2	1152804	321404	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	188318	0	0
T8	405312	61730	0	0
T9	0	31800	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	158005870	0	0
T1	8092	1372	0	0
T2	1152804	302802	0	0
T3	10580	388	0	0
T4	3186600	8488	0	0
T5	218248	1664	0	0
T7	0	144664	0	0
T8	405312	165076	0	0
T9	0	84584	0	0
T13	15656	1368	0	0
T14	7156	0	0	0
T17	0	1048576	0	0
T22	6464	256	0	0
T23	1705228	2444	0	0
T24	6912	866	0	0
T34	0	756	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	409255352	0	0
T1	8092	368	0	0
T2	1152804	384332	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	207098	0	0
T8	405312	64674	0	0
T9	0	33062	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	385192072	0	0
T1	8092	368	0	0
T2	1152804	321404	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	188318	0	0
T8	405312	61730	0	0
T9	0	31800	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	385192072	0	0
T1	8092	368	0	0
T2	1152804	321404	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	188318	0	0
T8	405312	61730	0	0
T9	0	31800	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	409255352	0	0
T1	8092	368	0	0
T2	1152804	384332	0	0
T3	10580	3006	0	0
T4	3186600	1426904	0	0
T5	218248	30224	0	0
T6	0	22442	0	0
T7	0	207098	0	0
T8	405312	64674	0	0
T9	0	33062	0	0
T13	15656	344	0	0
T14	7156	0	0	0
T17	0	255794	0	0
T22	6464	64	0	0
T23	1705228	832946	0	0
T24	6912	384	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338449544	1335123528	0	0
T1	16184	13512	0	0
T2	1152804	1152528	0	0
T3	10580	10300	0	0
T4	3186600	3186272	0	0
T5	218248	217896	0	0
T8	405312	404816	0	0
T13	15656	13088	0	0
T22	6464	6240	0	0
T23	1705228	1704892	0	0
T24	6912	6156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	334612386	333780882	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	334612386	102165324	0	0
GntImpliesValid_A	334612386	102165324	0	0
GrantKnown_A	334612386	333780882	0	0
IdxKnown_A	334612386	333780882	0	0
IndexIsCorrect_A	334612386	102165324	0	0
NoReadyValidNoGrant_A	334612386	40588863	0	0
Priority_A	334612386	108278783	0	0
ReadyAndValidImplyGrant_A	334612386	102165324	0	0
ReqAndReadyImplyGrant_A	334612386	102165324	0	0
ReqImpliesValid_A	334612386	108278783	0	0
ValidKnown_A	334612386	333780882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102165324	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102165324	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102165324	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	40588863	0	0
T1	4046	686	0	0
T2	288201	81393	0	0
T3	2645	148	0	0
T4	796650	1839	0	0
T5	54562	832	0	0
T8	101328	43591	0	0
T13	3914	684	0	0
T22	1616	128	0	0
T23	426307	463	0	0
T24	1728	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	108278783	0	0
T1	4046	184	0	0
T2	288201	111959	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	17317	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102165324	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102165324	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	108278783	0	0
T1	4046	184	0	0
T2	288201	111959	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	17317	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	334612386	333780882	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	334612386	102148270	0	0
GntImpliesValid_A	334612386	102148270	0	0
GrantKnown_A	334612386	333780882	0	0
IdxKnown_A	334612386	333780882	0	0
IndexIsCorrect_A	334612386	102148270	0	0
NoReadyValidNoGrant_A	334612386	40588865	0	0
Priority_A	334612386	108261727	0	0
ReadyAndValidImplyGrant_A	334612386	102148270	0	0
ReqAndReadyImplyGrant_A	334612386	102148270	0	0
ReqImpliesValid_A	334612386	108261727	0	0
ValidKnown_A	334612386	333780882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102148270	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102148270	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102148270	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	40588865	0	0
T1	4046	686	0	0
T2	288201	81393	0	0
T3	2645	148	0	0
T4	796650	1839	0	0
T5	54562	832	0	0
T8	101328	43591	0	0
T13	3914	684	0	0
T22	1616	128	0	0
T23	426307	463	0	0
T24	1728	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	108261727	0	0
T1	4046	184	0	0
T2	288201	111959	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	17317	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102148270	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	102148270	0	0
T1	4046	184	0	0
T2	288201	90745	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	16468	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	108261727	0	0
T1	4046	184	0	0
T2	288201	111959	0	0
T3	2645	1252	0	0
T4	796650	75200	0	0
T5	54562	15112	0	0
T8	101328	17317	0	0
T13	3914	172	0	0
T22	1616	32	0	0
T23	426307	339138	0	0
T24	1728	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T8,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	334612386	333780882	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	334612386	90439239	0	0
GntImpliesValid_A	334612386	90439239	0	0
GrantKnown_A	334612386	333780882	0	0
IdxKnown_A	334612386	333780882	0	0
IndexIsCorrect_A	334612386	90439239	0	0
NoReadyValidNoGrant_A	334612386	38414071	0	0
Priority_A	334612386	96357421	0	0
ReadyAndValidImplyGrant_A	334612386	90439239	0	0
ReqAndReadyImplyGrant_A	334612386	90439239	0	0
ReqImpliesValid_A	334612386	96357421	0	0
ValidKnown_A	334612386	333780882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	38414071	0	0
T2	288201	70008	0	0
T3	2645	46	0	0
T4	796650	2405	0	0
T5	54562	0	0	0
T7	0	72332	0	0
T8	101328	38947	0	0
T9	0	42292	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	524288	0	0
T22	1616	0	0	0
T23	426307	759	0	0
T24	1728	177	0	0
T34	0	378	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	96357421	0	0
T2	288201	80207	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	103549	0	0
T8	101328	15020	0	0
T9	0	16531	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	96357421	0	0
T2	288201	80207	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	103549	0	0
T8	101328	15020	0	0
T9	0	16531	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T8,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	334612386	333780882	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	334612386	90439239	0	0
GntImpliesValid_A	334612386	90439239	0	0
GrantKnown_A	334612386	333780882	0	0
IdxKnown_A	334612386	333780882	0	0
IndexIsCorrect_A	334612386	90439239	0	0
NoReadyValidNoGrant_A	334612386	38414071	0	0
Priority_A	334612386	96357421	0	0
ReadyAndValidImplyGrant_A	334612386	90439239	0	0
ReqAndReadyImplyGrant_A	334612386	90439239	0	0
ReqImpliesValid_A	334612386	96357421	0	0
ValidKnown_A	334612386	333780882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	38414071	0	0
T2	288201	70008	0	0
T3	2645	46	0	0
T4	796650	2405	0	0
T5	54562	0	0	0
T7	0	72332	0	0
T8	101328	38947	0	0
T9	0	42292	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	524288	0	0
T22	1616	0	0	0
T23	426307	759	0	0
T24	1728	177	0	0
T34	0	378	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	96357421	0	0
T2	288201	80207	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	103549	0	0
T8	101328	15020	0	0
T9	0	16531	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	90439239	0	0
T2	288201	69957	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	94159	0	0
T8	101328	14397	0	0
T9	0	15900	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	96357421	0	0
T2	288201	80207	0	0
T3	2645	251	0	0
T4	796650	638252	0	0
T5	54562	0	0	0
T6	0	11221	0	0
T7	0	103549	0	0
T8	101328	15020	0	0
T9	0	16531	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	127897	0	0
T22	1616	0	0	0
T23	426307	77335	0	0
T24	1728	128	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0