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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.87 94.08 98.95 89.80 98.46 98.20 98.42


Total test records in report: 1191
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T342 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2507393949 Jan 21 07:52:53 PM PST 24 Jan 21 07:53:08 PM PST 24 17516500 ps
T335 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3308011567 Jan 21 07:51:31 PM PST 24 Jan 21 07:51:50 PM PST 24 27245100 ps
T244 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1093324751 Jan 21 07:51:27 PM PST 24 Jan 21 08:06:29 PM PST 24 727842800 ps
T231 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3170937143 Jan 21 07:51:14 PM PST 24 Jan 21 07:59:03 PM PST 24 907973200 ps
T1064 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1541838103 Jan 21 07:52:06 PM PST 24 Jan 21 07:52:20 PM PST 24 20324800 ps
T340 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3311029575 Jan 21 07:52:21 PM PST 24 Jan 21 07:52:36 PM PST 24 53690000 ps
T341 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3630513579 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:49 PM PST 24 18478400 ps
T1065 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2256000431 Jan 21 07:51:03 PM PST 24 Jan 21 07:51:18 PM PST 24 14483200 ps
T1066 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1647001024 Jan 21 07:52:34 PM PST 24 Jan 21 07:52:49 PM PST 24 16802400 ps
T343 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3510727109 Jan 21 07:52:42 PM PST 24 Jan 21 07:52:56 PM PST 24 17327400 ps
T1067 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3381979488 Jan 21 07:50:59 PM PST 24 Jan 21 07:51:18 PM PST 24 32176200 ps
T232 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3314101227 Jan 21 07:52:12 PM PST 24 Jan 21 08:07:18 PM PST 24 665259100 ps
T266 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2482086331 Jan 21 07:50:55 PM PST 24 Jan 21 07:51:56 PM PST 24 2838653200 ps
T310 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.422464183 Jan 21 07:52:31 PM PST 24 Jan 21 07:52:49 PM PST 24 37071500 ps
T311 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2883065482 Jan 21 07:51:29 PM PST 24 Jan 21 07:51:44 PM PST 24 24047400 ps
T312 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3417618327 Jan 21 07:50:58 PM PST 24 Jan 21 07:51:37 PM PST 24 864557700 ps
T313 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2548409340 Jan 21 07:52:37 PM PST 24 Jan 21 07:52:54 PM PST 24 17844900 ps
T314 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1622260852 Jan 21 07:52:22 PM PST 24 Jan 21 07:52:40 PM PST 24 38271600 ps
T245 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2123727966 Jan 21 07:51:24 PM PST 24 Jan 21 07:57:54 PM PST 24 207125300 ps
T315 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3554646450 Jan 21 07:50:44 PM PST 24 Jan 21 07:51:16 PM PST 24 116888700 ps
T1068 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4005174424 Jan 21 07:52:29 PM PST 24 Jan 21 07:52:45 PM PST 24 43491000 ps
T1069 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3750132109 Jan 21 07:52:50 PM PST 24 Jan 21 07:53:05 PM PST 24 27554100 ps
T344 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1970157574 Jan 21 07:52:37 PM PST 24 Jan 21 07:52:52 PM PST 24 30810300 ps
T246 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2733814149 Jan 21 07:52:01 PM PST 24 Jan 21 07:59:41 PM PST 24 215691300 ps
T1070 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.861129837 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:49 PM PST 24 46988800 ps
T1071 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1630874517 Jan 21 07:51:54 PM PST 24 Jan 21 07:52:13 PM PST 24 65605000 ps
T1072 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2416221525 Jan 21 07:52:37 PM PST 24 Jan 21 07:52:51 PM PST 24 29126600 ps
T300 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.454973870 Jan 21 07:51:15 PM PST 24 Jan 21 07:52:02 PM PST 24 1421565000 ps
T247 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1623293048 Jan 21 07:51:19 PM PST 24 Jan 21 07:59:05 PM PST 24 685271600 ps
T250 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2526585479 Jan 21 07:50:51 PM PST 24 Jan 21 07:51:06 PM PST 24 159826400 ps
T251 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2655303475 Jan 21 07:52:29 PM PST 24 Jan 21 07:52:44 PM PST 24 49790400 ps
T233 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2313969641 Jan 21 07:51:12 PM PST 24 Jan 21 07:51:31 PM PST 24 41704200 ps
T252 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3621060173 Jan 21 07:52:30 PM PST 24 Jan 21 07:52:44 PM PST 24 28360800 ps
T253 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2222988926 Jan 21 07:52:22 PM PST 24 Jan 21 07:52:42 PM PST 24 152626800 ps
T234 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2086237507 Jan 21 07:51:53 PM PST 24 Jan 21 07:52:10 PM PST 24 113705300 ps
T254 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4187315096 Jan 21 07:50:53 PM PST 24 Jan 21 07:51:08 PM PST 24 17403800 ps
T255 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1888323985 Jan 21 07:50:50 PM PST 24 Jan 21 07:51:27 PM PST 24 386715900 ps
T235 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2793257043 Jan 21 07:51:52 PM PST 24 Jan 21 07:52:11 PM PST 24 200792000 ps
T256 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.229226714 Jan 21 07:51:28 PM PST 24 Jan 21 07:51:43 PM PST 24 23841900 ps
T301 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2749342873 Jan 21 07:52:12 PM PST 24 Jan 21 07:52:32 PM PST 24 1014001800 ps
T1073 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2132025434 Jan 21 07:52:50 PM PST 24 Jan 21 07:53:07 PM PST 24 42515300 ps
T236 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2775418958 Jan 21 07:52:21 PM PST 24 Jan 21 07:52:39 PM PST 24 33692100 ps
T1074 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1649561428 Jan 21 07:52:22 PM PST 24 Jan 21 07:52:41 PM PST 24 20848300 ps
T1075 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.479637741 Jan 21 07:52:04 PM PST 24 Jan 21 07:52:19 PM PST 24 24093000 ps
T1076 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.341372359 Jan 21 08:40:41 PM PST 24 Jan 21 08:40:57 PM PST 24 47738700 ps
T302 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.290376681 Jan 21 07:51:06 PM PST 24 Jan 21 07:51:26 PM PST 24 414534500 ps
T1077 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1168829919 Jan 21 07:51:15 PM PST 24 Jan 21 07:51:32 PM PST 24 28485500 ps
T1078 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2276858262 Jan 21 07:51:47 PM PST 24 Jan 21 07:52:04 PM PST 24 39808800 ps
T303 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3470888022 Jan 21 07:51:53 PM PST 24 Jan 21 07:52:08 PM PST 24 158516400 ps
T237 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.423768284 Jan 21 07:51:57 PM PST 24 Jan 21 07:52:14 PM PST 24 149475800 ps
T304 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1910980034 Jan 21 07:50:47 PM PST 24 Jan 21 07:51:57 PM PST 24 14076438400 ps
T1079 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1214540853 Jan 21 07:51:14 PM PST 24 Jan 21 07:51:50 PM PST 24 826178600 ps
T1080 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.968805894 Jan 21 07:51:28 PM PST 24 Jan 21 07:51:45 PM PST 24 21608100 ps
T1081 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.866549428 Jan 21 07:51:25 PM PST 24 Jan 21 07:51:43 PM PST 24 49695000 ps
T257 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3154997224 Jan 21 07:50:57 PM PST 24 Jan 21 07:51:11 PM PST 24 27932300 ps
T238 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2540976801 Jan 21 07:52:34 PM PST 24 Jan 21 07:52:55 PM PST 24 32085900 ps
T1082 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2418196138 Jan 21 07:52:01 PM PST 24 Jan 21 07:52:20 PM PST 24 66705400 ps
T1083 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3929044361 Jan 21 07:51:20 PM PST 24 Jan 21 07:51:35 PM PST 24 28756100 ps
T1084 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2579073227 Jan 21 07:50:46 PM PST 24 Jan 21 07:51:01 PM PST 24 23102400 ps
T239 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3461068404 Jan 21 07:52:22 PM PST 24 Jan 21 07:52:43 PM PST 24 164761400 ps
T277 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3559885948 Jan 21 08:50:43 PM PST 24 Jan 21 09:03:46 PM PST 24 1444344000 ps
T1085 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1419600001 Jan 21 07:52:50 PM PST 24 Jan 21 07:53:06 PM PST 24 18697600 ps
T1086 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.433390855 Jan 21 07:51:19 PM PST 24 Jan 21 07:51:34 PM PST 24 52115000 ps
T1087 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1208576064 Jan 21 07:52:24 PM PST 24 Jan 21 07:52:42 PM PST 24 20301900 ps
T305 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3489853836 Jan 21 07:51:27 PM PST 24 Jan 21 07:51:44 PM PST 24 105777000 ps
T1088 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2255923598 Jan 21 08:10:26 PM PST 24 Jan 21 08:10:57 PM PST 24 384588000 ps
T1089 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4256800853 Jan 21 07:52:03 PM PST 24 Jan 21 07:52:18 PM PST 24 17593600 ps
T1090 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.723695626 Jan 21 07:50:53 PM PST 24 Jan 21 07:51:45 PM PST 24 7859401300 ps
T1091 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2318119166 Jan 21 07:50:54 PM PST 24 Jan 21 07:51:11 PM PST 24 45601300 ps
T1092 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1109356447 Jan 21 07:50:47 PM PST 24 Jan 21 07:51:29 PM PST 24 6405129900 ps
T269 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3890691721 Jan 21 07:51:13 PM PST 24 Jan 21 07:51:34 PM PST 24 346183800 ps
T308 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3514919255 Jan 21 07:51:58 PM PST 24 Jan 21 08:07:01 PM PST 24 868727600 ps
T1093 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.958081719 Jan 21 07:52:51 PM PST 24 Jan 21 07:53:06 PM PST 24 69395300 ps
T1094 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.233095309 Jan 21 07:50:47 PM PST 24 Jan 21 07:51:02 PM PST 24 88023400 ps
T270 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3797840662 Jan 21 08:32:47 PM PST 24 Jan 21 08:33:08 PM PST 24 54469100 ps
T1095 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3825780615 Jan 21 07:50:51 PM PST 24 Jan 21 07:51:06 PM PST 24 47397000 ps
T1096 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.164322691 Jan 21 07:50:47 PM PST 24 Jan 21 07:51:05 PM PST 24 28825600 ps
T1097 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.238467862 Jan 21 07:52:34 PM PST 24 Jan 21 07:52:49 PM PST 24 33233400 ps
T1098 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.26994743 Jan 21 07:51:25 PM PST 24 Jan 21 07:51:40 PM PST 24 30925500 ps
T346 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.835834926 Jan 21 07:52:04 PM PST 24 Jan 21 07:59:48 PM PST 24 364858300 ps
T1099 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3914312726 Jan 21 07:51:13 PM PST 24 Jan 21 07:52:33 PM PST 24 4773294800 ps
T1100 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3386246344 Jan 21 07:52:12 PM PST 24 Jan 21 07:52:30 PM PST 24 22296200 ps
T309 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3659629433 Jan 21 07:51:39 PM PST 24 Jan 21 07:51:58 PM PST 24 351248900 ps
T1101 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2254320267 Jan 21 07:51:26 PM PST 24 Jan 21 07:51:42 PM PST 24 63689900 ps
T1102 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.273298646 Jan 21 07:51:17 PM PST 24 Jan 21 07:51:32 PM PST 24 15183500 ps
T274 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1278153067 Jan 21 07:51:44 PM PST 24 Jan 21 07:52:05 PM PST 24 51309300 ps
T345 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3407106879 Jan 21 07:52:30 PM PST 24 Jan 21 08:00:18 PM PST 24 512439200 ps
T258 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2449319547 Jan 21 07:51:12 PM PST 24 Jan 21 07:51:27 PM PST 24 58025600 ps
T1103 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3267357692 Jan 21 07:51:30 PM PST 24 Jan 21 07:51:50 PM PST 24 828087400 ps
T1104 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.954301940 Jan 21 07:52:50 PM PST 24 Jan 21 07:53:05 PM PST 24 58363600 ps
T1105 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.277709501 Jan 21 07:52:36 PM PST 24 Jan 21 07:52:51 PM PST 24 37908100 ps
T1106 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1047534641 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:48 PM PST 24 23715800 ps
T1107 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3099105498 Jan 21 07:52:17 PM PST 24 Jan 21 07:52:34 PM PST 24 17816300 ps
T1108 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3936534872 Jan 21 07:51:54 PM PST 24 Jan 21 07:52:13 PM PST 24 69775600 ps
T1109 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3120050017 Jan 21 07:52:00 PM PST 24 Jan 21 07:52:14 PM PST 24 14011700 ps
T1110 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2658039316 Jan 21 07:52:21 PM PST 24 Jan 21 07:52:36 PM PST 24 54293700 ps
T275 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.67142153 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:51 PM PST 24 125856800 ps
T1111 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3416231361 Jan 21 07:51:55 PM PST 24 Jan 21 07:52:16 PM PST 24 48159900 ps
T1112 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3552383308 Jan 21 07:52:23 PM PST 24 Jan 21 08:00:05 PM PST 24 406351700 ps
T1113 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3459717903 Jan 21 07:50:45 PM PST 24 Jan 21 07:51:01 PM PST 24 46145300 ps
T316 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4195291651 Jan 21 07:51:16 PM PST 24 Jan 21 07:51:36 PM PST 24 366848400 ps
T276 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1214820347 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:53 PM PST 24 535875700 ps
T1114 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2502712085 Jan 21 07:51:06 PM PST 24 Jan 21 07:52:14 PM PST 24 2544554000 ps
T1115 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.623723442 Jan 21 07:52:12 PM PST 24 Jan 21 07:52:27 PM PST 24 52667500 ps
T1116 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3026371696 Jan 21 07:50:53 PM PST 24 Jan 21 07:51:14 PM PST 24 96845800 ps
T1117 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.174061495 Jan 21 07:52:03 PM PST 24 Jan 21 07:52:18 PM PST 24 15113300 ps
T1118 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2522152736 Jan 21 07:50:53 PM PST 24 Jan 21 07:51:30 PM PST 24 2112065900 ps
T1119 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.587980003 Jan 21 07:52:49 PM PST 24 Jan 21 07:53:04 PM PST 24 27460500 ps
T1120 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2228839134 Jan 21 07:51:27 PM PST 24 Jan 21 07:51:45 PM PST 24 58356700 ps
T1121 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2102994916 Jan 21 07:52:38 PM PST 24 Jan 21 07:52:55 PM PST 24 14897700 ps
T1122 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1577575020 Jan 21 07:50:49 PM PST 24 Jan 21 07:51:08 PM PST 24 139771000 ps
T317 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2377620561 Jan 21 07:51:24 PM PST 24 Jan 21 07:51:42 PM PST 24 85930600 ps
T1123 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.845662115 Jan 21 07:51:07 PM PST 24 Jan 21 07:51:25 PM PST 24 69775300 ps
T1124 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3168228044 Jan 21 07:51:27 PM PST 24 Jan 21 07:51:44 PM PST 24 24024200 ps
T1125 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.251911020 Jan 21 07:52:16 PM PST 24 Jan 21 07:52:34 PM PST 24 45364800 ps
T1126 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4143745638 Jan 21 07:51:28 PM PST 24 Jan 21 07:51:45 PM PST 24 34125200 ps
T350 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.69697868 Jan 21 07:51:59 PM PST 24 Jan 21 07:59:53 PM PST 24 353554500 ps
T273 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3001129609 Jan 21 07:50:53 PM PST 24 Jan 21 07:57:22 PM PST 24 404041500 ps
T1127 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4107410608 Jan 21 07:52:49 PM PST 24 Jan 21 07:53:04 PM PST 24 55021000 ps
T1128 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1864502407 Jan 21 07:52:29 PM PST 24 Jan 21 07:52:44 PM PST 24 27105700 ps
T1129 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1076747024 Jan 21 07:52:36 PM PST 24 Jan 21 07:52:52 PM PST 24 59843300 ps
T1130 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4169522502 Jan 21 07:51:29 PM PST 24 Jan 21 07:51:43 PM PST 24 26527200 ps
T1131 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.548665623 Jan 21 07:50:44 PM PST 24 Jan 21 07:51:01 PM PST 24 12773600 ps
T1132 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3854260963 Jan 21 07:51:20 PM PST 24 Jan 21 07:51:40 PM PST 24 112890600 ps
T1133 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4044373833 Jan 21 07:50:52 PM PST 24 Jan 21 07:51:07 PM PST 24 37480100 ps
T1134 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.353944250 Jan 21 07:51:53 PM PST 24 Jan 21 07:52:10 PM PST 24 138106700 ps
T1135 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2544609582 Jan 21 07:50:48 PM PST 24 Jan 21 07:51:07 PM PST 24 60046800 ps
T1136 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4130980994 Jan 21 07:51:12 PM PST 24 Jan 21 07:51:30 PM PST 24 69946400 ps
T1137 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1178744434 Jan 21 07:50:51 PM PST 24 Jan 21 07:51:11 PM PST 24 289337700 ps
T1138 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3512988434 Jan 21 07:51:44 PM PST 24 Jan 21 07:52:05 PM PST 24 102793000 ps
T1139 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2048288226 Jan 21 07:51:39 PM PST 24 Jan 21 07:51:56 PM PST 24 18692600 ps
T1140 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3362541093 Jan 21 07:51:07 PM PST 24 Jan 21 07:51:26 PM PST 24 531220100 ps
T259 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3684119186 Jan 21 07:50:47 PM PST 24 Jan 21 07:51:02 PM PST 24 29463900 ps
T1141 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.539804364 Jan 21 07:52:36 PM PST 24 Jan 21 07:52:50 PM PST 24 16266000 ps
T1142 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3872847677 Jan 21 07:52:12 PM PST 24 Jan 21 07:52:32 PM PST 24 207363600 ps
T318 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2421709135 Jan 21 09:18:33 PM PST 24 Jan 21 09:18:57 PM PST 24 740204800 ps
T1143 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3803725820 Jan 21 07:52:35 PM PST 24 Jan 21 07:52:52 PM PST 24 43418100 ps
T1144 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2783675750 Jan 21 07:52:04 PM PST 24 Jan 21 07:52:21 PM PST 24 27624500 ps
T1145 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1640292267 Jan 21 07:51:56 PM PST 24 Jan 21 07:52:15 PM PST 24 329205000 ps
T1146 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2747066333 Jan 21 07:52:20 PM PST 24 Jan 21 07:52:37 PM PST 24 30854600 ps
T1147 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2103790334 Jan 21 07:50:50 PM PST 24 Jan 21 07:51:23 PM PST 24 19140900 ps
T1148 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1235265427 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:52 PM PST 24 37010900 ps
T348 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.725079472 Jan 21 07:50:52 PM PST 24 Jan 21 07:58:36 PM PST 24 419231400 ps
T1149 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2547218681 Jan 21 07:51:25 PM PST 24 Jan 21 07:51:44 PM PST 24 287517000 ps
T1150 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2870389960 Jan 21 07:51:31 PM PST 24 Jan 21 07:51:49 PM PST 24 53562600 ps
T1151 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3230050508 Jan 21 07:52:32 PM PST 24 Jan 21 07:52:51 PM PST 24 150229500 ps
T1152 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1020791579 Jan 21 07:51:14 PM PST 24 Jan 21 07:52:01 PM PST 24 100665900 ps
T1153 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2924156061 Jan 21 07:52:21 PM PST 24 Jan 21 07:52:37 PM PST 24 45858700 ps
T1154 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1017015463 Jan 21 07:51:17 PM PST 24 Jan 21 07:51:34 PM PST 24 155557000 ps
T1155 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3963319503 Jan 21 07:50:44 PM PST 24 Jan 21 07:51:02 PM PST 24 23667200 ps
T1156 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2307366174 Jan 21 07:51:27 PM PST 24 Jan 21 07:51:44 PM PST 24 34571900 ps
T1157 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1440923550 Jan 21 07:51:54 PM PST 24 Jan 21 07:52:11 PM PST 24 71075700 ps
T1158 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1081050916 Jan 21 07:52:17 PM PST 24 Jan 21 07:52:37 PM PST 24 164442800 ps
T351 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3658857232 Jan 21 07:51:41 PM PST 24 Jan 21 07:58:14 PM PST 24 355536500 ps
T1159 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.420401190 Jan 21 07:50:50 PM PST 24 Jan 21 07:51:04 PM PST 24 41207000 ps
T1160 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4244715005 Jan 21 07:51:25 PM PST 24 Jan 21 07:52:02 PM PST 24 986868300 ps
T1161 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2697086134 Jan 21 07:51:54 PM PST 24 Jan 21 07:52:11 PM PST 24 13601200 ps
T1162 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3256082994 Jan 21 08:45:08 PM PST 24 Jan 21 08:45:26 PM PST 24 127631400 ps
T1163 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1739888574 Jan 21 08:30:39 PM PST 24 Jan 21 08:30:57 PM PST 24 25870200 ps
T1164 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3263324300 Jan 21 07:52:00 PM PST 24 Jan 21 07:52:17 PM PST 24 85714200 ps
T1165 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.525145713 Jan 21 07:51:29 PM PST 24 Jan 21 07:51:50 PM PST 24 263504900 ps
T1166 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3880775751 Jan 21 07:52:09 PM PST 24 Jan 21 07:52:23 PM PST 24 14784300 ps
T1167 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.171314866 Jan 21 07:51:46 PM PST 24 Jan 21 07:52:03 PM PST 24 105650900 ps
T1168 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3983422716 Jan 21 07:51:05 PM PST 24 Jan 21 07:51:20 PM PST 24 18486600 ps
T1169 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.68448182 Jan 21 07:51:55 PM PST 24 Jan 21 07:52:14 PM PST 24 179701200 ps
T1170 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2845157903 Jan 21 07:52:34 PM PST 24 Jan 21 07:52:49 PM PST 24 52352100 ps
T1171 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2249102775 Jan 21 07:52:48 PM PST 24 Jan 21 07:53:02 PM PST 24 79311900 ps
T1172 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2081879237 Jan 21 07:50:49 PM PST 24 Jan 21 07:51:08 PM PST 24 148144400 ps
T1173 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1666848974 Jan 21 07:51:56 PM PST 24 Jan 21 07:52:14 PM PST 24 585534600 ps
T1174 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.411819975 Jan 21 07:51:19 PM PST 24 Jan 21 07:51:34 PM PST 24 17751900 ps
T1175 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.936536423 Jan 21 07:52:42 PM PST 24 Jan 21 07:52:59 PM PST 24 32557200 ps
T1176 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2850664253 Jan 21 07:52:18 PM PST 24 Jan 21 07:52:33 PM PST 24 34003200 ps
T1177 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3547790960 Jan 21 07:50:50 PM PST 24 Jan 21 07:51:10 PM PST 24 24953100 ps
T347 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1551628203 Jan 21 07:51:12 PM PST 24 Jan 21 08:06:17 PM PST 24 353658000 ps
T1178 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.986632238 Jan 21 07:52:03 PM PST 24 Jan 21 07:52:22 PM PST 24 60784600 ps
T1179 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.432758397 Jan 21 07:52:29 PM PST 24 Jan 21 07:52:44 PM PST 24 15002000 ps
T1180 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.828029818 Jan 21 07:51:20 PM PST 24 Jan 21 07:51:35 PM PST 24 45068000 ps
T1181 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2232668481 Jan 21 07:52:31 PM PST 24 Jan 21 07:52:49 PM PST 24 33627000 ps
T1182 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3544769414 Jan 21 07:51:44 PM PST 24 Jan 21 07:52:01 PM PST 24 759882000 ps
T1183 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1379257836 Jan 21 07:52:08 PM PST 24 Jan 21 07:52:25 PM PST 24 31167000 ps
T1184 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.954251052 Jan 21 07:52:36 PM PST 24 Jan 21 07:52:51 PM PST 24 28875200 ps
T1185 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2542705937 Jan 21 07:51:17 PM PST 24 Jan 21 07:51:31 PM PST 24 14541900 ps
T1186 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3680105481 Jan 21 07:52:40 PM PST 24 Jan 21 07:52:56 PM PST 24 24518000 ps
T349 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.705755330 Jan 21 07:50:44 PM PST 24 Jan 21 08:03:18 PM PST 24 1594497000 ps
T1187 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1677340961 Jan 21 07:50:59 PM PST 24 Jan 21 07:51:14 PM PST 24 23919200 ps
T260 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2032390681 Jan 21 07:51:05 PM PST 24 Jan 21 07:51:20 PM PST 24 28269500 ps
T278 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2156355632 Jan 21 07:52:35 PM PST 24 Jan 21 08:07:48 PM PST 24 713176400 ps
T1188 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2620762331 Jan 21 07:52:33 PM PST 24 Jan 21 07:52:49 PM PST 24 29539000 ps
T1189 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.297942443 Jan 21 07:51:28 PM PST 24 Jan 21 07:51:42 PM PST 24 15127800 ps
T1190 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.544054759 Jan 21 07:51:29 PM PST 24 Jan 21 07:51:47 PM PST 24 21626800 ps
T1191 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4060464596 Jan 21 07:52:01 PM PST 24 Jan 21 07:52:18 PM PST 24 37988100 ps

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1775809745
Short name T4
Test name
Test status
Simulation time 16570339400 ps
CPU time 612.2 seconds
Started Jan 21 03:33:35 PM PST 24
Finished Jan 21 03:43:49 PM PST 24
Peak memory 271172 kb
Host smart-47454edb-8198-441c-971d-0c16b8b704a6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775809745 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1775809745
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.4227536474
Short name T17
Test name
Test status
Simulation time 290243226500 ps
CPU time 770.47 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:47:02 PM PST 24
Peak memory 262972 kb
Host smart-e8eb0027-afd2-42cb-ba71-d3187688384b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227536474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.4227536474
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3760564910
Short name T179
Test name
Test status
Simulation time 3780532900 ps
CPU time 468.25 seconds
Started Jan 21 07:52:22 PM PST 24
Finished Jan 21 08:00:13 PM PST 24
Peak memory 263380 kb
Host smart-e090a7b4-f129-4f32-b22f-f45737e0f91f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760564910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3760564910
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.811595104
Short name T8
Test name
Test status
Simulation time 1215961100 ps
CPU time 151.02 seconds
Started Jan 21 03:34:49 PM PST 24
Finished Jan 21 03:37:23 PM PST 24
Peak memory 292296 kb
Host smart-c5accf50-e059-4cad-981f-8ebfaa7d4c07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811595104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.811595104
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3775656428
Short name T14
Test name
Test status
Simulation time 143186400 ps
CPU time 129.75 seconds
Started Jan 21 03:42:33 PM PST 24
Finished Jan 21 03:44:45 PM PST 24
Peak memory 258456 kb
Host smart-747aff8b-dab2-405d-a4cd-369e3b04e40b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775656428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3775656428
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1651394314
Short name T20
Test name
Test status
Simulation time 26629895600 ps
CPU time 4940.26 seconds
Started Jan 21 04:27:09 PM PST 24
Finished Jan 21 05:49:31 PM PST 24
Peak memory 282092 kb
Host smart-b12d7fdd-a3fc-46db-8aa3-9e862f1ca498
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651394314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1651394314
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3487001248
Short name T54
Test name
Test status
Simulation time 44324400 ps
CPU time 15.03 seconds
Started Jan 21 07:52:09 PM PST 24
Finished Jan 21 07:52:25 PM PST 24
Peak memory 270136 kb
Host smart-8d34865a-ead6-4bc6-9896-89c2cb304f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487001248 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3487001248
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.1952519211
Short name T2
Test name
Test status
Simulation time 3458435000 ps
CPU time 550.69 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:44:41 PM PST 24
Peak memory 320528 kb
Host smart-77a19b2b-afb5-4e0c-8503-f4383f7e056f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952519211 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.1952519211
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.652611503
Short name T66
Test name
Test status
Simulation time 13486173700 ps
CPU time 482.91 seconds
Started Jan 21 03:34:04 PM PST 24
Finished Jan 21 03:42:17 PM PST 24
Peak memory 261236 kb
Host smart-8afe103f-0177-4ac5-b417-c5dac4c64c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652611503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.652611503
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1689247306
Short name T147
Test name
Test status
Simulation time 3429245900 ps
CPU time 69.17 seconds
Started Jan 21 03:33:38 PM PST 24
Finished Jan 21 03:34:48 PM PST 24
Peak memory 258072 kb
Host smart-635b7f7e-7a5d-49d7-a713-50ef1e671b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689247306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1689247306
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4276589059
Short name T12
Test name
Test status
Simulation time 136914300 ps
CPU time 14.06 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:34:25 PM PST 24
Peak memory 264400 kb
Host smart-7a449fc4-d287-4370-88f6-52d753da9788
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276589059 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4276589059
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1908142900
Short name T181
Test name
Test status
Simulation time 102418600 ps
CPU time 20.78 seconds
Started Jan 21 07:50:48 PM PST 24
Finished Jan 21 07:51:10 PM PST 24
Peak memory 263288 kb
Host smart-edcebd8a-ad86-4ad8-84ed-dd8966920778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908142900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
908142900
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3582635068
Short name T18
Test name
Test status
Simulation time 10019838000 ps
CPU time 89.16 seconds
Started Jan 21 03:36:14 PM PST 24
Finished Jan 21 03:37:44 PM PST 24
Peak memory 329472 kb
Host smart-2021dbcf-f055-4b82-b1b9-f71d969a7a5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582635068 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3582635068
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1340393745
Short name T25
Test name
Test status
Simulation time 6535123800 ps
CPU time 66.11 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:35:26 PM PST 24
Peak memory 261172 kb
Host smart-0fc17e87-dec2-4fe1-b78e-da8ed40503d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340393745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1340393745
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2851925604
Short name T88
Test name
Test status
Simulation time 73195500 ps
CPU time 131.13 seconds
Started Jan 21 03:42:21 PM PST 24
Finished Jan 21 03:44:38 PM PST 24
Peak memory 262204 kb
Host smart-2318c1d7-bc14-46fb-b119-4f7e5b847345
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851925604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2851925604
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.787966257
Short name T242
Test name
Test status
Simulation time 72191500 ps
CPU time 13.7 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261316 kb
Host smart-fa5e7f4f-ea5a-422f-b4cb-e6726ba63b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787966257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.787966257
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3384613835
Short name T352
Test name
Test status
Simulation time 636494800 ps
CPU time 69.74 seconds
Started Jan 21 04:27:04 PM PST 24
Finished Jan 21 04:28:16 PM PST 24
Peak memory 261404 kb
Host smart-bc4ff52e-073a-4caf-833f-58f3266c6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384613835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3384613835
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3852775819
Short name T45
Test name
Test status
Simulation time 573570800 ps
CPU time 22.18 seconds
Started Jan 21 04:00:27 PM PST 24
Finished Jan 21 04:00:51 PM PST 24
Peak memory 264476 kb
Host smart-3c375bda-5dbf-47e8-8e74-6daf73ccc668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852775819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3852775819
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3233589405
Short name T298
Test name
Test status
Simulation time 10019332000 ps
CPU time 166.66 seconds
Started Jan 21 03:40:36 PM PST 24
Finished Jan 21 03:43:24 PM PST 24
Peak memory 282628 kb
Host smart-f1abca07-322f-4a91-8174-c7ec70885778
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233589405 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3233589405
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1113154327
Short name T86
Test name
Test status
Simulation time 48530800 ps
CPU time 13.96 seconds
Started Jan 21 03:35:45 PM PST 24
Finished Jan 21 03:36:00 PM PST 24
Peak memory 264344 kb
Host smart-4acf5a75-25ab-4dc3-a009-760af83ff76d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113154327 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1113154327
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4157525926
Short name T95
Test name
Test status
Simulation time 432544384900 ps
CPU time 1956.07 seconds
Started Jan 21 03:34:10 PM PST 24
Finished Jan 21 04:06:55 PM PST 24
Peak memory 264172 kb
Host smart-3413e0e2-3df9-4b46-8ac9-ca8af3e85bb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157525926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4157525926
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1402367129
Short name T10
Test name
Test status
Simulation time 85266500 ps
CPU time 14.96 seconds
Started Jan 21 03:34:21 PM PST 24
Finished Jan 21 03:34:40 PM PST 24
Peak memory 264364 kb
Host smart-c0a24583-2453-477e-8850-9dcd7dd36e9b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402367129 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1402367129
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1093324751
Short name T244
Test name
Test status
Simulation time 727842800 ps
CPU time 900.26 seconds
Started Jan 21 07:51:27 PM PST 24
Finished Jan 21 08:06:29 PM PST 24
Peak memory 260528 kb
Host smart-cd5380e7-37d8-4e63-843a-4cef7980f40a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093324751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1093324751
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.141759294
Short name T174
Test name
Test status
Simulation time 103295700 ps
CPU time 13.96 seconds
Started Jan 21 03:40:21 PM PST 24
Finished Jan 21 03:40:37 PM PST 24
Peak memory 264164 kb
Host smart-ef38dc23-b734-4897-946a-90bbf795c1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141759294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.141759294
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.997726080
Short name T678
Test name
Test status
Simulation time 86712000 ps
CPU time 111.45 seconds
Started Jan 21 03:34:06 PM PST 24
Finished Jan 21 03:36:07 PM PST 24
Peak memory 258332 kb
Host smart-de47328f-9428-4d82-af61-b0da1eb655b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997726080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp
_reset.997726080
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.4118552276
Short name T91
Test name
Test status
Simulation time 332118782900 ps
CPU time 884.67 seconds
Started Jan 21 03:34:26 PM PST 24
Finished Jan 21 03:49:12 PM PST 24
Peak memory 259760 kb
Host smart-af02d56d-896b-4ca8-ae4f-879236385a3d
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118552276 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.4118552276
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2956674370
Short name T154
Test name
Test status
Simulation time 118320100 ps
CPU time 105.45 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:37:17 PM PST 24
Peak memory 270604 kb
Host smart-6d7dc129-3ac6-44be-92f4-92e17168db70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956674370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2956674370
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3677404648
Short name T57
Test name
Test status
Simulation time 72083467000 ps
CPU time 358.5 seconds
Started Jan 21 03:34:53 PM PST 24
Finished Jan 21 03:40:54 PM PST 24
Peak memory 264284 kb
Host smart-d7334f9e-6c0b-4f96-a52d-0a16c07ec6d4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367
7404648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3677404648
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1064153579
Short name T38
Test name
Test status
Simulation time 398780400 ps
CPU time 741.83 seconds
Started Jan 21 04:09:02 PM PST 24
Finished Jan 21 04:21:25 PM PST 24
Peak memory 280620 kb
Host smart-3cc48672-1c46-44d3-8720-89840dd61391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064153579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1064153579
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.876681715
Short name T16
Test name
Test status
Simulation time 44456800 ps
CPU time 14.73 seconds
Started Jan 21 05:45:32 PM PST 24
Finished Jan 21 05:45:48 PM PST 24
Peak memory 263108 kb
Host smart-7120f9f9-9985-44e2-9bc1-3cd98db37cac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876681715 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.876681715
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.295075523
Short name T392
Test name
Test status
Simulation time 391085100 ps
CPU time 38.36 seconds
Started Jan 21 03:37:43 PM PST 24
Finished Jan 21 03:38:23 PM PST 24
Peak memory 276032 kb
Host smart-05f4de0c-71af-4b7e-9902-8f3dd5b6eb33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295075523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.295075523
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2793257043
Short name T235
Test name
Test status
Simulation time 200792000 ps
CPU time 18.7 seconds
Started Jan 21 07:51:52 PM PST 24
Finished Jan 21 07:52:11 PM PST 24
Peak memory 263300 kb
Host smart-6ca64168-8aef-4f2a-8f0a-395801f38143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793257043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2793257043
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2965911709
Short name T136
Test name
Test status
Simulation time 2541084800 ps
CPU time 67.76 seconds
Started Jan 21 03:37:51 PM PST 24
Finished Jan 21 03:39:01 PM PST 24
Peak memory 258228 kb
Host smart-3927c4c8-9a8a-4059-a58e-7269f1f4194d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965911709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
965911709
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2733138243
Short name T108
Test name
Test status
Simulation time 268402762700 ps
CPU time 1139.19 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:53:19 PM PST 24
Peak memory 272652 kb
Host smart-de2bdd73-e923-4752-b899-d13173932d58
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733138243 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2733138243
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2247568550
Short name T201
Test name
Test status
Simulation time 441427200 ps
CPU time 35.49 seconds
Started Jan 21 03:33:53 PM PST 24
Finished Jan 21 03:34:36 PM PST 24
Peak memory 272656 kb
Host smart-d3e9ff56-d90c-4192-971c-952941a833c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247568550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2247568550
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3142693623
Short name T70
Test name
Test status
Simulation time 12963276200 ps
CPU time 639.29 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:46:08 PM PST 24
Peak memory 329836 kb
Host smart-0435c22b-5b73-43aa-9fd2-b86b3815fcb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142693623 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3142693623
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2526585479
Short name T250
Test name
Test status
Simulation time 159826400 ps
CPU time 13.42 seconds
Started Jan 21 07:50:51 PM PST 24
Finished Jan 21 07:51:06 PM PST 24
Peak memory 262456 kb
Host smart-493fef9b-fced-43dd-a079-9f8a6184d47f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526585479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2526585479
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.2339968043
Short name T215
Test name
Test status
Simulation time 3751571500 ps
CPU time 700.54 seconds
Started Jan 21 03:36:19 PM PST 24
Finished Jan 21 03:48:00 PM PST 24
Peak memory 327844 kb
Host smart-9afc80f7-6fa7-4610-9429-1cb095893519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339968043 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.2339968043
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3559885948
Short name T277
Test name
Test status
Simulation time 1444344000 ps
CPU time 757.51 seconds
Started Jan 21 08:50:43 PM PST 24
Finished Jan 21 09:03:46 PM PST 24
Peak memory 263420 kb
Host smart-f5c81c51-d87b-47d3-9d19-1bea1e0f9483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559885948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.3559885948
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2224022284
Short name T295
Test name
Test status
Simulation time 29227800 ps
CPU time 13.48 seconds
Started Jan 21 03:40:26 PM PST 24
Finished Jan 21 03:40:45 PM PST 24
Peak memory 264340 kb
Host smart-25d28269-439b-4a3e-8374-0e5211845de2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224022284 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.2224022284
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1766899914
Short name T271
Test name
Test status
Simulation time 25056900 ps
CPU time 13.63 seconds
Started Jan 21 07:51:56 PM PST 24
Finished Jan 21 07:52:10 PM PST 24
Peak memory 261516 kb
Host smart-ea887cd5-1fdb-41c5-9224-866e174e1778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766899914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1766899914
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.493407903
Short name T204
Test name
Test status
Simulation time 354996300 ps
CPU time 35.39 seconds
Started Jan 21 03:39:04 PM PST 24
Finished Jan 21 03:39:40 PM PST 24
Peak memory 276324 kb
Host smart-16a799fd-5067-4545-b51f-d3645dcfe0c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493407903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_rw_evict.493407903
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2467180169
Short name T395
Test name
Test status
Simulation time 539815800 ps
CPU time 40.36 seconds
Started Jan 21 05:15:30 PM PST 24
Finished Jan 21 05:16:20 PM PST 24
Peak memory 264380 kb
Host smart-5d3b116a-9d42-4b49-8bea-52e568f5ca5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467180169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2467180169
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3311029575
Short name T340
Test name
Test status
Simulation time 53690000 ps
CPU time 13.6 seconds
Started Jan 21 07:52:21 PM PST 24
Finished Jan 21 07:52:36 PM PST 24
Peak memory 261272 kb
Host smart-68bdbdcf-2bad-41c9-86c2-10133767443a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311029575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3311029575
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2469933075
Short name T32
Test name
Test status
Simulation time 27475200 ps
CPU time 21.08 seconds
Started Jan 21 03:41:46 PM PST 24
Finished Jan 21 03:42:08 PM PST 24
Peak memory 264436 kb
Host smart-6e36a361-da60-4dc2-a77d-7a7699f89799
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469933075 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2469933075
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.534447669
Short name T321
Test name
Test status
Simulation time 11872866100 ps
CPU time 119.99 seconds
Started Jan 21 03:43:03 PM PST 24
Finished Jan 21 03:45:06 PM PST 24
Peak memory 261212 kb
Host smart-1d7ee117-e64c-45b1-9f96-3ac5575fb6ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534447669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.534447669
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.4028826639
Short name T46
Test name
Test status
Simulation time 363265500 ps
CPU time 27 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:34:56 PM PST 24
Peak memory 263248 kb
Host smart-31011b3f-31e5-45f1-acca-507a821b5c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028826639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.4028826639
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1513839253
Short name T73
Test name
Test status
Simulation time 43955200 ps
CPU time 14.04 seconds
Started Jan 21 03:34:16 PM PST 24
Finished Jan 21 03:34:36 PM PST 24
Peak memory 277328 kb
Host smart-f501cf84-4a1d-418b-b4c6-99c53983d7a6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1513839253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1513839253
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1560319678
Short name T119
Test name
Test status
Simulation time 75718300 ps
CPU time 17.19 seconds
Started Jan 21 03:33:58 PM PST 24
Finished Jan 21 03:34:24 PM PST 24
Peak memory 264504 kb
Host smart-c97864bd-222f-426c-927c-fc79ebcf3684
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560319678 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1560319678
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2320180845
Short name T216
Test name
Test status
Simulation time 64131100 ps
CPU time 13.69 seconds
Started Jan 21 03:34:16 PM PST 24
Finished Jan 21 03:34:35 PM PST 24
Peak memory 264328 kb
Host smart-213aa335-4892-4e79-85f3-7b338976f6f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320180845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2320180845
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1560941572
Short name T510
Test name
Test status
Simulation time 31416500 ps
CPU time 30.96 seconds
Started Jan 21 03:39:26 PM PST 24
Finished Jan 21 03:39:59 PM PST 24
Peak memory 273940 kb
Host smart-c00e726d-dd62-4299-9e98-cf344b6faea8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560941572 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1560941572
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.4280047379
Short name T369
Test name
Test status
Simulation time 7294074700 ps
CPU time 64.27 seconds
Started Jan 21 03:42:03 PM PST 24
Finished Jan 21 03:43:09 PM PST 24
Peak memory 258100 kb
Host smart-6744dfba-71b4-40cc-816a-edebb4344109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280047379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.4280047379
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.1374095739
Short name T182
Test name
Test status
Simulation time 15568800 ps
CPU time 15.5 seconds
Started Jan 21 03:41:36 PM PST 24
Finished Jan 21 03:41:52 PM PST 24
Peak memory 273556 kb
Host smart-d8e35970-0575-4288-a101-0f338878de6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374095739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1374095739
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3209827683
Short name T166
Test name
Test status
Simulation time 473467800 ps
CPU time 1996.25 seconds
Started Jan 21 03:34:01 PM PST 24
Finished Jan 21 04:07:27 PM PST 24
Peak memory 262592 kb
Host smart-b0ddb333-5b76-4d2f-85d8-a20b12dcadb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209827683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3209827683
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2244618170
Short name T84
Test name
Test status
Simulation time 24334700 ps
CPU time 13.71 seconds
Started Jan 21 03:34:26 PM PST 24
Finished Jan 21 03:34:41 PM PST 24
Peak memory 264216 kb
Host smart-bd457cab-0598-4ceb-a2cc-3e66533c9c37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244618170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2244618170
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2213533675
Short name T619
Test name
Test status
Simulation time 40565200 ps
CPU time 31.94 seconds
Started Jan 21 03:41:12 PM PST 24
Finished Jan 21 03:41:45 PM PST 24
Peak memory 270968 kb
Host smart-70cae03e-4fe4-4755-ae6c-2602685507ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213533675 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2213533675
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1278153067
Short name T274
Test name
Test status
Simulation time 51309300 ps
CPU time 19.52 seconds
Started Jan 21 07:51:44 PM PST 24
Finished Jan 21 07:52:05 PM PST 24
Peak memory 263368 kb
Host smart-f59242b3-9ccc-4697-a79e-f4f6559a64b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278153067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
278153067
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1369621112
Short name T692
Test name
Test status
Simulation time 504839300 ps
CPU time 1246.13 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:54:18 PM PST 24
Peak memory 272488 kb
Host smart-4bd78cfe-b1d0-483f-b1e7-5b64bcf777c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369621112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1369621112
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3514919255
Short name T308
Test name
Test status
Simulation time 868727600 ps
CPU time 901.6 seconds
Started Jan 21 07:51:58 PM PST 24
Finished Jan 21 08:07:01 PM PST 24
Peak memory 259256 kb
Host smart-80270180-6ea1-4211-9f89-20d673ff104b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514919255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3514919255
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3001129609
Short name T273
Test name
Test status
Simulation time 404041500 ps
CPU time 388.53 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:57:22 PM PST 24
Peak memory 263416 kb
Host smart-ea6bffd9-daba-4a9e-b682-4b5d44019892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001129609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3001129609
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3929424758
Short name T284
Test name
Test status
Simulation time 2187104200 ps
CPU time 142.87 seconds
Started Jan 21 03:39:16 PM PST 24
Finished Jan 21 03:41:39 PM PST 24
Peak memory 292388 kb
Host smart-24b8546e-4a25-49a6-a6dc-afe34b2ec072
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929424758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3929424758
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.338293245
Short name T30
Test name
Test status
Simulation time 37901200 ps
CPU time 14.09 seconds
Started Jan 21 03:33:43 PM PST 24
Finished Jan 21 03:34:04 PM PST 24
Peak memory 264352 kb
Host smart-b902e07c-6023-4b19-98ad-3fa64e49b536
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338293245 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.338293245
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.2363459345
Short name T378
Test name
Test status
Simulation time 343459300 ps
CPU time 56.89 seconds
Started Jan 21 03:38:00 PM PST 24
Finished Jan 21 03:38:58 PM PST 24
Peak memory 261620 kb
Host smart-f052a45a-1724-49e4-b902-8e71d259d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363459345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2363459345
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.387258444
Short name T373
Test name
Test status
Simulation time 4514835000 ps
CPU time 170.09 seconds
Started Jan 21 03:38:48 PM PST 24
Finished Jan 21 03:41:40 PM PST 24
Peak memory 260788 kb
Host smart-089441c7-7168-4b3b-96cf-e66f8e78246f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387258444 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_mp_regions.387258444
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3665014120
Short name T408
Test name
Test status
Simulation time 5358919300 ps
CPU time 168.87 seconds
Started Jan 21 03:39:48 PM PST 24
Finished Jan 21 03:42:38 PM PST 24
Peak memory 282996 kb
Host smart-3bb53610-85c7-4bd5-b323-f813ac178e8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665014120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3665014120
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3298603290
Short name T58
Test name
Test status
Simulation time 19839604500 ps
CPU time 114.06 seconds
Started Jan 21 03:34:18 PM PST 24
Finished Jan 21 03:36:16 PM PST 24
Peak memory 264508 kb
Host smart-42517212-0a7e-4d42-9b93-44a2a5e77320
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298603290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3298603290
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.274808031
Short name T296
Test name
Test status
Simulation time 10070145300 ps
CPU time 40.9 seconds
Started Jan 21 03:34:17 PM PST 24
Finished Jan 21 03:35:03 PM PST 24
Peak memory 264472 kb
Host smart-a6bf65dd-898c-47bf-afe3-0132668632c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274808031 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.274808031
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3094468209
Short name T1058
Test name
Test status
Simulation time 212591800 ps
CPU time 90.52 seconds
Started Jan 21 03:34:26 PM PST 24
Finished Jan 21 03:35:58 PM PST 24
Peak memory 264284 kb
Host smart-2831be38-1131-43fa-98ef-cf7ce48d4474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094468209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3094468209
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1080193216
Short name T770
Test name
Test status
Simulation time 85906100 ps
CPU time 13.93 seconds
Started Jan 21 03:33:55 PM PST 24
Finished Jan 21 03:34:15 PM PST 24
Peak memory 264336 kb
Host smart-bfa1f88d-c280-4fe0-8441-f4980c34bcbe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080193216 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1080193216
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.4057209387
Short name T100
Test name
Test status
Simulation time 13042800 ps
CPU time 22.1 seconds
Started Jan 21 03:33:46 PM PST 24
Finished Jan 21 03:34:15 PM PST 24
Peak memory 264432 kb
Host smart-124bd7b0-7791-42fb-830d-a971d974e940
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057209387 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.4057209387
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.258279002
Short name T140
Test name
Test status
Simulation time 7667668800 ps
CPU time 62.21 seconds
Started Jan 21 03:39:34 PM PST 24
Finished Jan 21 03:40:41 PM PST 24
Peak memory 258024 kb
Host smart-0fa7f24e-f06b-4559-a88f-d2149ce8ded6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258279002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.258279002
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1092562988
Short name T196
Test name
Test status
Simulation time 560699531200 ps
CPU time 2275.67 seconds
Started Jan 21 03:33:34 PM PST 24
Finished Jan 21 04:11:31 PM PST 24
Peak memory 264260 kb
Host smart-01683ab2-8936-4ede-bf77-3f204a9db6bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092562988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1092562988
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.835834926
Short name T346
Test name
Test status
Simulation time 364858300 ps
CPU time 463.54 seconds
Started Jan 21 07:52:04 PM PST 24
Finished Jan 21 07:59:48 PM PST 24
Peak memory 262708 kb
Host smart-797cb94a-f634-4f10-bd95-e3f530f59c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835834926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.835834926
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.2070465712
Short name T898
Test name
Test status
Simulation time 2181461800 ps
CPU time 74.42 seconds
Started Jan 21 03:33:54 PM PST 24
Finished Jan 21 03:35:15 PM PST 24
Peak memory 258100 kb
Host smart-12e319b4-9f76-47fb-b690-ba9ff7c8e0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070465712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2070465712
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.512590519
Short name T33
Test name
Test status
Simulation time 21729900 ps
CPU time 21.47 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 03:34:43 PM PST 24
Peak memory 264452 kb
Host smart-f60e1272-b7de-4890-ae30-3529e72699db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512590519 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.512590519
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3669481459
Short name T845
Test name
Test status
Simulation time 2296194800 ps
CPU time 73.08 seconds
Started Jan 21 03:34:34 PM PST 24
Finished Jan 21 03:35:48 PM PST 24
Peak memory 258116 kb
Host smart-1d7cb7cd-2703-4d5a-a9aa-3bdb5dee838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669481459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3669481459
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.2721475493
Short name T101
Test name
Test status
Simulation time 36119000 ps
CPU time 22.31 seconds
Started Jan 21 03:38:18 PM PST 24
Finished Jan 21 03:38:41 PM PST 24
Peak memory 264376 kb
Host smart-bb5b1340-77c8-41b0-b92e-4e3295b4020c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721475493 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.2721475493
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2919368174
Short name T374
Test name
Test status
Simulation time 1784967800 ps
CPU time 64.51 seconds
Started Jan 21 04:01:54 PM PST 24
Finished Jan 21 04:03:03 PM PST 24
Peak memory 258188 kb
Host smart-4a895069-4d6f-4d32-b48c-41baeead5bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919368174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2919368174
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1192528477
Short name T980
Test name
Test status
Simulation time 2375933500 ps
CPU time 69.45 seconds
Started Jan 21 05:09:52 PM PST 24
Finished Jan 21 05:11:02 PM PST 24
Peak memory 258088 kb
Host smart-0424fccb-db26-42a2-9b7f-f42ae75fd5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192528477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1192528477
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.130997827
Short name T353
Test name
Test status
Simulation time 17285300 ps
CPU time 22.47 seconds
Started Jan 21 03:41:17 PM PST 24
Finished Jan 21 03:41:40 PM PST 24
Peak memory 263852 kb
Host smart-041600da-40ac-4be0-909e-44eef414e41e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130997827 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.130997827
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1192191672
Short name T361
Test name
Test status
Simulation time 511917700 ps
CPU time 59.65 seconds
Started Jan 21 03:59:18 PM PST 24
Finished Jan 21 04:00:18 PM PST 24
Peak memory 261588 kb
Host smart-44b93a1d-ec05-4c13-9059-eda26e214a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192191672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1192191672
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.3992201735
Short name T21
Test name
Test status
Simulation time 993191000 ps
CPU time 4806.46 seconds
Started Jan 21 03:33:46 PM PST 24
Finished Jan 21 04:54:00 PM PST 24
Peak memory 281624 kb
Host smart-0d1d7c69-d815-4148-b1dd-b1d27047c4af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992201735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3992201735
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2722082508
Short name T19
Test name
Test status
Simulation time 25469400 ps
CPU time 13.41 seconds
Started Jan 21 03:38:24 PM PST 24
Finished Jan 21 03:38:40 PM PST 24
Peak memory 264348 kb
Host smart-07cf8c8e-3265-4c14-a2ff-b103098f023a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722082508 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2722082508
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2086237507
Short name T234
Test name
Test status
Simulation time 113705300 ps
CPU time 16.44 seconds
Started Jan 21 07:51:53 PM PST 24
Finished Jan 21 07:52:10 PM PST 24
Peak memory 263252 kb
Host smart-118f3242-16df-4740-8f98-6b69ac39eb7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086237507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2086237507
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3737827539
Short name T218
Test name
Test status
Simulation time 304916900 ps
CPU time 19.09 seconds
Started Jan 21 03:33:55 PM PST 24
Finished Jan 21 03:34:21 PM PST 24
Peak memory 264484 kb
Host smart-f2a68359-d10e-40b3-89e2-44badd6ce7c2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3737827539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3737827539
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3406828384
Short name T454
Test name
Test status
Simulation time 2969720700 ps
CPU time 115.74 seconds
Started Jan 21 04:47:49 PM PST 24
Finished Jan 21 04:49:46 PM PST 24
Peak memory 280472 kb
Host smart-00c7bcf8-5dde-4ab1-b39a-f7e500b945e1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406828384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.3406828384
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2733814149
Short name T246
Test name
Test status
Simulation time 215691300 ps
CPU time 459.16 seconds
Started Jan 21 07:52:01 PM PST 24
Finished Jan 21 07:59:41 PM PST 24
Peak memory 260488 kb
Host smart-ecf0f168-0883-4017-882f-4947e70fb832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733814149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2733814149
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3314101227
Short name T232
Test name
Test status
Simulation time 665259100 ps
CPU time 903.81 seconds
Started Jan 21 07:52:12 PM PST 24
Finished Jan 21 08:07:18 PM PST 24
Peak memory 259316 kb
Host smart-e66e306a-0041-4c17-b78b-4ad943c17f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314101227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3314101227
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2156355632
Short name T278
Test name
Test status
Simulation time 713176400 ps
CPU time 911.72 seconds
Started Jan 21 07:52:35 PM PST 24
Finished Jan 21 08:07:48 PM PST 24
Peak memory 260320 kb
Host smart-9a46083e-14e7-4bef-b49a-c62e75c5d50e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156355632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.2156355632
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.3119648609
Short name T385
Test name
Test status
Simulation time 3981108800 ps
CPU time 2210.27 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 04:10:33 PM PST 24
Peak memory 263904 kb
Host smart-a371ef2c-42f6-40c6-80e0-8a0caac2bc65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119648609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.3119648609
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1300627365
Short name T287
Test name
Test status
Simulation time 155878400 ps
CPU time 71.99 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:34:45 PM PST 24
Peak memory 263744 kb
Host smart-2be249fe-37e6-470d-a307-3b234c82389c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300627365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1300627365
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1631542182
Short name T327
Test name
Test status
Simulation time 1468984700 ps
CPU time 170.05 seconds
Started Jan 21 03:34:04 PM PST 24
Finished Jan 21 03:37:04 PM PST 24
Peak memory 292340 kb
Host smart-109ecbfa-24b9-4094-a891-aaa9141ab020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631542182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1631542182
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.890284310
Short name T199
Test name
Test status
Simulation time 15485232800 ps
CPU time 568.09 seconds
Started Jan 21 03:34:43 PM PST 24
Finished Jan 21 03:44:13 PM PST 24
Peak memory 335600 kb
Host smart-ebfb1099-a352-45c7-8983-db6ec2943ba4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890284310 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_rw_derr.890284310
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3907598719
Short name T200
Test name
Test status
Simulation time 1330242300 ps
CPU time 117.15 seconds
Started Jan 21 03:58:14 PM PST 24
Finished Jan 21 04:00:17 PM PST 24
Peak memory 292628 kb
Host smart-697549a0-aa48-4130-b2dc-63515ec450fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907598719 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3907598719
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1910980034
Short name T304
Test name
Test status
Simulation time 14076438400 ps
CPU time 68.56 seconds
Started Jan 21 07:50:47 PM PST 24
Finished Jan 21 07:51:57 PM PST 24
Peak memory 259228 kb
Host smart-b22537d3-3212-472d-8bd0-19a2982e1b75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910980034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1910980034
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.723695626
Short name T1090
Test name
Test status
Simulation time 7859401300 ps
CPU time 51.03 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:51:45 PM PST 24
Peak memory 259236 kb
Host smart-5e14baab-3523-4f93-a812-43ea6b67209e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723695626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.723695626
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2103790334
Short name T1147
Test name
Test status
Simulation time 19140900 ps
CPU time 31.61 seconds
Started Jan 21 07:50:50 PM PST 24
Finished Jan 21 07:51:23 PM PST 24
Peak memory 259276 kb
Host smart-394c7806-71f1-4750-91b5-0116b4a1fa36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103790334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2103790334
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3547790960
Short name T1177
Test name
Test status
Simulation time 24953100 ps
CPU time 18.37 seconds
Started Jan 21 07:50:50 PM PST 24
Finished Jan 21 07:51:10 PM PST 24
Peak memory 271600 kb
Host smart-c29dc96f-32d5-4afa-bcc4-93ddb0b7895e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547790960 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3547790960
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1577575020
Short name T1122
Test name
Test status
Simulation time 139771000 ps
CPU time 17.82 seconds
Started Jan 21 07:50:49 PM PST 24
Finished Jan 21 07:51:08 PM PST 24
Peak memory 259244 kb
Host smart-56cd4b7c-ec0c-466a-baec-a4c26d7ae30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577575020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1577575020
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3459717903
Short name T1113
Test name
Test status
Simulation time 46145300 ps
CPU time 13.96 seconds
Started Jan 21 07:50:45 PM PST 24
Finished Jan 21 07:51:01 PM PST 24
Peak memory 261120 kb
Host smart-b7110b21-c351-4fdd-8adf-5a01cad07958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459717903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
459717903
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2579073227
Short name T1084
Test name
Test status
Simulation time 23102400 ps
CPU time 13.42 seconds
Started Jan 21 07:50:46 PM PST 24
Finished Jan 21 07:51:01 PM PST 24
Peak memory 261440 kb
Host smart-769b0bcd-1c3e-4023-ae52-cc00b0682c79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579073227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2579073227
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1888323985
Short name T255
Test name
Test status
Simulation time 386715900 ps
CPU time 35.45 seconds
Started Jan 21 07:50:50 PM PST 24
Finished Jan 21 07:51:27 PM PST 24
Peak memory 259268 kb
Host smart-f9e45446-2c4f-4e3e-ab88-e7739e59e3e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888323985 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1888323985
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.548665623
Short name T1131
Test name
Test status
Simulation time 12773600 ps
CPU time 15.84 seconds
Started Jan 21 07:50:44 PM PST 24
Finished Jan 21 07:51:01 PM PST 24
Peak memory 259124 kb
Host smart-4ef04384-ad6c-4608-ab9c-7ee83e27dc50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548665623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.548665623
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.420401190
Short name T1159
Test name
Test status
Simulation time 41207000 ps
CPU time 13.16 seconds
Started Jan 21 07:50:50 PM PST 24
Finished Jan 21 07:51:04 PM PST 24
Peak memory 259208 kb
Host smart-472293f5-c697-4437-9df7-8712cf3db798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420401190 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.420401190
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.705755330
Short name T349
Test name
Test status
Simulation time 1594497000 ps
CPU time 752.88 seconds
Started Jan 21 07:50:44 PM PST 24
Finished Jan 21 08:03:18 PM PST 24
Peak memory 260448 kb
Host smart-19f8fa7d-8c50-480a-811b-79eb323122f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705755330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.705755330
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2482086331
Short name T266
Test name
Test status
Simulation time 2838653200 ps
CPU time 60.42 seconds
Started Jan 21 07:50:55 PM PST 24
Finished Jan 21 07:51:56 PM PST 24
Peak memory 259536 kb
Host smart-2701ed16-de79-4658-86b4-939aca9d01b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482086331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2482086331
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1109356447
Short name T1092
Test name
Test status
Simulation time 6405129900 ps
CPU time 39.91 seconds
Started Jan 21 07:50:47 PM PST 24
Finished Jan 21 07:51:29 PM PST 24
Peak memory 259356 kb
Host smart-36cde49f-11a3-4794-b9a6-4dcd839260b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109356447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1109356447
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3554646450
Short name T315
Test name
Test status
Simulation time 116888700 ps
CPU time 31.04 seconds
Started Jan 21 07:50:44 PM PST 24
Finished Jan 21 07:51:16 PM PST 24
Peak memory 259188 kb
Host smart-46ec3f57-c31d-4e4c-9099-09c8d9b469de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554646450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3554646450
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2318119166
Short name T1091
Test name
Test status
Simulation time 45601300 ps
CPU time 15.99 seconds
Started Jan 21 07:50:54 PM PST 24
Finished Jan 21 07:51:11 PM PST 24
Peak memory 271588 kb
Host smart-f5433c20-ec18-4dfd-bc23-a22402df27b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318119166 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2318119166
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2544609582
Short name T1135
Test name
Test status
Simulation time 60046800 ps
CPU time 17.16 seconds
Started Jan 21 07:50:48 PM PST 24
Finished Jan 21 07:51:07 PM PST 24
Peak memory 259204 kb
Host smart-5f9bf1d8-5044-41aa-99f9-7f60041a0ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544609582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.2544609582
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.233095309
Short name T1094
Test name
Test status
Simulation time 88023400 ps
CPU time 13.59 seconds
Started Jan 21 07:50:47 PM PST 24
Finished Jan 21 07:51:02 PM PST 24
Peak memory 261164 kb
Host smart-7e8de6b1-26da-48d7-b112-63c70d5582f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233095309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.233095309
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3684119186
Short name T259
Test name
Test status
Simulation time 29463900 ps
CPU time 13.8 seconds
Started Jan 21 07:50:47 PM PST 24
Finished Jan 21 07:51:02 PM PST 24
Peak memory 262468 kb
Host smart-744cae0e-7d6c-494f-8bb1-fa14b0d3a1c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684119186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.3684119186
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3825780615
Short name T1095
Test name
Test status
Simulation time 47397000 ps
CPU time 13.91 seconds
Started Jan 21 07:50:51 PM PST 24
Finished Jan 21 07:51:06 PM PST 24
Peak memory 260416 kb
Host smart-97a7857e-62af-4c66-8b83-74b858f809e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825780615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3825780615
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1178744434
Short name T1137
Test name
Test status
Simulation time 289337700 ps
CPU time 18.14 seconds
Started Jan 21 07:50:51 PM PST 24
Finished Jan 21 07:51:11 PM PST 24
Peak memory 259272 kb
Host smart-b76ba88e-d036-49fb-96ef-c505f56ae13f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178744434 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1178744434
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3963319503
Short name T1155
Test name
Test status
Simulation time 23667200 ps
CPU time 15.92 seconds
Started Jan 21 07:50:44 PM PST 24
Finished Jan 21 07:51:02 PM PST 24
Peak memory 259132 kb
Host smart-f4eb6c7b-7103-4bab-825b-e4fbdacf1be8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963319503 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3963319503
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.164322691
Short name T1096
Test name
Test status
Simulation time 28825600 ps
CPU time 15.83 seconds
Started Jan 21 07:50:47 PM PST 24
Finished Jan 21 07:51:05 PM PST 24
Peak memory 259056 kb
Host smart-a2fcee01-1579-4880-9e92-50ca6a725d35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164322691 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.164322691
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2081879237
Short name T1172
Test name
Test status
Simulation time 148144400 ps
CPU time 16.91 seconds
Started Jan 21 07:50:49 PM PST 24
Finished Jan 21 07:51:08 PM PST 24
Peak memory 263356 kb
Host smart-4f054750-15a7-474e-8215-73776dcd724f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081879237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
081879237
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.725079472
Short name T348
Test name
Test status
Simulation time 419231400 ps
CPU time 462.27 seconds
Started Jan 21 07:50:52 PM PST 24
Finished Jan 21 07:58:36 PM PST 24
Peak memory 260368 kb
Host smart-c3ff78b6-28a9-4b0f-af96-c1988b72516a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725079472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
tl_intg_err.725079472
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2418196138
Short name T1082
Test name
Test status
Simulation time 66705400 ps
CPU time 17.57 seconds
Started Jan 21 07:52:01 PM PST 24
Finished Jan 21 07:52:20 PM PST 24
Peak memory 270656 kb
Host smart-9c1cdc91-3687-46a5-9333-0e8def16de0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418196138 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2418196138
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1143051381
Short name T180
Test name
Test status
Simulation time 367253600 ps
CPU time 14.73 seconds
Started Jan 21 07:51:55 PM PST 24
Finished Jan 21 07:52:10 PM PST 24
Peak memory 259272 kb
Host smart-dcfd1241-e471-49e6-8965-834d24bb921b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143051381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.1143051381
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4060464596
Short name T1191
Test name
Test status
Simulation time 37988100 ps
CPU time 15.18 seconds
Started Jan 21 07:52:01 PM PST 24
Finished Jan 21 07:52:18 PM PST 24
Peak memory 260932 kb
Host smart-363266fc-cf16-417e-b2c1-ed59c2806f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060464596 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.4060464596
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1307714743
Short name T307
Test name
Test status
Simulation time 42365200 ps
CPU time 13.67 seconds
Started Jan 21 07:51:51 PM PST 24
Finished Jan 21 07:52:05 PM PST 24
Peak memory 259172 kb
Host smart-c633883d-5acc-414f-a467-aff8380e8679
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307714743 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1307714743
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2948060033
Short name T1063
Test name
Test status
Simulation time 12594800 ps
CPU time 15.78 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:11 PM PST 24
Peak memory 259064 kb
Host smart-8c1d103a-7295-4659-adfd-9ac754bad0e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948060033 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2948060033
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3293972702
Short name T55
Test name
Test status
Simulation time 28771400 ps
CPU time 17.33 seconds
Started Jan 21 07:51:55 PM PST 24
Finished Jan 21 07:52:13 PM PST 24
Peak memory 275416 kb
Host smart-912fb7dc-67df-470b-a537-cdf23ccc2ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293972702 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3293972702
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3470888022
Short name T303
Test name
Test status
Simulation time 158516400 ps
CPU time 13.87 seconds
Started Jan 21 07:51:53 PM PST 24
Finished Jan 21 07:52:08 PM PST 24
Peak memory 259160 kb
Host smart-0b52e54b-abad-4e53-b4eb-1e113cd2ea6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470888022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3470888022
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1353266218
Short name T243
Test name
Test status
Simulation time 157335000 ps
CPU time 14.02 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:09 PM PST 24
Peak memory 261332 kb
Host smart-ae31d0d6-3db5-430c-86ea-1e2d7b034ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353266218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1353266218
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.68448182
Short name T1169
Test name
Test status
Simulation time 179701200 ps
CPU time 18.32 seconds
Started Jan 21 07:51:55 PM PST 24
Finished Jan 21 07:52:14 PM PST 24
Peak memory 259220 kb
Host smart-70e507b8-cebf-4266-bc6b-67f2e1a30c7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68448182 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.68448182
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3120050017
Short name T1109
Test name
Test status
Simulation time 14011700 ps
CPU time 13.32 seconds
Started Jan 21 07:52:00 PM PST 24
Finished Jan 21 07:52:14 PM PST 24
Peak memory 259116 kb
Host smart-7649fc4e-9550-4e1b-ba22-4e2911376991
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120050017 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3120050017
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2697086134
Short name T1161
Test name
Test status
Simulation time 13601200 ps
CPU time 15.94 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:11 PM PST 24
Peak memory 259164 kb
Host smart-dfd525c0-0d70-4c65-ba15-7f3d3325aae7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697086134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2697086134
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.69697868
Short name T350
Test name
Test status
Simulation time 353554500 ps
CPU time 473.14 seconds
Started Jan 21 07:51:59 PM PST 24
Finished Jan 21 07:59:53 PM PST 24
Peak memory 263328 kb
Host smart-39916a9a-2bff-4866-a00b-18bdb757ff22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69697868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
tl_intg_err.69697868
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3263324300
Short name T1164
Test name
Test status
Simulation time 85714200 ps
CPU time 15.57 seconds
Started Jan 21 07:52:00 PM PST 24
Finished Jan 21 07:52:17 PM PST 24
Peak memory 271468 kb
Host smart-d71fe42a-6f40-4160-b121-570a92f46714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263324300 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3263324300
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1666848974
Short name T1173
Test name
Test status
Simulation time 585534600 ps
CPU time 16.81 seconds
Started Jan 21 07:51:56 PM PST 24
Finished Jan 21 07:52:14 PM PST 24
Peak memory 259296 kb
Host smart-14966f54-cbe3-40ea-b2fa-0595acf8dee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666848974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1666848974
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4256800853
Short name T1089
Test name
Test status
Simulation time 17593600 ps
CPU time 13.56 seconds
Started Jan 21 07:52:03 PM PST 24
Finished Jan 21 07:52:18 PM PST 24
Peak memory 261596 kb
Host smart-de84196a-bac0-4c6c-b838-0079a4bfe5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256800853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
4256800853
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2421709135
Short name T318
Test name
Test status
Simulation time 740204800 ps
CPU time 17.61 seconds
Started Jan 21 09:18:33 PM PST 24
Finished Jan 21 09:18:57 PM PST 24
Peak memory 259252 kb
Host smart-f3866e1f-8c2e-45b6-bbb6-22288db8a9de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421709135 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2421709135
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.353944250
Short name T1134
Test name
Test status
Simulation time 138106700 ps
CPU time 16.12 seconds
Started Jan 21 07:51:53 PM PST 24
Finished Jan 21 07:52:10 PM PST 24
Peak memory 259272 kb
Host smart-1b12591f-8789-41ab-88a8-d2eff722d743
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353944250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.353944250
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1440923550
Short name T1157
Test name
Test status
Simulation time 71075700 ps
CPU time 15.67 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:11 PM PST 24
Peak memory 259228 kb
Host smart-30cf651f-b06e-4c3b-afd1-821f2a9bd500
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440923550 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1440923550
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3416231361
Short name T1111
Test name
Test status
Simulation time 48159900 ps
CPU time 19.45 seconds
Started Jan 21 07:51:55 PM PST 24
Finished Jan 21 07:52:16 PM PST 24
Peak memory 263260 kb
Host smart-79304ea6-276a-407b-8afe-b31ca418dcd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416231361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3416231361
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.423768284
Short name T237
Test name
Test status
Simulation time 149475800 ps
CPU time 15.47 seconds
Started Jan 21 07:51:57 PM PST 24
Finished Jan 21 07:52:14 PM PST 24
Peak memory 270056 kb
Host smart-309d1c9d-fa01-428a-a666-b4cdb24d83b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423768284 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.423768284
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.986632238
Short name T1178
Test name
Test status
Simulation time 60784600 ps
CPU time 17.5 seconds
Started Jan 21 07:52:03 PM PST 24
Finished Jan 21 07:52:22 PM PST 24
Peak memory 259276 kb
Host smart-f5ad250b-a3a7-4a19-8128-c54eae21093b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986632238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.986632238
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.479637741
Short name T1075
Test name
Test status
Simulation time 24093000 ps
CPU time 13.66 seconds
Started Jan 21 07:52:04 PM PST 24
Finished Jan 21 07:52:19 PM PST 24
Peak memory 261432 kb
Host smart-6ec87f43-b048-49d4-ad3c-d764f20a8e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479637741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.479637741
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1640292267
Short name T1145
Test name
Test status
Simulation time 329205000 ps
CPU time 17.66 seconds
Started Jan 21 07:51:56 PM PST 24
Finished Jan 21 07:52:15 PM PST 24
Peak memory 259216 kb
Host smart-c986aa1d-d0c9-4f45-91a5-51ff219d3576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640292267 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1640292267
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1541838103
Short name T1064
Test name
Test status
Simulation time 20324800 ps
CPU time 12.94 seconds
Started Jan 21 07:52:06 PM PST 24
Finished Jan 21 07:52:20 PM PST 24
Peak memory 259176 kb
Host smart-b95f7707-83b9-4957-868f-033d078c0be9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541838103 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.1541838103
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.174061495
Short name T1117
Test name
Test status
Simulation time 15113300 ps
CPU time 13.68 seconds
Started Jan 21 07:52:03 PM PST 24
Finished Jan 21 07:52:18 PM PST 24
Peak memory 259156 kb
Host smart-e5a9d6a4-1ee5-49ed-a4fd-1cfb2e05daad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174061495 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.174061495
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3256082994
Short name T1162
Test name
Test status
Simulation time 127631400 ps
CPU time 16.26 seconds
Started Jan 21 08:45:08 PM PST 24
Finished Jan 21 08:45:26 PM PST 24
Peak memory 263352 kb
Host smart-c2f7bc31-d584-407e-bc1f-e0bd8c799753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256082994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3256082994
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3872847677
Short name T1142
Test name
Test status
Simulation time 207363600 ps
CPU time 18.03 seconds
Started Jan 21 07:52:12 PM PST 24
Finished Jan 21 07:52:32 PM PST 24
Peak memory 269244 kb
Host smart-1c09fd87-bf29-4aab-b8cb-b8f891498509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872847677 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3872847677
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.153423739
Short name T224
Test name
Test status
Simulation time 91227700 ps
CPU time 17.36 seconds
Started Jan 21 07:52:13 PM PST 24
Finished Jan 21 07:52:32 PM PST 24
Peak memory 259400 kb
Host smart-109abcfc-ec31-447e-a1b8-3ed142ef353f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153423739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_csr_rw.153423739
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3880775751
Short name T1166
Test name
Test status
Simulation time 14784300 ps
CPU time 13.57 seconds
Started Jan 21 07:52:09 PM PST 24
Finished Jan 21 07:52:23 PM PST 24
Peak memory 261400 kb
Host smart-0d8e24d1-94e6-4247-bc2d-b6cf0ddca938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880775751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3880775751
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1081050916
Short name T1158
Test name
Test status
Simulation time 164442800 ps
CPU time 18.78 seconds
Started Jan 21 07:52:17 PM PST 24
Finished Jan 21 07:52:37 PM PST 24
Peak memory 259336 kb
Host smart-65b98faa-eccb-4cac-8ea8-8a9b6c6ae804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081050916 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1081050916
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2783675750
Short name T1144
Test name
Test status
Simulation time 27624500 ps
CPU time 15.7 seconds
Started Jan 21 07:52:04 PM PST 24
Finished Jan 21 07:52:21 PM PST 24
Peak memory 259124 kb
Host smart-14dbc51e-0cfb-4fea-8470-13038fffa648
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783675750 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2783675750
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.341372359
Short name T1076
Test name
Test status
Simulation time 47738700 ps
CPU time 15.55 seconds
Started Jan 21 08:40:41 PM PST 24
Finished Jan 21 08:40:57 PM PST 24
Peak memory 259204 kb
Host smart-8713463e-5ffd-4753-b023-e65311a901dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341372359 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.341372359
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3797840662
Short name T270
Test name
Test status
Simulation time 54469100 ps
CPU time 18.89 seconds
Started Jan 21 08:32:47 PM PST 24
Finished Jan 21 08:33:08 PM PST 24
Peak memory 263284 kb
Host smart-d38cd9d7-fd9e-4671-bbc5-53ee0642281c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797840662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3797840662
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3386246344
Short name T1100
Test name
Test status
Simulation time 22296200 ps
CPU time 16.72 seconds
Started Jan 21 07:52:12 PM PST 24
Finished Jan 21 07:52:30 PM PST 24
Peak memory 259152 kb
Host smart-40622432-3b20-445f-b7af-76744367d93f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386246344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.3386246344
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.623723442
Short name T1115
Test name
Test status
Simulation time 52667500 ps
CPU time 14.36 seconds
Started Jan 21 07:52:12 PM PST 24
Finished Jan 21 07:52:27 PM PST 24
Peak memory 261524 kb
Host smart-8ab73346-8950-480e-96f7-ce275b17f9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623723442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.623723442
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2749342873
Short name T301
Test name
Test status
Simulation time 1014001800 ps
CPU time 19.03 seconds
Started Jan 21 07:52:12 PM PST 24
Finished Jan 21 07:52:32 PM PST 24
Peak memory 259228 kb
Host smart-2d842a3f-6add-4d28-92b2-a0428574e76a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749342873 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2749342873
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.251911020
Short name T1125
Test name
Test status
Simulation time 45364800 ps
CPU time 16.21 seconds
Started Jan 21 07:52:16 PM PST 24
Finished Jan 21 07:52:34 PM PST 24
Peak memory 259208 kb
Host smart-e2ba5bf5-825c-4e78-bae7-f00169639829
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251911020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.251911020
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3099105498
Short name T1107
Test name
Test status
Simulation time 17816300 ps
CPU time 15.94 seconds
Started Jan 21 07:52:17 PM PST 24
Finished Jan 21 07:52:34 PM PST 24
Peak memory 259136 kb
Host smart-cd69c7a8-4881-40f2-9241-600b3fb5947c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099105498 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3099105498
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1379257836
Short name T1183
Test name
Test status
Simulation time 31167000 ps
CPU time 16.15 seconds
Started Jan 21 07:52:08 PM PST 24
Finished Jan 21 07:52:25 PM PST 24
Peak memory 263284 kb
Host smart-6bca423b-1dd5-4e7d-8a3b-f76b9684906c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379257836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1379257836
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4192300361
Short name T222
Test name
Test status
Simulation time 91724100 ps
CPU time 18.21 seconds
Started Jan 21 07:52:18 PM PST 24
Finished Jan 21 07:52:37 PM PST 24
Peak memory 269508 kb
Host smart-d92eadd2-1ea7-48d7-841b-f480bed995d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192300361 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4192300361
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1622260852
Short name T314
Test name
Test status
Simulation time 38271600 ps
CPU time 17.32 seconds
Started Jan 21 07:52:22 PM PST 24
Finished Jan 21 07:52:40 PM PST 24
Peak memory 259244 kb
Host smart-f15ddec6-8d70-4aab-81f5-0966745cadc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622260852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1622260852
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2658039316
Short name T1110
Test name
Test status
Simulation time 54293700 ps
CPU time 13.5 seconds
Started Jan 21 07:52:21 PM PST 24
Finished Jan 21 07:52:36 PM PST 24
Peak memory 261464 kb
Host smart-2a592cae-3eb8-4a26-8f37-7f3af83ee1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658039316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
2658039316
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2222988926
Short name T253
Test name
Test status
Simulation time 152626800 ps
CPU time 18.79 seconds
Started Jan 21 07:52:22 PM PST 24
Finished Jan 21 07:52:42 PM PST 24
Peak memory 261360 kb
Host smart-628f630c-9158-4e44-8b33-ee68bcfef79f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222988926 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2222988926
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2924156061
Short name T1153
Test name
Test status
Simulation time 45858700 ps
CPU time 15.67 seconds
Started Jan 21 07:52:21 PM PST 24
Finished Jan 21 07:52:37 PM PST 24
Peak memory 259200 kb
Host smart-174646e5-cf2c-4b33-a5dd-30d813fa47be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924156061 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2924156061
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2850664253
Short name T1176
Test name
Test status
Simulation time 34003200 ps
CPU time 13.29 seconds
Started Jan 21 07:52:18 PM PST 24
Finished Jan 21 07:52:33 PM PST 24
Peak memory 259192 kb
Host smart-7ee78fb7-1165-4565-8466-5223791f29e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850664253 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2850664253
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3461068404
Short name T239
Test name
Test status
Simulation time 164761400 ps
CPU time 18.43 seconds
Started Jan 21 07:52:22 PM PST 24
Finished Jan 21 07:52:43 PM PST 24
Peak memory 263332 kb
Host smart-5b9e815d-2bcd-4b81-9eed-d368896596fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461068404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3461068404
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3552383308
Short name T1112
Test name
Test status
Simulation time 406351700 ps
CPU time 461.04 seconds
Started Jan 21 07:52:23 PM PST 24
Finished Jan 21 08:00:05 PM PST 24
Peak memory 263472 kb
Host smart-4bfc93e2-3fd7-42d5-8591-287c4f0f7b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552383308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3552383308
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2540976801
Short name T238
Test name
Test status
Simulation time 32085900 ps
CPU time 19.63 seconds
Started Jan 21 07:52:34 PM PST 24
Finished Jan 21 07:52:55 PM PST 24
Peak memory 276612 kb
Host smart-35f6fb14-0b9c-417a-9ba8-53546eaaa22d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540976801 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2540976801
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1208576064
Short name T1087
Test name
Test status
Simulation time 20301900 ps
CPU time 16.55 seconds
Started Jan 21 07:52:24 PM PST 24
Finished Jan 21 07:52:42 PM PST 24
Peak memory 259220 kb
Host smart-9ef16365-b1c6-494e-b1a6-992b60d7b929
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208576064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1208576064
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3230050508
Short name T1151
Test name
Test status
Simulation time 150229500 ps
CPU time 18.4 seconds
Started Jan 21 07:52:32 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 259188 kb
Host smart-e2d895ba-80c9-45e7-b1d3-b2ac9367284b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230050508 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3230050508
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2747066333
Short name T1146
Test name
Test status
Simulation time 30854600 ps
CPU time 15.72 seconds
Started Jan 21 07:52:20 PM PST 24
Finished Jan 21 07:52:37 PM PST 24
Peak memory 259220 kb
Host smart-7843a697-9e66-46b8-b787-08fb9abfcb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747066333 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2747066333
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1649561428
Short name T1074
Test name
Test status
Simulation time 20848300 ps
CPU time 15.8 seconds
Started Jan 21 07:52:22 PM PST 24
Finished Jan 21 07:52:41 PM PST 24
Peak memory 259192 kb
Host smart-4481e651-8ae4-44f8-a224-e860d72dc811
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649561428 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1649561428
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2775418958
Short name T236
Test name
Test status
Simulation time 33692100 ps
CPU time 16.24 seconds
Started Jan 21 07:52:21 PM PST 24
Finished Jan 21 07:52:39 PM PST 24
Peak memory 263256 kb
Host smart-9ceeb782-e9c4-4b13-9a39-1d0c0cf0b6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775418958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2775418958
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1235265427
Short name T1148
Test name
Test status
Simulation time 37010900 ps
CPU time 17.01 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:52 PM PST 24
Peak memory 262840 kb
Host smart-ffdb0e83-c29a-47bf-9d09-d1b315cae7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235265427 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1235265427
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.422464183
Short name T310
Test name
Test status
Simulation time 37071500 ps
CPU time 17.05 seconds
Started Jan 21 07:52:31 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 259168 kb
Host smart-703d06fd-909b-42e0-a389-21da494103e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422464183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_csr_rw.422464183
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3510727109
Short name T343
Test name
Test status
Simulation time 17327400 ps
CPU time 13.63 seconds
Started Jan 21 07:52:42 PM PST 24
Finished Jan 21 07:52:56 PM PST 24
Peak memory 261508 kb
Host smart-4a3b2c30-672e-4f4c-b984-b63c2019181f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510727109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3510727109
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2255923598
Short name T1088
Test name
Test status
Simulation time 384588000 ps
CPU time 29.77 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:57 PM PST 24
Peak memory 259192 kb
Host smart-3ec67155-a69f-4da2-9981-d6256220d4f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255923598 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2255923598
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3275844950
Short name T306
Test name
Test status
Simulation time 32490000 ps
CPU time 15.76 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 259176 kb
Host smart-b09d4019-d59f-4869-b402-7bae2b534555
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275844950 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.3275844950
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4005174424
Short name T1068
Test name
Test status
Simulation time 43491000 ps
CPU time 15.92 seconds
Started Jan 21 07:52:29 PM PST 24
Finished Jan 21 07:52:45 PM PST 24
Peak memory 259128 kb
Host smart-ae4726ab-741d-4b4d-b007-8b1885b06ad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005174424 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.4005174424
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.67142153
Short name T275
Test name
Test status
Simulation time 125856800 ps
CPU time 17.31 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 263340 kb
Host smart-cd1fa6ba-0fb4-48c9-92a9-88dddf4d472f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67142153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.67142153
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3407106879
Short name T345
Test name
Test status
Simulation time 512439200 ps
CPU time 466.77 seconds
Started Jan 21 07:52:30 PM PST 24
Finished Jan 21 08:00:18 PM PST 24
Peak memory 260584 kb
Host smart-6d8e694d-1baa-4454-bc26-90c8d46f2ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407106879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3407106879
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3803725820
Short name T1143
Test name
Test status
Simulation time 43418100 ps
CPU time 15.52 seconds
Started Jan 21 07:52:35 PM PST 24
Finished Jan 21 07:52:52 PM PST 24
Peak memory 261824 kb
Host smart-75135439-09c1-4990-bf68-0cbc817c49d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803725820 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3803725820
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2232668481
Short name T1181
Test name
Test status
Simulation time 33627000 ps
CPU time 16.64 seconds
Started Jan 21 07:52:31 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 259244 kb
Host smart-e2f4aefe-3563-4b4b-af86-001939f86af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232668481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2232668481
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1864502407
Short name T1128
Test name
Test status
Simulation time 27105700 ps
CPU time 13.62 seconds
Started Jan 21 07:52:29 PM PST 24
Finished Jan 21 07:52:44 PM PST 24
Peak memory 261380 kb
Host smart-83badc11-5ae9-4fdb-a5d9-29fac38f0e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864502407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1864502407
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1361420221
Short name T226
Test name
Test status
Simulation time 1739152500 ps
CPU time 37.03 seconds
Started Jan 21 09:45:40 PM PST 24
Finished Jan 21 09:46:22 PM PST 24
Peak memory 259044 kb
Host smart-5c840d29-2301-4691-a61b-cf68d3dfebf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361420221 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1361420221
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.432758397
Short name T1179
Test name
Test status
Simulation time 15002000 ps
CPU time 13.58 seconds
Started Jan 21 07:52:29 PM PST 24
Finished Jan 21 07:52:44 PM PST 24
Peak memory 259136 kb
Host smart-dbb6b7d8-717b-4a85-87b3-178bf8c7a3b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432758397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.432758397
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.936536423
Short name T1175
Test name
Test status
Simulation time 32557200 ps
CPU time 15.86 seconds
Started Jan 21 07:52:42 PM PST 24
Finished Jan 21 07:52:59 PM PST 24
Peak memory 259124 kb
Host smart-f9f7c4f6-1a93-42c9-b652-bef74f0edbbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936536423 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.936536423
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1214820347
Short name T276
Test name
Test status
Simulation time 535875700 ps
CPU time 18.37 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:53 PM PST 24
Peak memory 263348 kb
Host smart-85a0343c-d21e-4e1e-af88-e874dfb97f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214820347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
1214820347
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2522152736
Short name T1118
Test name
Test status
Simulation time 2112065900 ps
CPU time 36.88 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:51:30 PM PST 24
Peak memory 259340 kb
Host smart-13c6bad6-b429-4e5b-b40d-f70623eb2a8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522152736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2522152736
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3417618327
Short name T312
Test name
Test status
Simulation time 864557700 ps
CPU time 37.95 seconds
Started Jan 21 07:50:58 PM PST 24
Finished Jan 21 07:51:37 PM PST 24
Peak memory 259256 kb
Host smart-373e4144-8d96-44c1-9148-a1eea25990b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417618327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.3417618327
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1980303534
Short name T56
Test name
Test status
Simulation time 52171400 ps
CPU time 26.6 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:51:20 PM PST 24
Peak memory 259244 kb
Host smart-4a1ef6c3-f159-477c-be68-5a34b82aced0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980303534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1980303534
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2313969641
Short name T233
Test name
Test status
Simulation time 41704200 ps
CPU time 18.1 seconds
Started Jan 21 07:51:12 PM PST 24
Finished Jan 21 07:51:31 PM PST 24
Peak memory 276472 kb
Host smart-a2b7f822-217c-461b-ba2b-c8be2743fe96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313969641 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2313969641
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1450953438
Short name T225
Test name
Test status
Simulation time 20147200 ps
CPU time 16.54 seconds
Started Jan 21 07:50:57 PM PST 24
Finished Jan 21 07:51:14 PM PST 24
Peak memory 259292 kb
Host smart-5cb5bd36-357e-4753-b50d-2f586006bd21
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450953438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.1450953438
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4044373833
Short name T1133
Test name
Test status
Simulation time 37480100 ps
CPU time 13.76 seconds
Started Jan 21 07:50:52 PM PST 24
Finished Jan 21 07:51:07 PM PST 24
Peak memory 261304 kb
Host smart-76864c15-60f7-4192-9bed-68bab69f8312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044373833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.4
044373833
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3154997224
Short name T257
Test name
Test status
Simulation time 27932300 ps
CPU time 13.77 seconds
Started Jan 21 07:50:57 PM PST 24
Finished Jan 21 07:51:11 PM PST 24
Peak memory 262832 kb
Host smart-b2565a3e-9c19-404d-8994-e9fc27ff16e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154997224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.3154997224
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4187315096
Short name T254
Test name
Test status
Simulation time 17403800 ps
CPU time 13.59 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:51:08 PM PST 24
Peak memory 260472 kb
Host smart-38f9d2ef-894c-49f8-af79-2dfa60bbaa74
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187315096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.4187315096
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3362541093
Short name T1140
Test name
Test status
Simulation time 531220100 ps
CPU time 18.69 seconds
Started Jan 21 07:51:07 PM PST 24
Finished Jan 21 07:51:26 PM PST 24
Peak memory 259224 kb
Host smart-4c72c43f-206b-4575-b9e9-49bcc4f4b565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362541093 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3362541093
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1677340961
Short name T1187
Test name
Test status
Simulation time 23919200 ps
CPU time 13.72 seconds
Started Jan 21 07:50:59 PM PST 24
Finished Jan 21 07:51:14 PM PST 24
Peak memory 259252 kb
Host smart-b105a8ad-aa5d-4560-85e2-9cccd5d6ca1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677340961 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1677340961
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3381979488
Short name T1067
Test name
Test status
Simulation time 32176200 ps
CPU time 16.77 seconds
Started Jan 21 07:50:59 PM PST 24
Finished Jan 21 07:51:18 PM PST 24
Peak memory 259160 kb
Host smart-bef069c7-e410-4c1e-9623-374518b68ed0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381979488 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3381979488
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3026371696
Short name T1116
Test name
Test status
Simulation time 96845800 ps
CPU time 20.39 seconds
Started Jan 21 07:50:53 PM PST 24
Finished Jan 21 07:51:14 PM PST 24
Peak memory 263336 kb
Host smart-a2694a31-06bb-4364-b5e3-f2c257f6a256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026371696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
026371696
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3621060173
Short name T252
Test name
Test status
Simulation time 28360800 ps
CPU time 13.62 seconds
Started Jan 21 07:52:30 PM PST 24
Finished Jan 21 07:52:44 PM PST 24
Peak memory 261284 kb
Host smart-45cda414-e3af-4fab-934c-4903a0c4be75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621060173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3621060173
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2416221525
Short name T1072
Test name
Test status
Simulation time 29126600 ps
CPU time 13.26 seconds
Started Jan 21 07:52:37 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 261600 kb
Host smart-b2a9c190-05cf-4ea1-a9b2-4567ab7199a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416221525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2416221525
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2655303475
Short name T251
Test name
Test status
Simulation time 49790400 ps
CPU time 13.73 seconds
Started Jan 21 07:52:29 PM PST 24
Finished Jan 21 07:52:44 PM PST 24
Peak memory 261572 kb
Host smart-1f148546-97b7-45b5-a1d8-6b35dbb8d9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655303475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
2655303475
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1970157574
Short name T344
Test name
Test status
Simulation time 30810300 ps
CPU time 13.26 seconds
Started Jan 21 07:52:37 PM PST 24
Finished Jan 21 07:52:52 PM PST 24
Peak memory 261484 kb
Host smart-e0297102-1bfc-4592-988b-ef998d36547f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970157574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1970157574
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2102994916
Short name T1121
Test name
Test status
Simulation time 14897700 ps
CPU time 14.06 seconds
Started Jan 21 07:52:38 PM PST 24
Finished Jan 21 07:52:55 PM PST 24
Peak memory 261464 kb
Host smart-95761c25-43f1-47e3-9a99-8af1c78ef6b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102994916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2102994916
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1647001024
Short name T1066
Test name
Test status
Simulation time 16802400 ps
CPU time 13.54 seconds
Started Jan 21 07:52:34 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261400 kb
Host smart-e89a4820-5165-48f3-9f94-5e4c73a60879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647001024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1647001024
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2620762331
Short name T1188
Test name
Test status
Simulation time 29539000 ps
CPU time 13.86 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261156 kb
Host smart-4edd71af-f1e0-4dcc-84c9-732beaa73b45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620762331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2620762331
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.539804364
Short name T1141
Test name
Test status
Simulation time 16266000 ps
CPU time 13.19 seconds
Started Jan 21 07:52:36 PM PST 24
Finished Jan 21 07:52:50 PM PST 24
Peak memory 261616 kb
Host smart-0327eb82-4edc-46e4-ab51-80711e9a7b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539804364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.539804364
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1076747024
Short name T1129
Test name
Test status
Simulation time 59843300 ps
CPU time 14.44 seconds
Started Jan 21 07:52:36 PM PST 24
Finished Jan 21 07:52:52 PM PST 24
Peak memory 261352 kb
Host smart-5b48fe99-e983-409c-bed8-71b3e1296e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076747024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1076747024
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2502712085
Short name T1114
Test name
Test status
Simulation time 2544554000 ps
CPU time 66.88 seconds
Started Jan 21 07:51:06 PM PST 24
Finished Jan 21 07:52:14 PM PST 24
Peak memory 259336 kb
Host smart-868a3b1f-093f-45ad-8597-fdc4ba7ea5bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502712085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2502712085
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.454973870
Short name T300
Test name
Test status
Simulation time 1421565000 ps
CPU time 45.73 seconds
Started Jan 21 07:51:15 PM PST 24
Finished Jan 21 07:52:02 PM PST 24
Peak memory 259240 kb
Host smart-d9df0ffd-2090-428d-abb8-6909df665730
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454973870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.454973870
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.18401188
Short name T223
Test name
Test status
Simulation time 55526700 ps
CPU time 26.25 seconds
Started Jan 21 07:51:08 PM PST 24
Finished Jan 21 07:51:35 PM PST 24
Peak memory 259204 kb
Host smart-809c542f-8c95-43f3-a7f0-da36b80964d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.flash_ctrl_csr_hw_reset.18401188
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.845662115
Short name T1123
Test name
Test status
Simulation time 69775300 ps
CPU time 17.56 seconds
Started Jan 21 07:51:07 PM PST 24
Finished Jan 21 07:51:25 PM PST 24
Peak memory 269336 kb
Host smart-93ddd3a0-60bf-446f-b509-8ebb509b302c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845662115 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.845662115
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4130980994
Short name T1136
Test name
Test status
Simulation time 69946400 ps
CPU time 16.76 seconds
Started Jan 21 07:51:12 PM PST 24
Finished Jan 21 07:51:30 PM PST 24
Peak memory 259120 kb
Host smart-a3e83b36-9dc0-416c-9a8b-2987c0e0473a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130980994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.4130980994
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3983422716
Short name T1168
Test name
Test status
Simulation time 18486600 ps
CPU time 13.52 seconds
Started Jan 21 07:51:05 PM PST 24
Finished Jan 21 07:51:20 PM PST 24
Peak memory 261320 kb
Host smart-a5c6579d-77c7-447f-a484-4a3a012eb161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983422716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
983422716
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2032390681
Short name T260
Test name
Test status
Simulation time 28269500 ps
CPU time 13.72 seconds
Started Jan 21 07:51:05 PM PST 24
Finished Jan 21 07:51:20 PM PST 24
Peak memory 262908 kb
Host smart-dc988d09-d001-4410-84df-50b909d65b16
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032390681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.2032390681
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3929044361
Short name T1083
Test name
Test status
Simulation time 28756100 ps
CPU time 13.56 seconds
Started Jan 21 07:51:20 PM PST 24
Finished Jan 21 07:51:35 PM PST 24
Peak memory 261400 kb
Host smart-edf59980-7844-4c36-a320-d939ffe406d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929044361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.3929044361
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.290376681
Short name T302
Test name
Test status
Simulation time 414534500 ps
CPU time 18.79 seconds
Started Jan 21 07:51:06 PM PST 24
Finished Jan 21 07:51:26 PM PST 24
Peak memory 259148 kb
Host smart-d2a757a9-68db-4bc8-9155-4246e78f87f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290376681 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.290376681
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2256000431
Short name T1065
Test name
Test status
Simulation time 14483200 ps
CPU time 13.1 seconds
Started Jan 21 07:51:03 PM PST 24
Finished Jan 21 07:51:18 PM PST 24
Peak memory 259284 kb
Host smart-54e0095e-ecdd-4667-a2be-ec5fbdaae80c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256000431 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2256000431
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.433390855
Short name T1086
Test name
Test status
Simulation time 52115000 ps
CPU time 13.63 seconds
Started Jan 21 07:51:19 PM PST 24
Finished Jan 21 07:51:34 PM PST 24
Peak memory 259164 kb
Host smart-9b21050e-48eb-4a00-aa45-a06313f8cfce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433390855 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.433390855
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3890691721
Short name T269
Test name
Test status
Simulation time 346183800 ps
CPU time 19.37 seconds
Started Jan 21 07:51:13 PM PST 24
Finished Jan 21 07:51:34 PM PST 24
Peak memory 263276 kb
Host smart-3a26c0ed-dffb-43bc-8f8e-030c6b0b5ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890691721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3
890691721
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1551628203
Short name T347
Test name
Test status
Simulation time 353658000 ps
CPU time 903.69 seconds
Started Jan 21 07:51:12 PM PST 24
Finished Jan 21 08:06:17 PM PST 24
Peak memory 263412 kb
Host smart-8c37854a-cab6-4d39-9f86-a4576625b6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551628203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1551628203
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2867096125
Short name T248
Test name
Test status
Simulation time 15498500 ps
CPU time 13.55 seconds
Started Jan 21 07:52:34 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261588 kb
Host smart-de044418-9a46-4517-a8ad-d97af7bda7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867096125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
2867096125
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1733376410
Short name T240
Test name
Test status
Simulation time 31120600 ps
CPU time 14.58 seconds
Started Jan 21 07:52:37 PM PST 24
Finished Jan 21 07:52:54 PM PST 24
Peak memory 261320 kb
Host smart-0703c807-6511-49d7-bc42-1865963ffcb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733376410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1733376410
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.277709501
Short name T1105
Test name
Test status
Simulation time 37908100 ps
CPU time 13.42 seconds
Started Jan 21 07:52:36 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 261372 kb
Host smart-9221d051-cf64-4661-820b-ac39a63540b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277709501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.277709501
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2548409340
Short name T313
Test name
Test status
Simulation time 17844900 ps
CPU time 14.49 seconds
Started Jan 21 07:52:37 PM PST 24
Finished Jan 21 07:52:54 PM PST 24
Peak memory 261456 kb
Host smart-914a81bf-b90d-4b0a-b20b-3349fbcc4ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548409340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
2548409340
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.954251052
Short name T1184
Test name
Test status
Simulation time 28875200 ps
CPU time 13.54 seconds
Started Jan 21 07:52:36 PM PST 24
Finished Jan 21 07:52:51 PM PST 24
Peak memory 261468 kb
Host smart-00e5759d-34cc-4180-9103-9c0ff7500620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954251052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.954251052
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.238467862
Short name T1097
Test name
Test status
Simulation time 33233400 ps
CPU time 13.79 seconds
Started Jan 21 07:52:34 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261560 kb
Host smart-611635e8-64bf-43a6-a9fd-5a97dbeba92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238467862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.238467862
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3630513579
Short name T341
Test name
Test status
Simulation time 18478400 ps
CPU time 13.7 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261412 kb
Host smart-612149b4-f8db-4b3b-9129-09e90e153aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630513579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3630513579
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1047534641
Short name T1106
Test name
Test status
Simulation time 23715800 ps
CPU time 13.72 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:48 PM PST 24
Peak memory 261512 kb
Host smart-51abc4bc-45af-4ae1-8f5a-05ba77620a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047534641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1047534641
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.861129837
Short name T1070
Test name
Test status
Simulation time 46988800 ps
CPU time 13.37 seconds
Started Jan 21 07:52:33 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261048 kb
Host smart-7e1cdd7b-8b3d-452d-8667-6e0ac93ea8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861129837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.861129837
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2845157903
Short name T1170
Test name
Test status
Simulation time 52352100 ps
CPU time 13.53 seconds
Started Jan 21 07:52:34 PM PST 24
Finished Jan 21 07:52:49 PM PST 24
Peak memory 261588 kb
Host smart-e72823e9-fdb7-434a-aa72-f53c1b6384e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845157903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2845157903
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1214540853
Short name T1079
Test name
Test status
Simulation time 826178600 ps
CPU time 34.64 seconds
Started Jan 21 07:51:14 PM PST 24
Finished Jan 21 07:51:50 PM PST 24
Peak memory 259280 kb
Host smart-3f5afcd0-abba-4e2c-a0c6-c6b5627dadaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214540853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1214540853
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3914312726
Short name T1099
Test name
Test status
Simulation time 4773294800 ps
CPU time 79.24 seconds
Started Jan 21 07:51:13 PM PST 24
Finished Jan 21 07:52:33 PM PST 24
Peak memory 259200 kb
Host smart-cd657e0c-9822-4fdd-8826-22bc53af8f19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914312726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3914312726
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1020791579
Short name T1152
Test name
Test status
Simulation time 100665900 ps
CPU time 45.8 seconds
Started Jan 21 07:51:14 PM PST 24
Finished Jan 21 07:52:01 PM PST 24
Peak memory 259172 kb
Host smart-4d95092f-e5de-4eb2-a52d-58da852ac31b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020791579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1020791579
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1017015463
Short name T1154
Test name
Test status
Simulation time 155557000 ps
CPU time 15.38 seconds
Started Jan 21 07:51:17 PM PST 24
Finished Jan 21 07:51:34 PM PST 24
Peak memory 271416 kb
Host smart-0826f8e3-8754-4e5d-87e5-0de9908409ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017015463 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1017015463
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2254320267
Short name T1101
Test name
Test status
Simulation time 63689900 ps
CPU time 14.54 seconds
Started Jan 21 07:51:26 PM PST 24
Finished Jan 21 07:51:42 PM PST 24
Peak memory 259260 kb
Host smart-65ba2051-7078-4e63-9117-8c2fad95ac5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254320267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2254320267
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.26994743
Short name T1098
Test name
Test status
Simulation time 30925500 ps
CPU time 13.75 seconds
Started Jan 21 07:51:25 PM PST 24
Finished Jan 21 07:51:40 PM PST 24
Peak memory 261272 kb
Host smart-1adee2da-01be-4185-a8c9-84ee93391ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26994743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.26994743
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2449319547
Short name T258
Test name
Test status
Simulation time 58025600 ps
CPU time 13.51 seconds
Started Jan 21 07:51:12 PM PST 24
Finished Jan 21 07:51:27 PM PST 24
Peak memory 262400 kb
Host smart-1778b0cd-ab42-4fdc-9efc-e5a69071473b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449319547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.2449319547
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.273298646
Short name T1102
Test name
Test status
Simulation time 15183500 ps
CPU time 13.46 seconds
Started Jan 21 07:51:17 PM PST 24
Finished Jan 21 07:51:32 PM PST 24
Peak memory 260568 kb
Host smart-407cc2eb-6373-4553-a6c1-f888e2f15b77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273298646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.273298646
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4195291651
Short name T316
Test name
Test status
Simulation time 366848400 ps
CPU time 18.55 seconds
Started Jan 21 07:51:16 PM PST 24
Finished Jan 21 07:51:36 PM PST 24
Peak memory 259260 kb
Host smart-9ad51faf-ae36-4be2-a28e-ee17ba4a0987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195291651 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.4195291651
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2542705937
Short name T1185
Test name
Test status
Simulation time 14541900 ps
CPU time 13.41 seconds
Started Jan 21 07:51:17 PM PST 24
Finished Jan 21 07:51:31 PM PST 24
Peak memory 259272 kb
Host smart-b3fa3cba-315f-43df-a341-c4bf044ff177
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542705937 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2542705937
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1168829919
Short name T1077
Test name
Test status
Simulation time 28485500 ps
CPU time 15.85 seconds
Started Jan 21 07:51:15 PM PST 24
Finished Jan 21 07:51:32 PM PST 24
Peak memory 259124 kb
Host smart-1372c018-b6bf-4b77-9cb0-2960d0af44a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168829919 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1168829919
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3854260963
Short name T1132
Test name
Test status
Simulation time 112890600 ps
CPU time 19.27 seconds
Started Jan 21 07:51:20 PM PST 24
Finished Jan 21 07:51:40 PM PST 24
Peak memory 263268 kb
Host smart-9657890a-0f92-4d90-8bab-7b57a706316b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854260963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3
854260963
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3170937143
Short name T231
Test name
Test status
Simulation time 907973200 ps
CPU time 467.27 seconds
Started Jan 21 07:51:14 PM PST 24
Finished Jan 21 07:59:03 PM PST 24
Peak memory 259320 kb
Host smart-3b39849d-efaa-4af3-8d9c-3a976f1e4c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170937143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.3170937143
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3680105481
Short name T1186
Test name
Test status
Simulation time 24518000 ps
CPU time 14.01 seconds
Started Jan 21 07:52:40 PM PST 24
Finished Jan 21 07:52:56 PM PST 24
Peak memory 261372 kb
Host smart-603205ce-aa30-4e67-844a-8a5503c7ab62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680105481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
3680105481
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3750132109
Short name T1069
Test name
Test status
Simulation time 27554100 ps
CPU time 13.57 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:53:05 PM PST 24
Peak memory 260376 kb
Host smart-2f270edb-c162-45d4-a487-57d879cca426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750132109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3750132109
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.958081719
Short name T1093
Test name
Test status
Simulation time 69395300 ps
CPU time 13.59 seconds
Started Jan 21 07:52:51 PM PST 24
Finished Jan 21 07:53:06 PM PST 24
Peak memory 261484 kb
Host smart-802ec152-d47c-4f1f-addc-260f577fbeec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958081719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.958081719
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4107410608
Short name T1127
Test name
Test status
Simulation time 55021000 ps
CPU time 13.54 seconds
Started Jan 21 07:52:49 PM PST 24
Finished Jan 21 07:53:04 PM PST 24
Peak memory 261324 kb
Host smart-7c733cb9-c775-409c-aaf3-6f4064ca85cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107410608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
4107410608
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2249102775
Short name T1171
Test name
Test status
Simulation time 79311900 ps
CPU time 13.37 seconds
Started Jan 21 07:52:48 PM PST 24
Finished Jan 21 07:53:02 PM PST 24
Peak memory 261288 kb
Host smart-ce324a32-4e52-44e0-8ff9-f41a467db01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249102775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2249102775
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.587980003
Short name T1119
Test name
Test status
Simulation time 27460500 ps
CPU time 13.48 seconds
Started Jan 21 07:52:49 PM PST 24
Finished Jan 21 07:53:04 PM PST 24
Peak memory 261448 kb
Host smart-6dcc88be-0975-40b6-b66c-9ec476a9de93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587980003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.587980003
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2507393949
Short name T342
Test name
Test status
Simulation time 17516500 ps
CPU time 13.49 seconds
Started Jan 21 07:52:53 PM PST 24
Finished Jan 21 07:53:08 PM PST 24
Peak memory 261436 kb
Host smart-910b2c5d-fb1a-45d7-adf6-f6099bb890b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507393949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2507393949
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.954301940
Short name T1104
Test name
Test status
Simulation time 58363600 ps
CPU time 13.62 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:53:05 PM PST 24
Peak memory 261372 kb
Host smart-ecc559c3-7df9-4936-9ead-dabad70754ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954301940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.954301940
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2132025434
Short name T1073
Test name
Test status
Simulation time 42515300 ps
CPU time 14.23 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:53:07 PM PST 24
Peak memory 261596 kb
Host smart-787ca8f7-c780-4206-980d-69667af42341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132025434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2132025434
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1419600001
Short name T1085
Test name
Test status
Simulation time 18697600 ps
CPU time 13.6 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:53:06 PM PST 24
Peak memory 261304 kb
Host smart-6b30a622-ccbc-4a10-9708-45f36ef13eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419600001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
1419600001
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2377620561
Short name T317
Test name
Test status
Simulation time 85930600 ps
CPU time 17.77 seconds
Started Jan 21 07:51:24 PM PST 24
Finished Jan 21 07:51:42 PM PST 24
Peak memory 269444 kb
Host smart-6911e32e-1a16-46fd-b62b-abddccaf0398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377620561 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2377620561
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.544054759
Short name T1190
Test name
Test status
Simulation time 21626800 ps
CPU time 16.52 seconds
Started Jan 21 07:51:29 PM PST 24
Finished Jan 21 07:51:47 PM PST 24
Peak memory 259316 kb
Host smart-ceb6c538-e8ea-4a76-a679-cd121fbeaa14
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544054759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.544054759
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.411819975
Short name T1174
Test name
Test status
Simulation time 17751900 ps
CPU time 13.5 seconds
Started Jan 21 07:51:19 PM PST 24
Finished Jan 21 07:51:34 PM PST 24
Peak memory 261508 kb
Host smart-df027fec-a9fb-4a97-b44c-a7d2da6711df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411819975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.411819975
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4244715005
Short name T1160
Test name
Test status
Simulation time 986868300 ps
CPU time 35.72 seconds
Started Jan 21 07:51:25 PM PST 24
Finished Jan 21 07:52:02 PM PST 24
Peak memory 259264 kb
Host smart-7ffd4228-f22c-4f1b-bc26-a9acd906764e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244715005 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.4244715005
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3168228044
Short name T1124
Test name
Test status
Simulation time 24024200 ps
CPU time 15.84 seconds
Started Jan 21 07:51:27 PM PST 24
Finished Jan 21 07:51:44 PM PST 24
Peak memory 259124 kb
Host smart-ee2de3c4-9224-4f2c-9447-82e6168effd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168228044 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3168228044
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.297942443
Short name T1189
Test name
Test status
Simulation time 15127800 ps
CPU time 13.07 seconds
Started Jan 21 07:51:28 PM PST 24
Finished Jan 21 07:51:42 PM PST 24
Peak memory 259280 kb
Host smart-6f5414bd-253e-405d-b60b-8c31ebb2cd43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297942443 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.297942443
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.525145713
Short name T1165
Test name
Test status
Simulation time 263504900 ps
CPU time 18.87 seconds
Started Jan 21 07:51:29 PM PST 24
Finished Jan 21 07:51:50 PM PST 24
Peak memory 263208 kb
Host smart-bc676936-5cb7-44d6-95a8-882588c054b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525145713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.525145713
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1623293048
Short name T247
Test name
Test status
Simulation time 685271600 ps
CPU time 465.33 seconds
Started Jan 21 07:51:19 PM PST 24
Finished Jan 21 07:59:05 PM PST 24
Peak memory 263368 kb
Host smart-b2cbb2d1-4199-41f4-837b-476b9a9a1eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623293048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.1623293048
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2307366174
Short name T1156
Test name
Test status
Simulation time 34571900 ps
CPU time 15.24 seconds
Started Jan 21 07:51:27 PM PST 24
Finished Jan 21 07:51:44 PM PST 24
Peak memory 269340 kb
Host smart-0f538521-2b0d-470f-99e4-9178e0680d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307366174 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2307366174
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.866549428
Short name T1081
Test name
Test status
Simulation time 49695000 ps
CPU time 17.12 seconds
Started Jan 21 07:51:25 PM PST 24
Finished Jan 21 07:51:43 PM PST 24
Peak memory 259256 kb
Host smart-cbf0b61e-c05b-4d7a-be14-2c8f9c7e8dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866549428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_csr_rw.866549428
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.828029818
Short name T1180
Test name
Test status
Simulation time 45068000 ps
CPU time 13.61 seconds
Started Jan 21 07:51:20 PM PST 24
Finished Jan 21 07:51:35 PM PST 24
Peak memory 261528 kb
Host smart-37fe6795-d749-4ed8-9584-6fd00a010c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828029818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.828029818
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3267357692
Short name T1103
Test name
Test status
Simulation time 828087400 ps
CPU time 18.67 seconds
Started Jan 21 07:51:30 PM PST 24
Finished Jan 21 07:51:50 PM PST 24
Peak memory 260992 kb
Host smart-ecd94e4c-6131-49ee-97b5-1f2f79a04b24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267357692 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3267357692
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.229226714
Short name T256
Test name
Test status
Simulation time 23841900 ps
CPU time 13.32 seconds
Started Jan 21 07:51:28 PM PST 24
Finished Jan 21 07:51:43 PM PST 24
Peak memory 259176 kb
Host smart-0720a8d3-e73b-47ef-b5a2-c3d960529bdc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229226714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.229226714
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.968805894
Short name T1080
Test name
Test status
Simulation time 21608100 ps
CPU time 16.15 seconds
Started Jan 21 07:51:28 PM PST 24
Finished Jan 21 07:51:45 PM PST 24
Peak memory 259244 kb
Host smart-3a4803f5-fc33-46e8-96f9-8ba4ddd2bebd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968805894 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.968805894
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2547218681
Short name T1149
Test name
Test status
Simulation time 287517000 ps
CPU time 18.1 seconds
Started Jan 21 07:51:25 PM PST 24
Finished Jan 21 07:51:44 PM PST 24
Peak memory 263352 kb
Host smart-f72c8b20-8970-428f-9423-5b5c3fefb13e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547218681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
547218681
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2123727966
Short name T245
Test name
Test status
Simulation time 207125300 ps
CPU time 388.95 seconds
Started Jan 21 07:51:24 PM PST 24
Finished Jan 21 07:57:54 PM PST 24
Peak memory 260472 kb
Host smart-b43c02c8-3b57-473a-85db-e236882fc131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123727966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.2123727966
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3308011567
Short name T335
Test name
Test status
Simulation time 27245100 ps
CPU time 17.14 seconds
Started Jan 21 07:51:31 PM PST 24
Finished Jan 21 07:51:50 PM PST 24
Peak memory 263304 kb
Host smart-503d4a7a-cba1-4f0f-97a1-0b4cc06881f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308011567 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3308011567
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2228839134
Short name T1120
Test name
Test status
Simulation time 58356700 ps
CPU time 17.4 seconds
Started Jan 21 07:51:27 PM PST 24
Finished Jan 21 07:51:45 PM PST 24
Peak memory 259364 kb
Host smart-e81eeaac-08c5-4702-98d5-7251614f659b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228839134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2228839134
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4169522502
Short name T1130
Test name
Test status
Simulation time 26527200 ps
CPU time 13.24 seconds
Started Jan 21 07:51:29 PM PST 24
Finished Jan 21 07:51:43 PM PST 24
Peak memory 261448 kb
Host smart-76f495f2-9264-4e60-a355-a1a2d2bf4ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169522502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.4
169522502
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3489853836
Short name T305
Test name
Test status
Simulation time 105777000 ps
CPU time 16.08 seconds
Started Jan 21 07:51:27 PM PST 24
Finished Jan 21 07:51:44 PM PST 24
Peak memory 261412 kb
Host smart-b2381753-d83a-4a72-807f-00de5346f7a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489853836 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3489853836
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2883065482
Short name T311
Test name
Test status
Simulation time 24047400 ps
CPU time 13.29 seconds
Started Jan 21 07:51:29 PM PST 24
Finished Jan 21 07:51:44 PM PST 24
Peak memory 259136 kb
Host smart-abd9d5e2-7eaf-495d-b6d6-24012cbae7f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883065482 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2883065482
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4143745638
Short name T1126
Test name
Test status
Simulation time 34125200 ps
CPU time 15.49 seconds
Started Jan 21 07:51:28 PM PST 24
Finished Jan 21 07:51:45 PM PST 24
Peak memory 259228 kb
Host smart-b12feca1-c15b-44be-9c23-749322bddf6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143745638 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.4143745638
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2870389960
Short name T1150
Test name
Test status
Simulation time 53562600 ps
CPU time 16.41 seconds
Started Jan 21 07:51:31 PM PST 24
Finished Jan 21 07:51:49 PM PST 24
Peak memory 263540 kb
Host smart-6b3dd8fb-029c-4c44-8b4b-aa3683e9c861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870389960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
870389960
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.171314866
Short name T1167
Test name
Test status
Simulation time 105650900 ps
CPU time 16.23 seconds
Started Jan 21 07:51:46 PM PST 24
Finished Jan 21 07:52:03 PM PST 24
Peak memory 263304 kb
Host smart-0dd1afc0-b1c8-4945-bd5e-72c8e274d1a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171314866 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.171314866
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3659629433
Short name T309
Test name
Test status
Simulation time 351248900 ps
CPU time 16.72 seconds
Started Jan 21 07:51:39 PM PST 24
Finished Jan 21 07:51:58 PM PST 24
Peak memory 259464 kb
Host smart-6414ad40-8e66-44bc-badf-8ea27de6ad8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659629433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3659629433
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1547775520
Short name T272
Test name
Test status
Simulation time 31100100 ps
CPU time 13.48 seconds
Started Jan 21 07:51:44 PM PST 24
Finished Jan 21 07:51:59 PM PST 24
Peak memory 261412 kb
Host smart-24aaa3e6-3e26-4587-a369-050e4dad6e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547775520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1
547775520
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3544769414
Short name T1182
Test name
Test status
Simulation time 759882000 ps
CPU time 16.42 seconds
Started Jan 21 07:51:44 PM PST 24
Finished Jan 21 07:52:01 PM PST 24
Peak memory 259288 kb
Host smart-e46f64ee-a074-4202-9c1c-87d9b3108261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544769414 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3544769414
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2048288226
Short name T1139
Test name
Test status
Simulation time 18692600 ps
CPU time 15.43 seconds
Started Jan 21 07:51:39 PM PST 24
Finished Jan 21 07:51:56 PM PST 24
Peak memory 259064 kb
Host smart-47bf8351-3e0a-4b60-a8c7-3aac08d2100e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048288226 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2048288226
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.109084758
Short name T1062
Test name
Test status
Simulation time 14931400 ps
CPU time 16.47 seconds
Started Jan 21 07:51:40 PM PST 24
Finished Jan 21 07:51:59 PM PST 24
Peak memory 259124 kb
Host smart-115c38a2-b3f0-4227-8bb7-4bd75647cdaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109084758 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.109084758
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3658857232
Short name T351
Test name
Test status
Simulation time 355536500 ps
CPU time 391.49 seconds
Started Jan 21 07:51:41 PM PST 24
Finished Jan 21 07:58:14 PM PST 24
Peak memory 263412 kb
Host smart-39609f6a-2591-496b-92fe-ed70739b7971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658857232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.3658857232
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1945715743
Short name T220
Test name
Test status
Simulation time 38769900 ps
CPU time 15.76 seconds
Started Jan 21 07:51:45 PM PST 24
Finished Jan 21 07:52:02 PM PST 24
Peak memory 270340 kb
Host smart-02dc2099-d4f6-4359-904c-455822636754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945715743 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1945715743
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1630874517
Short name T1071
Test name
Test status
Simulation time 65605000 ps
CPU time 17.81 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:13 PM PST 24
Peak memory 259128 kb
Host smart-ce3640cb-e7ce-4472-aa20-059ade003df4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630874517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1630874517
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2918668818
Short name T241
Test name
Test status
Simulation time 17766200 ps
CPU time 13.43 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:08 PM PST 24
Peak memory 261544 kb
Host smart-601635cb-8933-477e-97cb-0c9a79a10cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918668818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
918668818
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3936534872
Short name T1108
Test name
Test status
Simulation time 69775600 ps
CPU time 17.74 seconds
Started Jan 21 07:51:54 PM PST 24
Finished Jan 21 07:52:13 PM PST 24
Peak memory 262856 kb
Host smart-32432543-cbbd-46a6-aea2-fdc06069de72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936534872 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3936534872
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1739888574
Short name T1163
Test name
Test status
Simulation time 25870200 ps
CPU time 13.18 seconds
Started Jan 21 08:30:39 PM PST 24
Finished Jan 21 08:30:57 PM PST 24
Peak memory 259264 kb
Host smart-057ced3d-bbe6-43a5-9c81-ab48e018dfef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739888574 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1739888574
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2276858262
Short name T1078
Test name
Test status
Simulation time 39808800 ps
CPU time 15.96 seconds
Started Jan 21 07:51:47 PM PST 24
Finished Jan 21 07:52:04 PM PST 24
Peak memory 259268 kb
Host smart-5dba2175-eb05-4fc0-8662-3187e85221ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276858262 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2276858262
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3512988434
Short name T1138
Test name
Test status
Simulation time 102793000 ps
CPU time 20.19 seconds
Started Jan 21 07:51:44 PM PST 24
Finished Jan 21 07:52:05 PM PST 24
Peak memory 263336 kb
Host smart-5b9ace65-1d3c-45ba-89fa-83d99b472a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512988434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3
512988434
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1335103339
Short name T221
Test name
Test status
Simulation time 1313543800 ps
CPU time 394.03 seconds
Started Jan 21 07:51:46 PM PST 24
Finished Jan 21 07:58:21 PM PST 24
Peak memory 263416 kb
Host smart-8cdc487f-311f-4498-95b1-9e50de5011b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335103339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1335103339
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.1941562313
Short name T494
Test name
Test status
Simulation time 42663100 ps
CPU time 14.05 seconds
Started Jan 21 03:33:53 PM PST 24
Finished Jan 21 03:34:14 PM PST 24
Peak memory 264404 kb
Host smart-3a8ae42d-67c9-4687-ba65-16b2d94b9dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941562313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1
941562313
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.1979984779
Short name T268
Test name
Test status
Simulation time 44286800 ps
CPU time 13.76 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:34:25 PM PST 24
Peak memory 262988 kb
Host smart-c47d493c-6c07-44aa-aaf8-51662b0948cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979984779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.1979984779
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2282618574
Short name T627
Test name
Test status
Simulation time 14602100 ps
CPU time 15.67 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:33:59 PM PST 24
Peak memory 273676 kb
Host smart-e956ae99-fb06-4ad8-9d2d-cb92a4288c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282618574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2282618574
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.938338991
Short name T1054
Test name
Test status
Simulation time 443299900 ps
CPU time 103.07 seconds
Started Jan 21 03:33:46 PM PST 24
Finished Jan 21 03:35:36 PM PST 24
Peak memory 270592 kb
Host smart-a8bba397-3073-42ed-a99c-fa52c61d2c6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938338991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_derr_detect.938338991
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3804051154
Short name T1013
Test name
Test status
Simulation time 18642885900 ps
CPU time 566.08 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:42:59 PM PST 24
Peak memory 261368 kb
Host smart-765d6da3-0bb8-4e0b-a0e3-e801c1625c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804051154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3804051154
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.860639114
Short name T706
Test name
Test status
Simulation time 1852571900 ps
CPU time 2444.25 seconds
Started Jan 21 03:33:32 PM PST 24
Finished Jan 21 04:14:18 PM PST 24
Peak memory 263732 kb
Host smart-34af1627-6f26-49d4-bada-6f0c0915427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860639114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.860639114
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.4110611662
Short name T875
Test name
Test status
Simulation time 508433200 ps
CPU time 29.94 seconds
Started Jan 21 04:53:48 PM PST 24
Finished Jan 21 04:54:18 PM PST 24
Peak memory 264268 kb
Host smart-b81a1cc7-9576-4b58-9102-055d05a72d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110611662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.4110611662
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.4156294500
Short name T169
Test name
Test status
Simulation time 283691700 ps
CPU time 34.5 seconds
Started Jan 21 03:33:54 PM PST 24
Finished Jan 21 03:34:35 PM PST 24
Peak memory 264332 kb
Host smart-e258a261-49d7-4e4b-a941-505d3ec4b18c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156294500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.4156294500
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.2130156884
Short name T137
Test name
Test status
Simulation time 81092540000 ps
CPU time 2596.37 seconds
Started Jan 21 03:33:28 PM PST 24
Finished Jan 21 04:16:47 PM PST 24
Peak memory 260032 kb
Host smart-1335983e-c1c2-4b91-8860-8f54ffe63d8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130156884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.2130156884
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.993251160
Short name T92
Test name
Test status
Simulation time 10042600200 ps
CPU time 46.08 seconds
Started Jan 21 03:33:55 PM PST 24
Finished Jan 21 03:34:48 PM PST 24
Peak memory 273292 kb
Host smart-a336f6b6-f1a4-4ae7-8883-1232ef82fb85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993251160 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.993251160
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.381360373
Short name T984
Test name
Test status
Simulation time 24451200 ps
CPU time 13.59 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:34:25 PM PST 24
Peak memory 262984 kb
Host smart-04d03723-8300-4e27-8aac-bd71df6256d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381360373 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.381360373
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3916982048
Short name T80
Test name
Test status
Simulation time 169017395700 ps
CPU time 1652.08 seconds
Started Jan 21 03:33:37 PM PST 24
Finished Jan 21 04:01:11 PM PST 24
Peak memory 262172 kb
Host smart-e17f1395-4334-4a64-88e5-315599c0fa68
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916982048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3916982048
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1417124056
Short name T624
Test name
Test status
Simulation time 40131515500 ps
CPU time 771.77 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:46:35 PM PST 24
Peak memory 262732 kb
Host smart-3a69e39d-a1f0-4e02-af78-b4b7f1faa71c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417124056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1417124056
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2103570637
Short name T656
Test name
Test status
Simulation time 1063970600 ps
CPU time 34.92 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:34:07 PM PST 24
Peak memory 261084 kb
Host smart-a2c77f0c-dfac-47d7-8030-6c9376310dc3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103570637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2103570637
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.726122550
Short name T68
Test name
Test status
Simulation time 7450201000 ps
CPU time 617.65 seconds
Started Jan 21 03:33:43 PM PST 24
Finished Jan 21 03:44:10 PM PST 24
Peak memory 319324 kb
Host smart-fd91c0ff-b224-4f49-a4d2-5b0c45d8870c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726122550 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_integrity.726122550
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.129930148
Short name T760
Test name
Test status
Simulation time 1385162700 ps
CPU time 171.38 seconds
Started Jan 21 03:33:42 PM PST 24
Finished Jan 21 03:36:40 PM PST 24
Peak memory 293292 kb
Host smart-f5777f58-439e-4f9a-a92d-16356ff8462e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129930148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.129930148
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.378740980
Short name T853
Test name
Test status
Simulation time 8636932700 ps
CPU time 219.18 seconds
Started Jan 21 03:33:48 PM PST 24
Finished Jan 21 03:37:32 PM PST 24
Peak memory 292224 kb
Host smart-745e28a9-fe45-4a22-bedc-073d0d192996
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378740980 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.378740980
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2432656696
Short name T404
Test name
Test status
Simulation time 4924972400 ps
CPU time 124.49 seconds
Started Jan 21 03:33:45 PM PST 24
Finished Jan 21 03:35:58 PM PST 24
Peak memory 264548 kb
Host smart-29c63f9e-5fb4-4fc1-815f-79fdee99cb9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432656696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2432656696
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.676411379
Short name T59
Test name
Test status
Simulation time 47487664200 ps
CPU time 407.93 seconds
Started Jan 21 03:33:52 PM PST 24
Finished Jan 21 03:40:45 PM PST 24
Peak memory 264200 kb
Host smart-2af673fe-e0e2-437c-8109-82880d147c55
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676
411379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.676411379
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.3960270801
Short name T683
Test name
Test status
Simulation time 3315495300 ps
CPU time 59.74 seconds
Started Jan 21 03:33:37 PM PST 24
Finished Jan 21 03:34:38 PM PST 24
Peak memory 258284 kb
Host smart-6020db3c-e053-489d-8517-9e26c74cb32c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960270801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3960270801
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3041919356
Short name T1008
Test name
Test status
Simulation time 1143186900 ps
CPU time 152.23 seconds
Started Jan 21 03:33:42 PM PST 24
Finished Jan 21 03:36:20 PM PST 24
Peak memory 293852 kb
Host smart-272733de-d861-46a2-8bea-71a8b28d3236
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041919356 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3041919356
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.1324324776
Short name T759
Test name
Test status
Simulation time 540789000 ps
CPU time 283.1 seconds
Started Jan 21 03:33:37 PM PST 24
Finished Jan 21 03:38:21 PM PST 24
Peak memory 261044 kb
Host smart-35433d3f-ec82-4342-8f73-81919d86e3af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324324776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1324324776
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.507174806
Short name T1042
Test name
Test status
Simulation time 60339100 ps
CPU time 13.51 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:33:57 PM PST 24
Peak memory 264280 kb
Host smart-708d847b-db37-46d9-bfc6-30f59b5352be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507174806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_rese
t.507174806
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2482954370
Short name T712
Test name
Test status
Simulation time 199760000 ps
CPU time 777.23 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:46:41 PM PST 24
Peak memory 280796 kb
Host smart-4661d7b8-daee-4256-9665-60b7ee8caa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482954370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2482954370
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.998445256
Short name T567
Test name
Test status
Simulation time 1456195700 ps
CPU time 118.51 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:35:32 PM PST 24
Peak memory 264156 kb
Host smart-df15c3e3-6653-43b6-bf03-d19d6210bde5
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=998445256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.998445256
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.683396972
Short name T1033
Test name
Test status
Simulation time 135077400 ps
CPU time 31.52 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:34:15 PM PST 24
Peak memory 272564 kb
Host smart-26d44ba7-b543-4277-80b0-97d63bb7d932
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683396972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rd_intg.683396972
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.4039831334
Short name T473
Test name
Test status
Simulation time 81188100 ps
CPU time 45.06 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:34:56 PM PST 24
Peak memory 271008 kb
Host smart-ab10a511-4f4e-44b3-b17f-9ca76cc08629
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039831334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.4039831334
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.778024504
Short name T745
Test name
Test status
Simulation time 15567000 ps
CPU time 13.29 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:33:56 PM PST 24
Peak memory 264308 kb
Host smart-0b43f684-5999-4a55-821a-11b143141460
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=778024504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.
778024504
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3313444003
Short name T524
Test name
Test status
Simulation time 52519300 ps
CPU time 23.01 seconds
Started Jan 21 03:33:48 PM PST 24
Finished Jan 21 03:34:16 PM PST 24
Peak memory 264476 kb
Host smart-e4c06665-b4b8-4cff-81a1-1d4d02a7a3dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313444003 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3313444003
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3356478897
Short name T419
Test name
Test status
Simulation time 24315700 ps
CPU time 23.73 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:33:57 PM PST 24
Peak memory 264316 kb
Host smart-8c04ff82-a918-45f1-b75b-8d39eb0f8c9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356478897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3356478897
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2187132737
Short name T98
Test name
Test status
Simulation time 55321339100 ps
CPU time 861.89 seconds
Started Jan 21 03:34:01 PM PST 24
Finished Jan 21 03:48:32 PM PST 24
Peak memory 259568 kb
Host smart-d92e45cd-e023-4881-9467-5521c345efcc
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187132737 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2187132737
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.1075558766
Short name T1020
Test name
Test status
Simulation time 505493900 ps
CPU time 94.76 seconds
Started Jan 21 03:33:39 PM PST 24
Finished Jan 21 03:35:17 PM PST 24
Peak memory 280628 kb
Host smart-9d5d8bdc-0fe2-4dfb-a212-24a89faf112d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075558766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_ro.1075558766
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.1218503822
Short name T47
Test name
Test status
Simulation time 2412715600 ps
CPU time 140.92 seconds
Started Jan 21 03:33:46 PM PST 24
Finished Jan 21 03:36:14 PM PST 24
Peak memory 280992 kb
Host smart-01fa0ef1-99f5-4bf5-897a-d076c7c7c809
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1218503822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1218503822
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.1222699137
Short name T687
Test name
Test status
Simulation time 687212200 ps
CPU time 143.6 seconds
Started Jan 21 03:33:45 PM PST 24
Finished Jan 21 03:36:17 PM PST 24
Peak memory 280820 kb
Host smart-521999e8-86d6-433c-afe9-af0735d013ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222699137 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.1222699137
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.387596227
Short name T206
Test name
Test status
Simulation time 33278970600 ps
CPU time 479.56 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:41:43 PM PST 24
Peak memory 313420 kb
Host smart-f4c95b91-ead8-4a13-859b-a1815e2bb5a9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387596227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctr
l_rw.387596227
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.1896431908
Short name T191
Test name
Test status
Simulation time 4500939800 ps
CPU time 621.29 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:44:04 PM PST 24
Peak memory 337496 kb
Host smart-b15be47f-0b3c-49db-8fcb-08858cd9ea9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896431908 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.1896431908
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.4135258667
Short name T847
Test name
Test status
Simulation time 70465700 ps
CPU time 31.75 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:34:15 PM PST 24
Peak memory 274912 kb
Host smart-ccfc77f6-57e5-48a6-b8a0-e501c9405d78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135258667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.4135258667
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.873027919
Short name T48
Test name
Test status
Simulation time 30977000 ps
CPU time 32.01 seconds
Started Jan 21 03:33:52 PM PST 24
Finished Jan 21 03:34:29 PM PST 24
Peak memory 270964 kb
Host smart-afb8cd2f-bad1-4575-8f10-462093477e0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873027919 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.873027919
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.1542564023
Short name T993
Test name
Test status
Simulation time 13239770000 ps
CPU time 551.85 seconds
Started Jan 21 03:33:44 PM PST 24
Finished Jan 21 03:43:05 PM PST 24
Peak memory 318352 kb
Host smart-ea6bce3d-eff4-4527-a57d-5eb076672292
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542564023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.1542564023
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2072022037
Short name T842
Test name
Test status
Simulation time 3093406600 ps
CPU time 75.73 seconds
Started Jan 21 03:33:43 PM PST 24
Finished Jan 21 03:35:05 PM PST 24
Peak memory 264400 kb
Host smart-981b4b59-cead-46d6-8525-a35973f65098
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072022037 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2072022037
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.669901147
Short name T697
Test name
Test status
Simulation time 718478200 ps
CPU time 63.42 seconds
Started Jan 21 03:33:54 PM PST 24
Finished Jan 21 03:35:04 PM PST 24
Peak memory 280792 kb
Host smart-ccc83c64-cd36-42cb-ab5e-493f91ca76ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669901147 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_counter.669901147
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.396838832
Short name T561
Test name
Test status
Simulation time 166921000 ps
CPU time 164.53 seconds
Started Jan 21 05:16:38 PM PST 24
Finished Jan 21 05:19:24 PM PST 24
Peak memory 274452 kb
Host smart-e19ec585-5ba3-462d-9cee-5f4b233e21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396838832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.396838832
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1873872471
Short name T565
Test name
Test status
Simulation time 94298500 ps
CPU time 26.26 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:34:09 PM PST 24
Peak memory 258016 kb
Host smart-a9988354-ec82-4e2c-a464-73867ac6c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873872471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1873872471
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.3542783005
Short name T737
Test name
Test status
Simulation time 451115900 ps
CPU time 1104.15 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:52:07 PM PST 24
Peak memory 284348 kb
Host smart-f8f85962-2427-4e84-88af-e56847061d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542783005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.3542783005
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.2927102942
Short name T581
Test name
Test status
Simulation time 62131400 ps
CPU time 27.53 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:34:00 PM PST 24
Peak memory 257988 kb
Host smart-b024ffd8-8880-4034-9f4b-415fdf2d9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927102942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2927102942
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.1524139672
Short name T710
Test name
Test status
Simulation time 4049359100 ps
CPU time 171.99 seconds
Started Jan 21 03:33:39 PM PST 24
Finished Jan 21 03:36:35 PM PST 24
Peak memory 264324 kb
Host smart-a0a301ad-1dac-4fb4-8e85-b0da173211b1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524139672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_wo.1524139672
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.863746493
Short name T175
Test name
Test status
Simulation time 175602000 ps
CPU time 15 seconds
Started Jan 21 03:33:48 PM PST 24
Finished Jan 21 03:34:08 PM PST 24
Peak memory 264348 kb
Host smart-ad53f055-0e30-432e-bdc9-c162ad331308
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863746493 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.863746493
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3256641981
Short name T965
Test name
Test status
Simulation time 66652600 ps
CPU time 17.17 seconds
Started Jan 21 03:33:38 PM PST 24
Finished Jan 21 03:33:58 PM PST 24
Peak memory 263028 kb
Host smart-a2f85db7-210f-4136-b551-2908121e19f0
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3256641981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3256641981
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.1818515204
Short name T41
Test name
Test status
Simulation time 20968300 ps
CPU time 13.75 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 03:34:43 PM PST 24
Peak memory 264332 kb
Host smart-71bc7c1b-5595-49a3-aaf1-d9bc1eeadb0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818515204 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1818515204
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2853051488
Short name T644
Test name
Test status
Simulation time 78256600 ps
CPU time 13.75 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:34:40 PM PST 24
Peak memory 264380 kb
Host smart-c1d5ea2d-72c7-4143-8130-8fcb200bf32b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853051488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
853051488
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3053147487
Short name T424
Test name
Test status
Simulation time 13141200 ps
CPU time 15.66 seconds
Started Jan 21 03:34:16 PM PST 24
Finished Jan 21 03:34:38 PM PST 24
Peak memory 273528 kb
Host smart-1ba56b76-5851-4065-b1b7-e54e6f9bc1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053147487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3053147487
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3195143662
Short name T162
Test name
Test status
Simulation time 179127400 ps
CPU time 106.18 seconds
Started Jan 21 03:34:04 PM PST 24
Finished Jan 21 03:36:00 PM PST 24
Peak memory 270616 kb
Host smart-f213dfcd-84ba-43ee-8bbe-cda592e22b9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195143662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3195143662
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.3169462002
Short name T786
Test name
Test status
Simulation time 4522239900 ps
CPU time 2464.33 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 04:15:25 PM PST 24
Peak memory 264300 kb
Host smart-0d96d34f-eaab-4890-be64-f89e7ee5de64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169462002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.3169462002
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2378969464
Short name T992
Test name
Test status
Simulation time 1272514100 ps
CPU time 813.44 seconds
Started Jan 21 03:34:09 PM PST 24
Finished Jan 21 03:47:52 PM PST 24
Peak memory 263836 kb
Host smart-4944ff02-2df7-4ac1-8673-24f8b89ad53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378969464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2378969464
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1427329939
Short name T571
Test name
Test status
Simulation time 125622900 ps
CPU time 22.55 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:34:43 PM PST 24
Peak memory 264128 kb
Host smart-933bbdfa-a8cc-4063-8b43-d7829aca8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427329939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1427329939
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.4215071722
Short name T585
Test name
Test status
Simulation time 267768300 ps
CPU time 35.76 seconds
Started Jan 21 03:34:18 PM PST 24
Finished Jan 21 03:34:58 PM PST 24
Peak memory 272544 kb
Host smart-84b3ddf2-8a08-44b1-b858-e97943de9f07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215071722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.4215071722
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.3124545549
Short name T939
Test name
Test status
Simulation time 330671841500 ps
CPU time 2651.58 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 04:18:32 PM PST 24
Peak memory 261352 kb
Host smart-ca786502-aa71-4d76-80da-0e8904c8c437
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124545549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.3124545549
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.1320991285
Short name T360
Test name
Test status
Simulation time 50054900 ps
CPU time 82.02 seconds
Started Jan 21 03:34:04 PM PST 24
Finished Jan 21 03:35:36 PM PST 24
Peak memory 260736 kb
Host smart-c7e93a79-bceb-4f49-b51e-fbf87e5d9f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320991285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1320991285
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3968704033
Short name T606
Test name
Test status
Simulation time 169348101500 ps
CPU time 1742.59 seconds
Started Jan 21 03:34:04 PM PST 24
Finished Jan 21 04:03:17 PM PST 24
Peak memory 262664 kb
Host smart-b82b6236-7f5c-437e-be38-a063547f9ced
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968704033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3968704033
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1563746997
Short name T265
Test name
Test status
Simulation time 5110703300 ps
CPU time 633.49 seconds
Started Jan 21 03:34:05 PM PST 24
Finished Jan 21 03:44:48 PM PST 24
Peak memory 334436 kb
Host smart-6fb76e99-db87-4826-b7a8-1505e89c566d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563746997 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1563746997
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1092986102
Short name T552
Test name
Test status
Simulation time 8411635400 ps
CPU time 200.78 seconds
Started Jan 21 03:34:05 PM PST 24
Finished Jan 21 03:37:36 PM PST 24
Peak memory 282956 kb
Host smart-b79538ef-7798-4c10-a53e-f17781420250
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092986102 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.1092986102
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.3553416171
Short name T756
Test name
Test status
Simulation time 34940052500 ps
CPU time 121.96 seconds
Started Jan 21 03:34:07 PM PST 24
Finished Jan 21 03:36:18 PM PST 24
Peak memory 264416 kb
Host smart-4edada7d-8f68-498e-8e3c-44912490ba2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553416171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.3553416171
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.342167831
Short name T765
Test name
Test status
Simulation time 76427534500 ps
CPU time 288.41 seconds
Started Jan 21 03:34:08 PM PST 24
Finished Jan 21 03:39:04 PM PST 24
Peak memory 264564 kb
Host smart-42ae0f2e-7b17-46f5-90aa-b5a6fc7a9338
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342
167831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.342167831
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1438419032
Short name T701
Test name
Test status
Simulation time 1628533300 ps
CPU time 65.76 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:35:25 PM PST 24
Peak memory 258060 kb
Host smart-58563bee-f717-480e-97f4-0454026ecce3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438419032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1438419032
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3254581475
Short name T714
Test name
Test status
Simulation time 28663100 ps
CPU time 13.43 seconds
Started Jan 21 03:34:17 PM PST 24
Finished Jan 21 03:34:36 PM PST 24
Peak memory 264348 kb
Host smart-f8a37fe1-a02a-4b64-b2eb-4d5f29fde759
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254581475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3254581475
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.2187802957
Short name T148
Test name
Test status
Simulation time 2319998800 ps
CPU time 69.28 seconds
Started Jan 21 03:34:06 PM PST 24
Finished Jan 21 03:35:25 PM PST 24
Peak memory 258052 kb
Host smart-5155108a-a622-43fd-9fe4-d247ea7f0168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187802957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2187802957
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.2422101438
Short name T997
Test name
Test status
Simulation time 4502200300 ps
CPU time 181.75 seconds
Started Jan 21 03:34:03 PM PST 24
Finished Jan 21 03:37:14 PM PST 24
Peak memory 289028 kb
Host smart-7a32de2d-199b-4a04-8e5e-dbc5f617e490
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422101438 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2422101438
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3871539687
Short name T713
Test name
Test status
Simulation time 32104100 ps
CPU time 111.27 seconds
Started Jan 21 03:34:07 PM PST 24
Finished Jan 21 03:36:07 PM PST 24
Peak memory 259676 kb
Host smart-244c642b-ce04-40e3-9397-383f95209823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871539687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3871539687
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.236794661
Short name T164
Test name
Test status
Simulation time 127863300 ps
CPU time 14.23 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:34:34 PM PST 24
Peak memory 264448 kb
Host smart-f469c414-7369-4167-8ed3-e518b0ab898d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236794661 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.236794661
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.4140138332
Short name T1025
Test name
Test status
Simulation time 73423100 ps
CPU time 13.63 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:34:43 PM PST 24
Peak memory 264464 kb
Host smart-a33ea263-ba51-4a80-8d3e-3a6df476104d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140138332 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.4140138332
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.3933861804
Short name T609
Test name
Test status
Simulation time 29971800 ps
CPU time 13.78 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 03:34:35 PM PST 24
Peak memory 264328 kb
Host smart-9d86b4a8-2f4d-4ac0-afe7-a9adb966d3c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933861804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.3933861804
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1895993704
Short name T596
Test name
Test status
Simulation time 854638300 ps
CPU time 1416.18 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:57:48 PM PST 24
Peak memory 284864 kb
Host smart-3ef87d5a-fddc-42b5-a142-a16d9e02afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895993704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1895993704
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.899245998
Short name T144
Test name
Test status
Simulation time 8162786500 ps
CPU time 136.21 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:36:36 PM PST 24
Peak memory 263952 kb
Host smart-cad2bcf0-e5bf-49c8-8a46-c370caea209a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899245998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.899245998
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.102177883
Short name T923
Test name
Test status
Simulation time 342086400 ps
CPU time 33.22 seconds
Started Jan 21 03:34:22 PM PST 24
Finished Jan 21 03:34:58 PM PST 24
Peak memory 277800 kb
Host smart-c1ddaee0-847c-4019-a88c-32eeaf67c6c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102177883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rd_intg.102177883
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3231218069
Short name T478
Test name
Test status
Simulation time 44872800 ps
CPU time 34.11 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:34:54 PM PST 24
Peak memory 276336 kb
Host smart-7bd73521-3d66-4522-bdcb-ae32f3601859
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231218069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3231218069
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.785425539
Short name T325
Test name
Test status
Simulation time 31011000 ps
CPU time 22.95 seconds
Started Jan 21 03:34:09 PM PST 24
Finished Jan 21 03:34:41 PM PST 24
Peak memory 264412 kb
Host smart-eb417ecd-bd0e-4ec2-bc81-c4d43158a362
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785425539 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.785425539
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3901770162
Short name T927
Test name
Test status
Simulation time 23394100 ps
CPU time 23.04 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:34:35 PM PST 24
Peak memory 263068 kb
Host smart-4a51cec0-0935-423d-93aa-6b4d4ca6f514
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901770162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.3901770162
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1496358075
Short name T97
Test name
Test status
Simulation time 97353055400 ps
CPU time 868.93 seconds
Started Jan 21 03:34:24 PM PST 24
Finished Jan 21 03:48:55 PM PST 24
Peak memory 259480 kb
Host smart-a1e3e6fe-dbf1-4384-905f-ab9e44d6e9a2
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496358075 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1496358075
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.572012718
Short name T1019
Test name
Test status
Simulation time 1385466300 ps
CPU time 83.83 seconds
Started Jan 21 03:34:05 PM PST 24
Finished Jan 21 03:35:40 PM PST 24
Peak memory 280724 kb
Host smart-d01f89de-8f3d-403f-88f7-15821918316c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572012718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_ro.572012718
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1415046040
Short name T280
Test name
Test status
Simulation time 1106499100 ps
CPU time 120.82 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:36:14 PM PST 24
Peak memory 280836 kb
Host smart-74aaca2a-0d20-46c5-ad10-62eb0aeed662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1415046040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1415046040
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1638033513
Short name T977
Test name
Test status
Simulation time 2047536900 ps
CPU time 114 seconds
Started Jan 21 03:34:07 PM PST 24
Finished Jan 21 03:36:08 PM PST 24
Peak memory 280832 kb
Host smart-cacfd13c-650b-4f9b-9bad-db00a8d40672
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638033513 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1638033513
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.1848621075
Short name T857
Test name
Test status
Simulation time 25380043700 ps
CPU time 505.53 seconds
Started Jan 21 03:34:16 PM PST 24
Finished Jan 21 03:42:47 PM PST 24
Peak memory 313416 kb
Host smart-87020304-3de4-4510-a5c3-97c894c2e986
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848621075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.1848621075
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.4264671978
Short name T851
Test name
Test status
Simulation time 3535488100 ps
CPU time 535.11 seconds
Started Jan 21 03:34:02 PM PST 24
Finished Jan 21 03:43:08 PM PST 24
Peak memory 313600 kb
Host smart-139be53d-12eb-4927-86c7-0f9ff49d1a9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264671978 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.4264671978
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1888557926
Short name T662
Test name
Test status
Simulation time 148279600 ps
CPU time 33.19 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:34:53 PM PST 24
Peak memory 270964 kb
Host smart-5a66ec61-1957-4e0e-a815-eb788fcb80c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888557926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1888557926
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3116282860
Short name T398
Test name
Test status
Simulation time 68547000 ps
CPU time 30.58 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:34:50 PM PST 24
Peak memory 273868 kb
Host smart-278dc176-9c99-4641-b5af-8529db2e4047
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116282860 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3116282860
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.2110204142
Short name T639
Test name
Test status
Simulation time 18776935200 ps
CPU time 528.21 seconds
Started Jan 21 03:34:05 PM PST 24
Finished Jan 21 03:43:03 PM PST 24
Peak memory 313524 kb
Host smart-b6ac659c-14a1-4d3b-b5e1-8847bbb94d32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110204142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.2110204142
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.544840904
Short name T74
Test name
Test status
Simulation time 9102463900 ps
CPU time 4879.77 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 04:55:40 PM PST 24
Peak memory 285140 kb
Host smart-2f3975f5-040e-423e-92dd-f9be727e784f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544840904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.544840904
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2481673909
Short name T998
Test name
Test status
Simulation time 638368300 ps
CPU time 63.86 seconds
Started Jan 21 03:34:05 PM PST 24
Finished Jan 21 03:35:18 PM PST 24
Peak memory 264420 kb
Host smart-0db03c5b-a617-406a-ae3e-1b08ca5079b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481673909 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2481673909
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2768757036
Short name T441
Test name
Test status
Simulation time 1034259900 ps
CPU time 63.9 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:35:24 PM PST 24
Peak memory 264436 kb
Host smart-49969200-fe02-457d-9e37-49ea4d9e893e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768757036 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2768757036
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2345801494
Short name T157
Test name
Test status
Simulation time 8539721800 ps
CPU time 184.59 seconds
Started Jan 21 03:33:56 PM PST 24
Finished Jan 21 03:37:06 PM PST 24
Peak memory 280680 kb
Host smart-cd5a1b4f-ce6c-4dfe-acee-99dad7fb7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345801494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2345801494
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.672825454
Short name T950
Test name
Test status
Simulation time 18115500 ps
CPU time 23.91 seconds
Started Jan 21 03:33:56 PM PST 24
Finished Jan 21 03:34:25 PM PST 24
Peak memory 258012 kb
Host smart-15a1626c-619e-4f21-a386-e2c01b288a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672825454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.672825454
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1518753330
Short name T372
Test name
Test status
Simulation time 583519500 ps
CPU time 675.21 seconds
Started Jan 21 03:34:21 PM PST 24
Finished Jan 21 03:45:40 PM PST 24
Peak memory 280668 kb
Host smart-060be247-8f92-46d0-9bae-e5a474d6c105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518753330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1518753330
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.1666400857
Short name T812
Test name
Test status
Simulation time 76397100 ps
CPU time 24.11 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:34:44 PM PST 24
Peak memory 257988 kb
Host smart-2b06c119-b087-456c-b0f1-e6c745a4e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666400857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1666400857
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3670634556
Short name T702
Test name
Test status
Simulation time 5005906100 ps
CPU time 159.14 seconds
Started Jan 21 03:34:03 PM PST 24
Finished Jan 21 03:36:52 PM PST 24
Peak memory 264364 kb
Host smart-32dfda20-e6bd-4756-8e35-741fc56e626e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670634556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.3670634556
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2002788335
Short name T11
Test name
Test status
Simulation time 164744800 ps
CPU time 14.81 seconds
Started Jan 21 03:34:13 PM PST 24
Finished Jan 21 03:34:35 PM PST 24
Peak memory 264344 kb
Host smart-1ca2fd8a-43d4-4f3d-ac5b-b9ff8e9c1ea1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002788335 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2002788335
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3633175404
Short name T560
Test name
Test status
Simulation time 44286500 ps
CPU time 13.77 seconds
Started Jan 21 03:38:09 PM PST 24
Finished Jan 21 03:38:23 PM PST 24
Peak memory 264108 kb
Host smart-a6c4bcc1-a346-46ec-bb5d-06fb802791a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633175404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3633175404
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1404832854
Short name T568
Test name
Test status
Simulation time 27961200 ps
CPU time 13.29 seconds
Started Jan 21 03:38:10 PM PST 24
Finished Jan 21 03:38:25 PM PST 24
Peak memory 273668 kb
Host smart-1c2e411e-ea06-4b54-9c40-ff480cd179c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404832854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1404832854
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.2670336074
Short name T36
Test name
Test status
Simulation time 10207600 ps
CPU time 20.79 seconds
Started Jan 21 03:38:03 PM PST 24
Finished Jan 21 03:38:24 PM PST 24
Peak memory 264428 kb
Host smart-ec751d7e-7334-4926-93b5-f9feb6e33498
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670336074 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.2670336074
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1456302801
Short name T679
Test name
Test status
Simulation time 10035282800 ps
CPU time 96.45 seconds
Started Jan 21 04:06:01 PM PST 24
Finished Jan 21 04:07:44 PM PST 24
Peak memory 270180 kb
Host smart-7637277d-e8ec-43ba-80a7-30531a2e09cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456302801 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1456302801
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2848924552
Short name T339
Test name
Test status
Simulation time 55331100 ps
CPU time 14.09 seconds
Started Jan 21 04:36:34 PM PST 24
Finished Jan 21 04:36:48 PM PST 24
Peak memory 264320 kb
Host smart-20407a27-e2ed-4c37-848c-557acacaa822
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848924552 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2848924552
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3240102457
Short name T103
Test name
Test status
Simulation time 140171320100 ps
CPU time 743.94 seconds
Started Jan 21 03:37:49 PM PST 24
Finished Jan 21 03:50:15 PM PST 24
Peak memory 262844 kb
Host smart-63726e23-3fdb-4281-ae2f-23e983cfc24c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240102457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3240102457
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3625021629
Short name T975
Test name
Test status
Simulation time 4052722900 ps
CPU time 89.67 seconds
Started Jan 21 03:37:56 PM PST 24
Finished Jan 21 03:39:27 PM PST 24
Peak memory 261432 kb
Host smart-477f4cc7-c47d-4b88-90ff-67de3a79f81a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625021629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3625021629
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1985367671
Short name T660
Test name
Test status
Simulation time 1242445200 ps
CPU time 165.66 seconds
Started Jan 21 03:38:12 PM PST 24
Finished Jan 21 03:40:59 PM PST 24
Peak memory 292184 kb
Host smart-14c5a15f-4b2b-4094-a615-43081129db2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985367671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1985367671
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3650361066
Short name T700
Test name
Test status
Simulation time 9072084400 ps
CPU time 212.71 seconds
Started Jan 21 03:38:02 PM PST 24
Finished Jan 21 03:41:35 PM PST 24
Peak memory 288932 kb
Host smart-52eeb498-cef2-43c9-94d3-c6165aa1a8ab
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650361066 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3650361066
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1972819626
Short name T910
Test name
Test status
Simulation time 28186800 ps
CPU time 13.3 seconds
Started Jan 21 04:02:32 PM PST 24
Finished Jan 21 04:02:51 PM PST 24
Peak memory 264352 kb
Host smart-e48f426e-e205-4c91-aa46-46e7eb759b58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972819626 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1972819626
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3926091051
Short name T114
Test name
Test status
Simulation time 26885220900 ps
CPU time 330.81 seconds
Started Jan 21 03:37:49 PM PST 24
Finished Jan 21 03:43:20 PM PST 24
Peak memory 272028 kb
Host smart-8108c02b-64bc-470d-b64f-b215ddb77e9e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926091051 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.3926091051
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2729068004
Short name T77
Test name
Test status
Simulation time 44228100 ps
CPU time 130.09 seconds
Started Jan 21 03:55:03 PM PST 24
Finished Jan 21 03:57:14 PM PST 24
Peak memory 258436 kb
Host smart-2270c1ff-856d-4c8e-a7fa-b22207727fc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729068004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2729068004
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2702751946
Short name T694
Test name
Test status
Simulation time 2969754900 ps
CPU time 370.37 seconds
Started Jan 21 03:37:49 PM PST 24
Finished Jan 21 03:44:00 PM PST 24
Peak memory 259932 kb
Host smart-fd6d5ae9-2fe2-4ebd-a384-68f4ab52f72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702751946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2702751946
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.160963561
Short name T865
Test name
Test status
Simulation time 118540200 ps
CPU time 21.31 seconds
Started Jan 21 03:38:01 PM PST 24
Finished Jan 21 03:38:24 PM PST 24
Peak memory 264324 kb
Host smart-063e8e9e-812b-4d35-ad74-bb9abb2c7262
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160963561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_res
et.160963561
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.4133963395
Short name T133
Test name
Test status
Simulation time 767788500 ps
CPU time 628.68 seconds
Started Jan 21 03:37:52 PM PST 24
Finished Jan 21 03:48:23 PM PST 24
Peak memory 281504 kb
Host smart-42b6db90-fc51-40aa-aaa8-8faf38c314c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133963395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.4133963395
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1900272068
Short name T490
Test name
Test status
Simulation time 457581100 ps
CPU time 37.92 seconds
Started Jan 21 03:38:13 PM PST 24
Finished Jan 21 03:38:51 PM PST 24
Peak memory 265484 kb
Host smart-b4742965-1301-4329-86da-beb470a7b277
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900272068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1900272068
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1152346725
Short name T681
Test name
Test status
Simulation time 4631972600 ps
CPU time 100.67 seconds
Started Jan 21 03:38:00 PM PST 24
Finished Jan 21 03:39:41 PM PST 24
Peak memory 280552 kb
Host smart-0112f1b9-d943-4cf0-a97b-d94487ce1c4e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152346725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.1152346725
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1540499107
Short name T504
Test name
Test status
Simulation time 3714179300 ps
CPU time 423.72 seconds
Started Jan 21 03:38:01 PM PST 24
Finished Jan 21 03:45:06 PM PST 24
Peak memory 307728 kb
Host smart-0cc697c7-7a9a-4a15-819e-08ba37c0a8d0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540499107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.1540499107
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.141872705
Short name T684
Test name
Test status
Simulation time 575238800 ps
CPU time 33.59 seconds
Started Jan 21 03:38:12 PM PST 24
Finished Jan 21 03:38:47 PM PST 24
Peak memory 270956 kb
Host smart-ff053e7c-e6f2-4db5-814c-ec193332ad03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141872705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.141872705
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2472741803
Short name T496
Test name
Test status
Simulation time 1182391400 ps
CPU time 34.62 seconds
Started Jan 21 03:38:13 PM PST 24
Finished Jan 21 03:38:48 PM PST 24
Peak memory 275692 kb
Host smart-e9bcc286-a4f2-4257-bc9d-c5d7d977d8e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472741803 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2472741803
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.4004260700
Short name T837
Test name
Test status
Simulation time 39206500 ps
CPU time 52.05 seconds
Started Jan 21 03:37:51 PM PST 24
Finished Jan 21 03:38:46 PM PST 24
Peak memory 268900 kb
Host smart-78a2675e-9375-46a4-8539-c65c768a306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004260700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4004260700
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1699011610
Short name T433
Test name
Test status
Simulation time 1188526800 ps
CPU time 32.28 seconds
Started Jan 21 03:38:12 PM PST 24
Finished Jan 21 03:38:46 PM PST 24
Peak memory 264196 kb
Host smart-e2407b02-fa85-43e4-ba81-5e13565982ee
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699011610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.1699011610
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3611756269
Short name T336
Test name
Test status
Simulation time 88190800 ps
CPU time 14.3 seconds
Started Jan 21 03:38:29 PM PST 24
Finished Jan 21 03:38:43 PM PST 24
Peak memory 264116 kb
Host smart-97fa86d5-5668-499e-abb2-d6b51ad48725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611756269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3611756269
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2876539119
Short name T516
Test name
Test status
Simulation time 33582800 ps
CPU time 15.63 seconds
Started Jan 21 03:38:17 PM PST 24
Finished Jan 21 03:38:33 PM PST 24
Peak memory 273636 kb
Host smart-1f817bfa-144a-4eab-999c-80f48f6228c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876539119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2876539119
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2662531316
Short name T90
Test name
Test status
Simulation time 10012315600 ps
CPU time 312.89 seconds
Started Jan 21 03:38:28 PM PST 24
Finished Jan 21 03:43:42 PM PST 24
Peak memory 308836 kb
Host smart-6f06067c-113b-429e-a657-6027b489ed37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662531316 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2662531316
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3270363602
Short name T645
Test name
Test status
Simulation time 46908100 ps
CPU time 13.69 seconds
Started Jan 21 03:38:23 PM PST 24
Finished Jan 21 03:38:40 PM PST 24
Peak memory 264304 kb
Host smart-a67ede5a-22a0-4739-ab3b-825a41e835eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270363602 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3270363602
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.4235601089
Short name T438
Test name
Test status
Simulation time 3646225700 ps
CPU time 84.47 seconds
Started Jan 21 03:38:09 PM PST 24
Finished Jan 21 03:39:34 PM PST 24
Peak memory 261392 kb
Host smart-486998cc-ae7c-4289-83c3-f2cd08d96512
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235601089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.4235601089
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1765386784
Short name T407
Test name
Test status
Simulation time 5243010800 ps
CPU time 165.69 seconds
Started Jan 21 03:38:23 PM PST 24
Finished Jan 21 03:41:12 PM PST 24
Peak memory 291988 kb
Host smart-72a56fac-598a-4600-83c7-bd487174aa0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765386784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1765386784
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2049312691
Short name T481
Test name
Test status
Simulation time 123289783400 ps
CPU time 300.35 seconds
Started Jan 21 03:38:18 PM PST 24
Finished Jan 21 03:43:19 PM PST 24
Peak memory 289004 kb
Host smart-59f3334b-ba23-4fc0-89e4-8c7d5ae71a97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049312691 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2049312691
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1093242821
Short name T434
Test name
Test status
Simulation time 1635843900 ps
CPU time 67.77 seconds
Started Jan 21 03:38:10 PM PST 24
Finished Jan 21 03:39:19 PM PST 24
Peak memory 258092 kb
Host smart-ca04a3dc-745e-4fdc-8b88-ca3a98ca9939
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093242821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
093242821
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3769255200
Short name T688
Test name
Test status
Simulation time 2239971500 ps
CPU time 195.54 seconds
Started Jan 21 06:02:50 PM PST 24
Finished Jan 21 06:06:06 PM PST 24
Peak memory 260232 kb
Host smart-1d638087-31aa-4a48-8819-d84089af26b3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769255200 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3769255200
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2749675527
Short name T71
Test name
Test status
Simulation time 66406300 ps
CPU time 283.28 seconds
Started Jan 21 03:38:10 PM PST 24
Finished Jan 21 03:42:55 PM PST 24
Peak memory 260664 kb
Host smart-5585f492-53c2-4d34-9a42-af8fe3391423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749675527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2749675527
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.4134955683
Short name T576
Test name
Test status
Simulation time 162372400 ps
CPU time 20.55 seconds
Started Jan 21 03:38:25 PM PST 24
Finished Jan 21 03:38:47 PM PST 24
Peak memory 264304 kb
Host smart-a5a22c28-e5c0-4f47-9b2b-2bca53f1c949
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134955683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.4134955683
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1766362833
Short name T873
Test name
Test status
Simulation time 380462600 ps
CPU time 397.19 seconds
Started Jan 21 03:38:15 PM PST 24
Finished Jan 21 03:44:53 PM PST 24
Peak memory 275560 kb
Host smart-85b3a932-183b-4ddd-b3cc-4ab79dfbb73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766362833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1766362833
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.421739711
Short name T393
Test name
Test status
Simulation time 395260000 ps
CPU time 38.52 seconds
Started Jan 21 03:38:18 PM PST 24
Finished Jan 21 03:38:57 PM PST 24
Peak memory 275504 kb
Host smart-c53eaef0-802e-4ec3-89d8-08b9e1f33239
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421739711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.421739711
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.3660870374
Short name T880
Test name
Test status
Simulation time 456920600 ps
CPU time 95.25 seconds
Started Jan 21 03:38:07 PM PST 24
Finished Jan 21 03:39:43 PM PST 24
Peak memory 280648 kb
Host smart-b9d7e6a8-2962-40f6-b115-adfeb0429e86
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660870374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.3660870374
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1172612169
Short name T535
Test name
Test status
Simulation time 11891041400 ps
CPU time 557.49 seconds
Started Jan 21 03:38:24 PM PST 24
Finished Jan 21 03:47:44 PM PST 24
Peak memory 312284 kb
Host smart-5c6409c9-83e1-4771-8b3d-416c3db2800a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172612169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.1172612169
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.117792381
Short name T207
Test name
Test status
Simulation time 132699100 ps
CPU time 31.24 seconds
Started Jan 21 03:38:23 PM PST 24
Finished Jan 21 03:38:58 PM PST 24
Peak memory 264460 kb
Host smart-6b34e06b-6a72-4ecf-8e14-f246ff316b2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117792381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_rw_evict.117792381
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1911973535
Short name T293
Test name
Test status
Simulation time 46258300 ps
CPU time 33.09 seconds
Started Jan 21 03:38:24 PM PST 24
Finished Jan 21 03:39:00 PM PST 24
Peak memory 274688 kb
Host smart-249426f0-b88b-4bbf-9e65-1da9730048da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911973535 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1911973535
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1428126070
Short name T444
Test name
Test status
Simulation time 9510624300 ps
CPU time 86.45 seconds
Started Jan 21 03:38:18 PM PST 24
Finished Jan 21 03:39:46 PM PST 24
Peak memory 258104 kb
Host smart-b3874299-f2b7-45f8-b0b3-d7c2c83a8ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428126070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1428126070
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2603784548
Short name T459
Test name
Test status
Simulation time 51142000 ps
CPU time 77.36 seconds
Started Jan 21 05:20:44 PM PST 24
Finished Jan 21 05:22:02 PM PST 24
Peak memory 273248 kb
Host smart-6ee44547-0e2b-4e2f-9471-0fff56cffe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603784548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2603784548
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3335811384
Short name T447
Test name
Test status
Simulation time 29031387300 ps
CPU time 138.59 seconds
Started Jan 21 04:48:47 PM PST 24
Finished Jan 21 04:51:07 PM PST 24
Peak memory 264304 kb
Host smart-dbda7b20-b5a1-4988-926c-59334db4b2c7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335811384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.3335811384
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1492713228
Short name T746
Test name
Test status
Simulation time 426079100 ps
CPU time 13.89 seconds
Started Jan 21 03:38:42 PM PST 24
Finished Jan 21 03:38:57 PM PST 24
Peak memory 264264 kb
Host smart-aa6ae59a-30ef-4e55-9352-2815c153e0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492713228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1492713228
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.9507077
Short name T513
Test name
Test status
Simulation time 41551600 ps
CPU time 13.27 seconds
Started Jan 21 04:06:10 PM PST 24
Finished Jan 21 04:06:28 PM PST 24
Peak memory 273576 kb
Host smart-37b60df7-c1d2-4ab4-9920-3fecf55ef77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9507077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.9507077
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1635381284
Short name T904
Test name
Test status
Simulation time 10012539600 ps
CPU time 131.91 seconds
Started Jan 21 03:38:41 PM PST 24
Finished Jan 21 03:40:54 PM PST 24
Peak memory 359616 kb
Host smart-dcfdc76e-bd91-46d4-938c-7d241c24614a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635381284 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1635381284
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.824148430
Short name T641
Test name
Test status
Simulation time 15319500 ps
CPU time 14.31 seconds
Started Jan 21 04:02:00 PM PST 24
Finished Jan 21 04:02:19 PM PST 24
Peak memory 264284 kb
Host smart-2b6797b0-2d50-4e74-9cbd-e9fa938667ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824148430 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.824148430
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.772607212
Short name T657
Test name
Test status
Simulation time 20159233800 ps
CPU time 69.86 seconds
Started Jan 21 03:38:32 PM PST 24
Finished Jan 21 03:39:43 PM PST 24
Peak memory 260900 kb
Host smart-45d2aa7c-b207-4948-a496-fd2cb52130a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772607212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.772607212
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.2723567382
Short name T281
Test name
Test status
Simulation time 5718775600 ps
CPU time 156.87 seconds
Started Jan 21 03:38:34 PM PST 24
Finished Jan 21 03:41:12 PM PST 24
Peak memory 292248 kb
Host smart-2d0ddfd3-41e1-40e7-92fc-07f9a9e1a786
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723567382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.2723567382
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2035366647
Short name T410
Test name
Test status
Simulation time 10652701400 ps
CPU time 222.84 seconds
Started Jan 21 03:38:37 PM PST 24
Finished Jan 21 03:42:21 PM PST 24
Peak memory 288940 kb
Host smart-d1fad024-11cf-4433-a98c-627ce40fd64d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035366647 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2035366647
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.1356614901
Short name T384
Test name
Test status
Simulation time 2994139900 ps
CPU time 71.1 seconds
Started Jan 21 03:38:37 PM PST 24
Finished Jan 21 03:39:49 PM PST 24
Peak memory 258148 kb
Host smart-6d749173-1f74-4083-a398-0d23d448cc3d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356614901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1
356614901
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1833832768
Short name T299
Test name
Test status
Simulation time 85547600 ps
CPU time 13.53 seconds
Started Jan 21 03:38:42 PM PST 24
Finished Jan 21 03:38:56 PM PST 24
Peak memory 264348 kb
Host smart-dde6eb93-f68b-4ced-aab2-811edef60dc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833832768 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1833832768
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2139504198
Short name T590
Test name
Test status
Simulation time 64292700 ps
CPU time 109.48 seconds
Started Jan 21 03:38:29 PM PST 24
Finished Jan 21 03:40:19 PM PST 24
Peak memory 259900 kb
Host smart-f57e2854-814a-416f-95f5-d60b76da76c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139504198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2139504198
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.350212688
Short name T505
Test name
Test status
Simulation time 160837200 ps
CPU time 13.99 seconds
Started Jan 21 03:38:36 PM PST 24
Finished Jan 21 03:38:51 PM PST 24
Peak memory 264320 kb
Host smart-aa7a2082-f27a-4fb1-987c-b8975e4e3a2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350212688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_res
et.350212688
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.3384276377
Short name T132
Test name
Test status
Simulation time 289444000 ps
CPU time 300.11 seconds
Started Jan 21 03:38:28 PM PST 24
Finished Jan 21 03:43:29 PM PST 24
Peak memory 280612 kb
Host smart-d5843820-74ee-4267-9e30-6984545d250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384276377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3384276377
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.3146567721
Short name T651
Test name
Test status
Simulation time 132410400 ps
CPU time 37.39 seconds
Started Jan 21 03:38:44 PM PST 24
Finished Jan 21 03:39:23 PM PST 24
Peak memory 276016 kb
Host smart-0790a0f9-883e-41c5-b18d-f691ab2ae786
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146567721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.3146567721
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.3928143393
Short name T195
Test name
Test status
Simulation time 404544700 ps
CPU time 94.58 seconds
Started Jan 21 03:38:47 PM PST 24
Finished Jan 21 03:40:23 PM PST 24
Peak memory 280500 kb
Host smart-27f14ad5-2c28-477c-8491-c1eaadaf7ca3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928143393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.3928143393
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2584406043
Short name T474
Test name
Test status
Simulation time 4142993900 ps
CPU time 548.03 seconds
Started Jan 21 03:38:42 PM PST 24
Finished Jan 21 03:47:51 PM PST 24
Peak memory 312820 kb
Host smart-6cdae945-092c-4a89-b905-70aefe28c9fb
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584406043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw.2584406043
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.851214036
Short name T292
Test name
Test status
Simulation time 94823400 ps
CPU time 31.93 seconds
Started Jan 21 03:38:42 PM PST 24
Finished Jan 21 03:39:15 PM PST 24
Peak memory 272680 kb
Host smart-901eeb4b-50c7-4b47-8234-3cf1afbbe833
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851214036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.851214036
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1508748633
Short name T399
Test name
Test status
Simulation time 43122700 ps
CPU time 32.41 seconds
Started Jan 21 03:38:41 PM PST 24
Finished Jan 21 03:39:15 PM PST 24
Peak memory 272684 kb
Host smart-37c46db8-056b-4521-a107-5308bdd00c42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508748633 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1508748633
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.4031791487
Short name T994
Test name
Test status
Simulation time 154750300 ps
CPU time 49.28 seconds
Started Jan 21 03:38:31 PM PST 24
Finished Jan 21 03:39:21 PM PST 24
Peak memory 268872 kb
Host smart-528ff638-43ea-450c-b738-cc628c1dbe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031791487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.4031791487
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.303023791
Short name T126
Test name
Test status
Simulation time 9137773400 ps
CPU time 199 seconds
Started Jan 21 03:38:47 PM PST 24
Finished Jan 21 03:42:07 PM PST 24
Peak memory 264304 kb
Host smart-6bb96ad0-f5c2-4dd8-b8b2-b09d9bc7e09f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303023791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_wo.303023791
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3832647386
Short name T427
Test name
Test status
Simulation time 220357200 ps
CPU time 14 seconds
Started Jan 21 03:39:10 PM PST 24
Finished Jan 21 03:39:25 PM PST 24
Peak memory 264308 kb
Host smart-a501a223-20b4-422b-9f02-13a3a07dc943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832647386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3832647386
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3489643063
Short name T429
Test name
Test status
Simulation time 108938300 ps
CPU time 15.67 seconds
Started Jan 21 03:39:12 PM PST 24
Finished Jan 21 03:39:28 PM PST 24
Peak memory 273576 kb
Host smart-91b4e6b3-d82e-4b57-b22e-6d67dd21caaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489643063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3489643063
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.18743575
Short name T727
Test name
Test status
Simulation time 21522300 ps
CPU time 22.17 seconds
Started Jan 21 03:39:09 PM PST 24
Finished Jan 21 03:39:33 PM PST 24
Peak memory 264468 kb
Host smart-e2f839d6-c46f-4cb7-88ce-3028d24f73e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18743575 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_disable.18743575
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.990754250
Short name T330
Test name
Test status
Simulation time 10035068100 ps
CPU time 60.49 seconds
Started Jan 21 03:39:10 PM PST 24
Finished Jan 21 03:40:12 PM PST 24
Peak memory 290484 kb
Host smart-c26ffa4c-283a-4611-a530-bab6de5431e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990754250 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.990754250
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3734785010
Short name T831
Test name
Test status
Simulation time 15235500 ps
CPU time 13.54 seconds
Started Jan 21 03:39:09 PM PST 24
Finished Jan 21 03:39:23 PM PST 24
Peak memory 264288 kb
Host smart-1ec86b32-bec8-4671-8266-69b6e2be20fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734785010 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3734785010
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2286506473
Short name T936
Test name
Test status
Simulation time 40126784500 ps
CPU time 806.83 seconds
Started Jan 21 04:08:20 PM PST 24
Finished Jan 21 04:21:51 PM PST 24
Peak memory 262408 kb
Host smart-29e71204-a1b9-4900-ab44-ae39f58fc8ca
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286506473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2286506473
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2494746550
Short name T546
Test name
Test status
Simulation time 5490764600 ps
CPU time 108.04 seconds
Started Jan 21 03:38:52 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 261084 kb
Host smart-ebeb05ac-3a34-470b-b366-f6ec52ec63ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494746550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.2494746550
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.640900048
Short name T502
Test name
Test status
Simulation time 4125790700 ps
CPU time 179.17 seconds
Started Jan 21 05:34:42 PM PST 24
Finished Jan 21 05:37:42 PM PST 24
Peak memory 283056 kb
Host smart-b6268098-9405-4743-adae-da7b5e503da4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640900048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flas
h_ctrl_intr_rd.640900048
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.725571540
Short name T528
Test name
Test status
Simulation time 16725662300 ps
CPU time 221.53 seconds
Started Jan 21 04:13:26 PM PST 24
Finished Jan 21 04:17:13 PM PST 24
Peak memory 282944 kb
Host smart-fe137221-f663-4512-9060-9576a14b4d69
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725571540 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.725571540
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.1071915242
Short name T130
Test name
Test status
Simulation time 1010080100 ps
CPU time 88.85 seconds
Started Jan 21 03:38:50 PM PST 24
Finished Jan 21 03:40:20 PM PST 24
Peak memory 258848 kb
Host smart-c1956f98-0487-4910-9064-87eae1e3389b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071915242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1
071915242
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.4018099887
Short name T85
Test name
Test status
Simulation time 19942900 ps
CPU time 13.49 seconds
Started Jan 21 03:39:09 PM PST 24
Finished Jan 21 03:39:23 PM PST 24
Peak memory 264320 kb
Host smart-17c80424-9669-4c97-bf45-0b07086ff98a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018099887 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.4018099887
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2787594417
Short name T229
Test name
Test status
Simulation time 5184752800 ps
CPU time 141.18 seconds
Started Jan 21 03:38:53 PM PST 24
Finished Jan 21 03:41:16 PM PST 24
Peak memory 260724 kb
Host smart-57bc0822-da52-416b-9929-cb8dc8720508
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787594417 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2787594417
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.2112791659
Short name T838
Test name
Test status
Simulation time 158022200 ps
CPU time 364.19 seconds
Started Jan 21 03:38:51 PM PST 24
Finished Jan 21 03:44:56 PM PST 24
Peak memory 264292 kb
Host smart-e9516b65-7322-4401-8135-2bf3fdb2b867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112791659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2112791659
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3136671803
Short name T558
Test name
Test status
Simulation time 18514100 ps
CPU time 13.49 seconds
Started Jan 21 03:38:59 PM PST 24
Finished Jan 21 03:39:13 PM PST 24
Peak memory 264300 kb
Host smart-363b090e-59f0-4d2d-9d58-9337d92add2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136671803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3136671803
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.1344774733
Short name T52
Test name
Test status
Simulation time 119411500 ps
CPU time 37.74 seconds
Started Jan 21 03:39:10 PM PST 24
Finished Jan 21 03:39:49 PM PST 24
Peak memory 270932 kb
Host smart-bb791165-9c6f-4840-9de1-d8a35fa5c493
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344774733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.1344774733
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3778408402
Short name T871
Test name
Test status
Simulation time 425651200 ps
CPU time 106.14 seconds
Started Jan 21 03:39:02 PM PST 24
Finished Jan 21 03:40:49 PM PST 24
Peak memory 280636 kb
Host smart-5dbfbf54-caaa-44ec-917a-99bdddd5865d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778408402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3778408402
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2062623262
Short name T811
Test name
Test status
Simulation time 3149423000 ps
CPU time 439.37 seconds
Started Jan 21 03:39:00 PM PST 24
Finished Jan 21 03:46:20 PM PST 24
Peak memory 313184 kb
Host smart-4486eb2b-72d9-46cd-9a1e-1438c2d02393
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062623262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.2062623262
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.533353255
Short name T65
Test name
Test status
Simulation time 45448400 ps
CPU time 31.97 seconds
Started Jan 21 03:39:04 PM PST 24
Finished Jan 21 03:39:36 PM PST 24
Peak memory 272728 kb
Host smart-66314667-3103-4b7f-9c08-7e869233c964
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533353255 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.533353255
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.995727636
Short name T382
Test name
Test status
Simulation time 10064025800 ps
CPU time 75.06 seconds
Started Jan 21 03:39:12 PM PST 24
Finished Jan 21 03:40:29 PM PST 24
Peak memory 258060 kb
Host smart-c6a3f832-7a3b-4fd7-81de-7b6216d66613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995727636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.995727636
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.523726129
Short name T707
Test name
Test status
Simulation time 98927000 ps
CPU time 99.51 seconds
Started Jan 21 03:38:51 PM PST 24
Finished Jan 21 03:40:31 PM PST 24
Peak memory 273668 kb
Host smart-ac0b42cc-8863-475b-af22-cfd0456524f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523726129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.523726129
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3573769524
Short name T261
Test name
Test status
Simulation time 3317975500 ps
CPU time 150.13 seconds
Started Jan 21 03:39:00 PM PST 24
Finished Jan 21 03:41:31 PM PST 24
Peak memory 264388 kb
Host smart-85962bec-c24e-418e-8a87-c3625640e02a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573769524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.3573769524
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.205740161
Short name T1002
Test name
Test status
Simulation time 102750100 ps
CPU time 13.79 seconds
Started Jan 21 03:39:30 PM PST 24
Finished Jan 21 03:39:49 PM PST 24
Peak memory 264372 kb
Host smart-0de0aa43-e227-4d48-95c7-5de850bdcb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205740161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.205740161
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.22435316
Short name T426
Test name
Test status
Simulation time 54177000 ps
CPU time 13.56 seconds
Started Jan 21 03:39:25 PM PST 24
Finished Jan 21 03:39:41 PM PST 24
Peak memory 273684 kb
Host smart-01f5f49e-03b7-423c-bacd-8563db844e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22435316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.22435316
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1637890800
Short name T1007
Test name
Test status
Simulation time 10033282200 ps
CPU time 46.94 seconds
Started Jan 21 03:39:29 PM PST 24
Finished Jan 21 03:40:22 PM PST 24
Peak memory 264444 kb
Host smart-0c6cdb1a-2f15-41f3-be85-c7097b0e3a8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637890800 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1637890800
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2056060711
Short name T911
Test name
Test status
Simulation time 15798900 ps
CPU time 13.99 seconds
Started Jan 21 04:17:24 PM PST 24
Finished Jan 21 04:17:39 PM PST 24
Peak memory 264336 kb
Host smart-b60488a4-836c-44ee-9a71-8c042f1c489c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056060711 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2056060711
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.3723091368
Short name T830
Test name
Test status
Simulation time 2233879600 ps
CPU time 60.12 seconds
Started Jan 21 03:39:18 PM PST 24
Finished Jan 21 03:40:19 PM PST 24
Peak memory 260936 kb
Host smart-403038c1-2d80-4ab5-b5ce-b074444713ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723091368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.3723091368
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4038719237
Short name T526
Test name
Test status
Simulation time 31409594800 ps
CPU time 222.92 seconds
Started Jan 21 03:39:15 PM PST 24
Finished Jan 21 03:42:58 PM PST 24
Peak memory 282996 kb
Host smart-99e653f1-17b2-4612-abeb-1e8e12d50f3e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038719237 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.4038719237
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3875251577
Short name T799
Test name
Test status
Simulation time 1110212200 ps
CPU time 86.85 seconds
Started Jan 21 03:57:10 PM PST 24
Finished Jan 21 03:58:38 PM PST 24
Peak memory 258076 kb
Host smart-4ae1ddf5-1602-48af-a51d-f677ed2a4c4f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875251577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
875251577
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2508212647
Short name T951
Test name
Test status
Simulation time 15817700 ps
CPU time 13.46 seconds
Started Jan 21 03:39:29 PM PST 24
Finished Jan 21 03:39:49 PM PST 24
Peak memory 264348 kb
Host smart-29cf2fc6-fe8a-44ae-8182-cf80909b38fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508212647 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2508212647
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2797155617
Short name T887
Test name
Test status
Simulation time 26200692700 ps
CPU time 209.2 seconds
Started Jan 21 03:39:15 PM PST 24
Finished Jan 21 03:42:44 PM PST 24
Peak memory 271760 kb
Host smart-80240b52-d542-47a9-b979-8fe2acba1cc8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797155617 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2797155617
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.4241780750
Short name T754
Test name
Test status
Simulation time 305337000 ps
CPU time 405.23 seconds
Started Jan 21 03:39:17 PM PST 24
Finished Jan 21 03:46:04 PM PST 24
Peak memory 260864 kb
Host smart-a2009e9a-b225-4aef-a725-fd404f3dcd56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241780750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.4241780750
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.258246252
Short name T458
Test name
Test status
Simulation time 76304600 ps
CPU time 13.91 seconds
Started Jan 21 03:39:17 PM PST 24
Finished Jan 21 03:39:32 PM PST 24
Peak memory 264340 kb
Host smart-4462f224-74c4-4716-82cb-987ea4b18431
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258246252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.258246252
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.1143769867
Short name T465
Test name
Test status
Simulation time 170434700 ps
CPU time 673.55 seconds
Started Jan 21 03:49:52 PM PST 24
Finished Jan 21 04:01:08 PM PST 24
Peak memory 280804 kb
Host smart-ac7cab12-47f1-44a4-b012-c5f01f5d781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143769867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1143769867
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3879963831
Short name T547
Test name
Test status
Simulation time 104001700 ps
CPU time 36.91 seconds
Started Jan 21 03:39:27 PM PST 24
Finished Jan 21 03:40:05 PM PST 24
Peak memory 265476 kb
Host smart-235180db-429e-4e10-b974-0399d6925820
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879963831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3879963831
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1805000936
Short name T477
Test name
Test status
Simulation time 382851300 ps
CPU time 95.53 seconds
Started Jan 21 03:39:16 PM PST 24
Finished Jan 21 03:40:53 PM PST 24
Peak memory 280636 kb
Host smart-7d8d0db5-f148-4536-a8f4-de7c5675d613
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805000936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.1805000936
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3111139750
Short name T909
Test name
Test status
Simulation time 19033212400 ps
CPU time 500.39 seconds
Started Jan 21 03:39:17 PM PST 24
Finished Jan 21 03:47:39 PM PST 24
Peak memory 313448 kb
Host smart-d1c7d743-ad14-4211-94fc-bc40772a6bbc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111139750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw.3111139750
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.3668416629
Short name T637
Test name
Test status
Simulation time 28298200 ps
CPU time 31.77 seconds
Started Jan 21 03:39:27 PM PST 24
Finished Jan 21 03:40:00 PM PST 24
Peak memory 272640 kb
Host smart-f8228548-7e77-49e8-a98a-7f6f042031fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668416629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.3668416629
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.4069275150
Short name T990
Test name
Test status
Simulation time 5955003000 ps
CPU time 65.06 seconds
Started Jan 21 03:39:29 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 261544 kb
Host smart-17816791-03d5-494c-8695-003eaa0d4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069275150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.4069275150
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.1821665743
Short name T741
Test name
Test status
Simulation time 61034500 ps
CPU time 168.47 seconds
Started Jan 21 03:39:15 PM PST 24
Finished Jan 21 03:42:04 PM PST 24
Peak memory 274868 kb
Host smart-e51b79ab-390a-4857-8e72-6623ba700577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821665743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1821665743
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1244154999
Short name T905
Test name
Test status
Simulation time 10988589800 ps
CPU time 245.96 seconds
Started Jan 21 03:39:16 PM PST 24
Finished Jan 21 03:43:23 PM PST 24
Peak memory 264508 kb
Host smart-d3a4e86b-24b6-429d-9575-f014f30b1b5d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244154999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.1244154999
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3203380323
Short name T1038
Test name
Test status
Simulation time 124435900 ps
CPU time 13.71 seconds
Started Jan 21 03:39:46 PM PST 24
Finished Jan 21 03:40:01 PM PST 24
Peak memory 264272 kb
Host smart-6235e218-ad23-4660-815e-b8f1cc0964a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203380323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3203380323
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3721278202
Short name T439
Test name
Test status
Simulation time 32594800 ps
CPU time 16.13 seconds
Started Jan 21 03:39:46 PM PST 24
Finished Jan 21 03:40:02 PM PST 24
Peak memory 273492 kb
Host smart-22dab5c5-3bd8-42b6-b884-498dfe4070ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721278202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3721278202
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1248995293
Short name T896
Test name
Test status
Simulation time 10035643900 ps
CPU time 54.56 seconds
Started Jan 21 03:39:45 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 284832 kb
Host smart-87f1a8bf-5fcb-4c35-a707-386662d815e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248995293 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1248995293
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3129705149
Short name T600
Test name
Test status
Simulation time 44378100 ps
CPU time 13.62 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:40:05 PM PST 24
Peak memory 264312 kb
Host smart-c9d16bf9-8326-4af0-930d-cfab5d00e750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129705149 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3129705149
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.690306283
Short name T625
Test name
Test status
Simulation time 9119729200 ps
CPU time 50.36 seconds
Started Jan 21 03:39:36 PM PST 24
Finished Jan 21 03:40:29 PM PST 24
Peak memory 261268 kb
Host smart-ced716e2-338f-4c89-89cd-069ebb60e53a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690306283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.690306283
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.4047442204
Short name T833
Test name
Test status
Simulation time 3407498700 ps
CPU time 167.05 seconds
Started Jan 21 03:39:33 PM PST 24
Finished Jan 21 03:42:24 PM PST 24
Peak memory 282952 kb
Host smart-b60f79e4-8b88-458a-a318-74be820c5b2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047442204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.4047442204
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2062926358
Short name T1061
Test name
Test status
Simulation time 19786528700 ps
CPU time 246.24 seconds
Started Jan 21 03:39:33 PM PST 24
Finished Jan 21 03:43:42 PM PST 24
Peak memory 288964 kb
Host smart-7cfd86b7-2617-49b1-9ab2-113e70eb234e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062926358 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2062926358
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3524517607
Short name T825
Test name
Test status
Simulation time 15046400 ps
CPU time 13.41 seconds
Started Jan 21 03:39:46 PM PST 24
Finished Jan 21 03:40:00 PM PST 24
Peak memory 264380 kb
Host smart-a0a6379d-b9b6-448e-b518-7d0b8eab59d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524517607 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3524517607
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.4105595628
Short name T110
Test name
Test status
Simulation time 18765313700 ps
CPU time 232.09 seconds
Started Jan 21 03:39:37 PM PST 24
Finished Jan 21 03:43:32 PM PST 24
Peak memory 271916 kb
Host smart-8479bfb1-8c30-4459-8d72-3d878b1f4cd5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105595628 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.4105595628
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2313195598
Short name T748
Test name
Test status
Simulation time 713023200 ps
CPU time 245.4 seconds
Started Jan 21 03:39:37 PM PST 24
Finished Jan 21 03:43:45 PM PST 24
Peak memory 260776 kb
Host smart-4c7fa3e9-7cd6-44ff-a364-f995338d8a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313195598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2313195598
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.737443756
Short name T432
Test name
Test status
Simulation time 68908300 ps
CPU time 13.62 seconds
Started Jan 21 03:39:41 PM PST 24
Finished Jan 21 03:39:55 PM PST 24
Peak memory 264324 kb
Host smart-2ce0feda-c71d-4302-94c6-8dbafe52106e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737443756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.737443756
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3417010466
Short name T120
Test name
Test status
Simulation time 457326500 ps
CPU time 729.44 seconds
Started Jan 21 03:39:41 PM PST 24
Finished Jan 21 03:51:51 PM PST 24
Peak memory 282408 kb
Host smart-a02c8fc3-cef9-4ccf-afab-a972311aee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417010466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3417010466
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1961401185
Short name T689
Test name
Test status
Simulation time 498555600 ps
CPU time 39 seconds
Started Jan 21 03:58:35 PM PST 24
Finished Jan 21 03:59:15 PM PST 24
Peak memory 265496 kb
Host smart-760741d0-6a63-4cf1-b4f3-d7787c372002
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961401185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1961401185
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1220072693
Short name T145
Test name
Test status
Simulation time 407249000 ps
CPU time 92.01 seconds
Started Jan 21 03:39:36 PM PST 24
Finished Jan 21 03:41:11 PM PST 24
Peak memory 280652 kb
Host smart-cff7b1aa-1809-4a1d-ae90-dd247aceb1ed
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220072693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.1220072693
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.3137413943
Short name T889
Test name
Test status
Simulation time 4222306200 ps
CPU time 522.16 seconds
Started Jan 21 03:39:32 PM PST 24
Finished Jan 21 03:48:18 PM PST 24
Peak memory 313020 kb
Host smart-f24291eb-bd8d-46a1-989d-a0ea445a252c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137413943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.3137413943
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.2246462306
Short name T850
Test name
Test status
Simulation time 123627200 ps
CPU time 33.33 seconds
Started Jan 21 03:39:36 PM PST 24
Finished Jan 21 03:40:13 PM PST 24
Peak memory 276464 kb
Host smart-ca237bfa-92e3-4b72-91b0-387d0f1f02f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246462306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.2246462306
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1226931868
Short name T616
Test name
Test status
Simulation time 103736200 ps
CPU time 36.49 seconds
Started Jan 21 03:39:39 PM PST 24
Finished Jan 21 03:40:17 PM PST 24
Peak memory 272676 kb
Host smart-dfc34da9-e632-4292-9715-d4983e1b4d67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226931868 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1226931868
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2883141595
Short name T966
Test name
Test status
Simulation time 510795900 ps
CPU time 63.96 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:40:56 PM PST 24
Peak memory 261636 kb
Host smart-42a7184d-8992-4618-9361-41dd0e2dcc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883141595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2883141595
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1625288642
Short name T518
Test name
Test status
Simulation time 256269500 ps
CPU time 122.53 seconds
Started Jan 21 03:39:33 PM PST 24
Finished Jan 21 03:41:38 PM PST 24
Peak memory 265852 kb
Host smart-f26eea52-f592-403f-80a2-49d836df33b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625288642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1625288642
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.1225060978
Short name T726
Test name
Test status
Simulation time 2199584700 ps
CPU time 178.52 seconds
Started Jan 21 03:39:33 PM PST 24
Finished Jan 21 03:42:34 PM PST 24
Peak memory 264356 kb
Host smart-e9954780-b7b0-4b7a-8bae-9ad03c246b97
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225060978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.1225060978
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.1791654769
Short name T421
Test name
Test status
Simulation time 89990600 ps
CPU time 13.33 seconds
Started Jan 21 04:08:09 PM PST 24
Finished Jan 21 04:08:25 PM PST 24
Peak memory 264428 kb
Host smart-edefc17e-5e9e-4227-982b-92ab72032be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791654769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
1791654769
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.323589696
Short name T450
Test name
Test status
Simulation time 17569500 ps
CPU time 15.77 seconds
Started Jan 21 03:40:07 PM PST 24
Finished Jan 21 03:40:24 PM PST 24
Peak memory 273716 kb
Host smart-dcbc3d0d-f87a-4687-a1b4-e218d61df7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323589696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.323589696
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3817336563
Short name T297
Test name
Test status
Simulation time 10020932100 ps
CPU time 68.6 seconds
Started Jan 21 03:40:07 PM PST 24
Finished Jan 21 03:41:16 PM PST 24
Peak memory 280828 kb
Host smart-255aef89-2aef-4992-98af-b7bdaf9788f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817336563 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3817336563
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3192560288
Short name T773
Test name
Test status
Simulation time 70327600 ps
CPU time 13.59 seconds
Started Jan 21 03:40:09 PM PST 24
Finished Jan 21 03:40:23 PM PST 24
Peak memory 262932 kb
Host smart-64ef6d0b-4d56-4226-bb6b-0f1859413bb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192560288 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3192560288
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2968969841
Short name T807
Test name
Test status
Simulation time 40127158000 ps
CPU time 788.7 seconds
Started Jan 21 04:03:03 PM PST 24
Finished Jan 21 04:16:13 PM PST 24
Peak memory 262332 kb
Host smart-c2b8b05a-5fe4-46ad-ac66-3488e69963c4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968969841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.2968969841
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2280994936
Short name T1039
Test name
Test status
Simulation time 21960632500 ps
CPU time 158.34 seconds
Started Jan 21 03:39:49 PM PST 24
Finished Jan 21 03:42:29 PM PST 24
Peak memory 260836 kb
Host smart-7830225f-3175-4e7d-9840-c85329cb62ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280994936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2280994936
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1015177682
Short name T150
Test name
Test status
Simulation time 17672870100 ps
CPU time 197.14 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:43:10 PM PST 24
Peak memory 288972 kb
Host smart-db20ab18-0595-4404-8f1c-7015281d4344
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015177682 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.1015177682
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3893190450
Short name T705
Test name
Test status
Simulation time 2567698600 ps
CPU time 75.55 seconds
Started Jan 21 03:39:51 PM PST 24
Finished Jan 21 03:41:12 PM PST 24
Peak memory 258120 kb
Host smart-380409df-c509-453e-8144-c37cacfeffbc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893190450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
893190450
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.285188376
Short name T989
Test name
Test status
Simulation time 53037200 ps
CPU time 13.41 seconds
Started Jan 21 03:40:06 PM PST 24
Finished Jan 21 03:40:20 PM PST 24
Peak memory 264360 kb
Host smart-8a91544c-47dd-4854-857d-f4b08bbce717
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285188376 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.285188376
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.652677001
Short name T953
Test name
Test status
Simulation time 10808209200 ps
CPU time 407.49 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:46:40 PM PST 24
Peak memory 271240 kb
Host smart-ca6b7e79-cb90-4dfc-806d-d29c8fa0bfe6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652677001 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.652677001
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.3929162987
Short name T76
Test name
Test status
Simulation time 40178400 ps
CPU time 139.83 seconds
Started Jan 21 04:31:43 PM PST 24
Finished Jan 21 04:34:04 PM PST 24
Peak memory 258056 kb
Host smart-72e55e26-507e-4b99-9908-23e744de9321
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929162987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.3929162987
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3536528170
Short name T512
Test name
Test status
Simulation time 1409248300 ps
CPU time 369.33 seconds
Started Jan 21 03:39:48 PM PST 24
Finished Jan 21 03:45:58 PM PST 24
Peak memory 264484 kb
Host smart-c2cf9d3a-7d98-443a-8c1b-139e68e75da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536528170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3536528170
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.343430973
Short name T612
Test name
Test status
Simulation time 29162000 ps
CPU time 13.77 seconds
Started Jan 21 03:39:51 PM PST 24
Finished Jan 21 03:40:11 PM PST 24
Peak memory 264280 kb
Host smart-1c16aa29-e5c8-4078-bb3c-6146f453d7c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343430973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_res
et.343430973
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.3645412735
Short name T918
Test name
Test status
Simulation time 1602815800 ps
CPU time 667.98 seconds
Started Jan 21 03:52:10 PM PST 24
Finished Jan 21 04:03:24 PM PST 24
Peak memory 281588 kb
Host smart-dacfd7a0-29f3-4258-9fc2-1192aed489e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645412735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3645412735
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1120553764
Short name T666
Test name
Test status
Simulation time 788446900 ps
CPU time 97.21 seconds
Started Jan 21 03:39:52 PM PST 24
Finished Jan 21 03:41:36 PM PST 24
Peak memory 279148 kb
Host smart-56c533d3-08c4-4900-862a-6503f707f620
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120553764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.1120553764
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.1614648665
Short name T723
Test name
Test status
Simulation time 3288305000 ps
CPU time 468.41 seconds
Started Jan 21 03:39:49 PM PST 24
Finished Jan 21 03:47:39 PM PST 24
Peak memory 313332 kb
Host smart-849d7108-f9d2-46b5-9211-8a80109bce25
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614648665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.1614648665
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.3538061477
Short name T924
Test name
Test status
Simulation time 92762300 ps
CPU time 31.01 seconds
Started Jan 21 04:03:53 PM PST 24
Finished Jan 21 04:04:26 PM PST 24
Peak memory 272648 kb
Host smart-e1a0b160-36bf-40dc-b22a-013292c62d38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538061477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.3538061477
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2409929670
Short name T390
Test name
Test status
Simulation time 45725300 ps
CPU time 32.13 seconds
Started Jan 21 03:39:50 PM PST 24
Finished Jan 21 03:40:24 PM PST 24
Peak memory 264452 kb
Host smart-5f7fee9b-2683-4b23-a38a-fbac8232e5da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409929670 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2409929670
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3940803477
Short name T460
Test name
Test status
Simulation time 3177752200 ps
CPU time 67.75 seconds
Started Jan 21 03:40:05 PM PST 24
Finished Jan 21 03:41:14 PM PST 24
Peak memory 258132 kb
Host smart-f99cc2a5-3dae-4e1d-ad01-51214f240970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940803477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3940803477
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3327853001
Short name T769
Test name
Test status
Simulation time 64826200 ps
CPU time 120.1 seconds
Started Jan 21 04:02:39 PM PST 24
Finished Jan 21 04:04:46 PM PST 24
Peak memory 274340 kb
Host smart-2e2b0481-b645-4884-8346-2c111081749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327853001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3327853001
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.482940594
Short name T978
Test name
Test status
Simulation time 9716704600 ps
CPU time 146.34 seconds
Started Jan 21 03:39:51 PM PST 24
Finished Jan 21 03:42:22 PM PST 24
Peak memory 264320 kb
Host smart-59519417-a8b6-428c-9680-0fc99918384c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482940594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_wo.482940594
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1721757826
Short name T1021
Test name
Test status
Simulation time 73489200 ps
CPU time 15.95 seconds
Started Jan 21 03:40:12 PM PST 24
Finished Jan 21 03:40:29 PM PST 24
Peak memory 273604 kb
Host smart-57d2e137-cbc6-43e8-ae1d-a8804a465bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721757826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1721757826
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.2648424920
Short name T1053
Test name
Test status
Simulation time 20431300 ps
CPU time 21.84 seconds
Started Jan 21 03:40:15 PM PST 24
Finished Jan 21 03:40:38 PM PST 24
Peak memory 264480 kb
Host smart-aedc144e-70df-4f81-b8be-151420dc1920
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648424920 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.2648424920
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3524597866
Short name T650
Test name
Test status
Simulation time 10036088900 ps
CPU time 56.64 seconds
Started Jan 21 03:40:22 PM PST 24
Finished Jan 21 03:41:26 PM PST 24
Peak memory 290428 kb
Host smart-e97c56d0-f54f-4182-99dc-3743d09da525
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524597866 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3524597866
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.331194801
Short name T319
Test name
Test status
Simulation time 5496101300 ps
CPU time 38.88 seconds
Started Jan 21 03:40:07 PM PST 24
Finished Jan 21 03:40:47 PM PST 24
Peak memory 261120 kb
Host smart-795583fd-319b-402c-b944-676dfb778d65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331194801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h
w_sec_otp.331194801
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2245842932
Short name T824
Test name
Test status
Simulation time 1093637200 ps
CPU time 149.1 seconds
Started Jan 21 03:40:11 PM PST 24
Finished Jan 21 03:42:41 PM PST 24
Peak memory 292340 kb
Host smart-bc90a098-da2b-481d-aa4e-c0359d212064
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245842932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2245842932
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.4247476455
Short name T915
Test name
Test status
Simulation time 18632645500 ps
CPU time 200.51 seconds
Started Jan 21 03:40:13 PM PST 24
Finished Jan 21 03:43:34 PM PST 24
Peak memory 288952 kb
Host smart-b5b38dfc-bf63-4329-93a9-ef6aa24b234a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247476455 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.4247476455
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.49109411
Short name T386
Test name
Test status
Simulation time 2278862700 ps
CPU time 64.81 seconds
Started Jan 21 03:40:12 PM PST 24
Finished Jan 21 03:41:18 PM PST 24
Peak memory 258184 kb
Host smart-604e32cf-4fe1-471e-b73b-bf66173d69a3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49109411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.49109411
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1083358498
Short name T466
Test name
Test status
Simulation time 16292000 ps
CPU time 13.78 seconds
Started Jan 21 03:40:14 PM PST 24
Finished Jan 21 03:40:29 PM PST 24
Peak memory 264316 kb
Host smart-7663c4cb-42cb-40ee-806c-0020362ac0fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083358498 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1083358498
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2648161621
Short name T61
Test name
Test status
Simulation time 5694760200 ps
CPU time 153.06 seconds
Started Jan 21 03:40:17 PM PST 24
Finished Jan 21 03:42:51 PM PST 24
Peak memory 260332 kb
Host smart-fa00735c-a7b0-4937-9428-8f6f04fc7abe
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648161621 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2648161621
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.543761768
Short name T129
Test name
Test status
Simulation time 140523600 ps
CPU time 111.76 seconds
Started Jan 21 03:40:13 PM PST 24
Finished Jan 21 03:42:06 PM PST 24
Peak memory 259320 kb
Host smart-44ca7a06-2f1f-467b-a633-4590dcf00f7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543761768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.543761768
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.3401532837
Short name T491
Test name
Test status
Simulation time 82442300 ps
CPU time 396.93 seconds
Started Jan 21 04:05:39 PM PST 24
Finished Jan 21 04:12:20 PM PST 24
Peak memory 264212 kb
Host smart-bde67481-e4da-4c4e-9cec-5ea48511b676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401532837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3401532837
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.3049534297
Short name T599
Test name
Test status
Simulation time 21769600 ps
CPU time 13.62 seconds
Started Jan 21 03:40:15 PM PST 24
Finished Jan 21 03:40:30 PM PST 24
Peak memory 264296 kb
Host smart-5009a86e-ed5e-4c13-93df-d6879469a5d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049534297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.3049534297
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2509724597
Short name T141
Test name
Test status
Simulation time 3453754400 ps
CPU time 623.71 seconds
Started Jan 21 03:39:59 PM PST 24
Finished Jan 21 03:50:28 PM PST 24
Peak memory 283376 kb
Host smart-eca11e9c-ef28-4fb1-b80a-5d1d75e74a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509724597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2509724597
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.1310594223
Short name T878
Test name
Test status
Simulation time 252944700 ps
CPU time 33.35 seconds
Started Jan 21 03:40:18 PM PST 24
Finished Jan 21 03:40:53 PM PST 24
Peak memory 265444 kb
Host smart-80dd8072-a020-404e-bb74-e72bebac42f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310594223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.1310594223
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.1180279536
Short name T446
Test name
Test status
Simulation time 1069500400 ps
CPU time 113.99 seconds
Started Jan 21 03:40:16 PM PST 24
Finished Jan 21 03:42:11 PM PST 24
Peak memory 280384 kb
Host smart-a1083bf0-876c-4d30-9303-341dc4bbcead
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180279536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.1180279536
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3377380066
Short name T633
Test name
Test status
Simulation time 12521791400 ps
CPU time 506.52 seconds
Started Jan 21 03:40:11 PM PST 24
Finished Jan 21 03:48:38 PM PST 24
Peak memory 311920 kb
Host smart-cacb01db-5e48-42e6-9efc-70f6bff8a5ca
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377380066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.3377380066
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.1855313038
Short name T1040
Test name
Test status
Simulation time 266404600 ps
CPU time 32.88 seconds
Started Jan 21 03:40:18 PM PST 24
Finished Jan 21 03:40:51 PM PST 24
Peak memory 272632 kb
Host smart-551f1686-d970-4793-940f-1b2b7ff8d910
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855313038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.1855313038
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2520870358
Short name T497
Test name
Test status
Simulation time 41663500 ps
CPU time 28.66 seconds
Started Jan 21 03:40:16 PM PST 24
Finished Jan 21 03:40:46 PM PST 24
Peak memory 274004 kb
Host smart-0849a7a4-944c-462f-ba07-0b5a42e48c73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520870358 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2520870358
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1422285952
Short name T367
Test name
Test status
Simulation time 4372442300 ps
CPU time 56.77 seconds
Started Jan 21 03:40:15 PM PST 24
Finished Jan 21 03:41:13 PM PST 24
Peak memory 261376 kb
Host smart-73ebe7f4-4f13-45ef-9fc4-e0eea65acb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422285952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1422285952
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.456821088
Short name T431
Test name
Test status
Simulation time 27514200 ps
CPU time 100.48 seconds
Started Jan 21 05:48:57 PM PST 24
Finished Jan 21 05:50:38 PM PST 24
Peak memory 273452 kb
Host smart-88fde823-2475-40cb-b849-2feff803dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456821088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.456821088
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.535649800
Short name T430
Test name
Test status
Simulation time 3950831600 ps
CPU time 163.05 seconds
Started Jan 21 03:40:16 PM PST 24
Finished Jan 21 03:43:00 PM PST 24
Peak memory 264340 kb
Host smart-b7530b0b-6d6b-49b3-843b-5231e9fd94db
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535649800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_wo.535649800
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.677212727
Short name T536
Test name
Test status
Simulation time 109356500 ps
CPU time 15.65 seconds
Started Jan 21 04:30:38 PM PST 24
Finished Jan 21 04:30:55 PM PST 24
Peak memory 264420 kb
Host smart-7e126bcb-b813-4ed4-930c-55df56b9000d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677212727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.677212727
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.3617672977
Short name T582
Test name
Test status
Simulation time 23116900 ps
CPU time 15.41 seconds
Started Jan 21 04:00:22 PM PST 24
Finished Jan 21 04:00:38 PM PST 24
Peak memory 273700 kb
Host smart-e0052659-5ee6-4bb6-985e-cb911581a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617672977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3617672977
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3496301843
Short name T874
Test name
Test status
Simulation time 47159800 ps
CPU time 13.58 seconds
Started Jan 21 03:40:38 PM PST 24
Finished Jan 21 03:40:53 PM PST 24
Peak memory 264304 kb
Host smart-93a8b725-5375-4788-980f-0f87e3acce27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496301843 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3496301843
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.4154916579
Short name T104
Test name
Test status
Simulation time 80144130400 ps
CPU time 771.12 seconds
Started Jan 21 03:40:29 PM PST 24
Finished Jan 21 03:53:25 PM PST 24
Peak memory 262256 kb
Host smart-9270ed3f-2197-4040-a5e3-8bced8f887d2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154916579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.4154916579
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.3895913104
Short name T856
Test name
Test status
Simulation time 5954432400 ps
CPU time 116.32 seconds
Started Jan 21 03:40:23 PM PST 24
Finished Jan 21 03:42:26 PM PST 24
Peak memory 261044 kb
Host smart-563c4e62-d50f-4aba-92eb-6fbb344c1203
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895913104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.3895913104
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.3801249670
Short name T872
Test name
Test status
Simulation time 7703896800 ps
CPU time 178.64 seconds
Started Jan 21 03:40:29 PM PST 24
Finished Jan 21 03:43:31 PM PST 24
Peak memory 291064 kb
Host smart-9e10bf93-b190-4f19-90cf-de4aeaa6af51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801249670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.3801249670
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1868186549
Short name T591
Test name
Test status
Simulation time 66568138000 ps
CPU time 193.03 seconds
Started Jan 21 04:02:34 PM PST 24
Finished Jan 21 04:05:55 PM PST 24
Peak memory 288924 kb
Host smart-393b43da-8d51-4563-921f-e98684759bd0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868186549 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1868186549
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.709091335
Short name T763
Test name
Test status
Simulation time 4287038500 ps
CPU time 71.62 seconds
Started Jan 21 03:40:32 PM PST 24
Finished Jan 21 03:41:47 PM PST 24
Peak memory 258084 kb
Host smart-4bdab3fd-e8b2-49ed-bcb5-5488a5401e0a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709091335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.709091335
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1744856466
Short name T881
Test name
Test status
Simulation time 24082400 ps
CPU time 13.89 seconds
Started Jan 21 03:40:39 PM PST 24
Finished Jan 21 03:40:53 PM PST 24
Peak memory 264316 kb
Host smart-eee537e7-6b4d-47e4-9487-fb6fa0c6c28a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744856466 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1744856466
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.605029140
Short name T579
Test name
Test status
Simulation time 14458353000 ps
CPU time 168.87 seconds
Started Jan 21 03:40:28 PM PST 24
Finished Jan 21 03:43:21 PM PST 24
Peak memory 259836 kb
Host smart-70cd5972-67c1-411b-9de3-6728e3633a41
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605029140 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.605029140
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3039024813
Short name T982
Test name
Test status
Simulation time 78219100 ps
CPU time 110.82 seconds
Started Jan 21 03:40:30 PM PST 24
Finished Jan 21 03:42:26 PM PST 24
Peak memory 258328 kb
Host smart-dc9c3e51-af14-4773-b27c-9f6ac32d9961
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039024813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3039024813
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1508872863
Short name T724
Test name
Test status
Simulation time 1846751500 ps
CPU time 450.83 seconds
Started Jan 21 03:40:22 PM PST 24
Finished Jan 21 03:48:00 PM PST 24
Peak memory 260716 kb
Host smart-f9c910b1-ab31-49b9-acf4-c002d8781912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508872863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1508872863
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.4143978051
Short name T118
Test name
Test status
Simulation time 217369800 ps
CPU time 15.36 seconds
Started Jan 21 03:40:38 PM PST 24
Finished Jan 21 03:40:54 PM PST 24
Peak memory 264380 kb
Host smart-0d36259d-0c54-4270-a19b-d9aa6f197440
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143978051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.4143978051
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1300110867
Short name T577
Test name
Test status
Simulation time 1507614400 ps
CPU time 659 seconds
Started Jan 21 03:40:21 PM PST 24
Finished Jan 21 03:51:23 PM PST 24
Peak memory 281712 kb
Host smart-7ec7fc5e-f996-4e6e-b0a4-a4152326a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300110867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1300110867
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2122872845
Short name T485
Test name
Test status
Simulation time 1301516400 ps
CPU time 35.65 seconds
Started Jan 21 03:40:37 PM PST 24
Finished Jan 21 03:41:13 PM PST 24
Peak memory 270992 kb
Host smart-4413447d-8be7-4ac2-9bb1-101686b2ad1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122872845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2122872845
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1594665456
Short name T762
Test name
Test status
Simulation time 660013100 ps
CPU time 102.36 seconds
Started Jan 21 03:40:30 PM PST 24
Finished Jan 21 03:42:17 PM PST 24
Peak memory 280532 kb
Host smart-c8fe4476-75f8-48ae-8f44-eee162cc8f9a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594665456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_ro.1594665456
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1817295972
Short name T1006
Test name
Test status
Simulation time 20051634400 ps
CPU time 460.52 seconds
Started Jan 21 03:40:27 PM PST 24
Finished Jan 21 03:48:12 PM PST 24
Peak memory 313532 kb
Host smart-bc4f103c-5cc4-4ac6-a222-8259734fed78
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817295972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.1817295972
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3388237080
Short name T205
Test name
Test status
Simulation time 64785100 ps
CPU time 34.71 seconds
Started Jan 21 03:40:37 PM PST 24
Finished Jan 21 03:41:12 PM PST 24
Peak memory 272616 kb
Host smart-a553f446-8d3f-4a72-af81-546defd35a9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388237080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3388237080
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.613905245
Short name T935
Test name
Test status
Simulation time 73315800 ps
CPU time 33.6 seconds
Started Jan 21 04:22:56 PM PST 24
Finished Jan 21 04:23:37 PM PST 24
Peak memory 274892 kb
Host smart-f400ae4e-710a-457c-8e64-c2b6746f28ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613905245 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.613905245
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.4252608432
Short name T642
Test name
Test status
Simulation time 122522000 ps
CPU time 99.61 seconds
Started Jan 21 03:40:24 PM PST 24
Finished Jan 21 03:42:10 PM PST 24
Peak memory 273916 kb
Host smart-c732ff01-98d4-494b-88e5-20ba695e2592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252608432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.4252608432
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1640463543
Short name T708
Test name
Test status
Simulation time 3433742600 ps
CPU time 122.76 seconds
Started Jan 21 03:40:29 PM PST 24
Finished Jan 21 03:42:37 PM PST 24
Peak memory 264304 kb
Host smart-a09bc0a2-d540-40b8-a2af-d93edb76ea65
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640463543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.1640463543
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.3838954276
Short name T416
Test name
Test status
Simulation time 97364500 ps
CPU time 13.93 seconds
Started Jan 21 03:41:01 PM PST 24
Finished Jan 21 03:41:16 PM PST 24
Peak memory 264424 kb
Host smart-ce675b0a-54ff-439c-b1ca-279f639f0c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838954276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
3838954276
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3854642933
Short name T787
Test name
Test status
Simulation time 53266700 ps
CPU time 15.71 seconds
Started Jan 21 03:40:55 PM PST 24
Finished Jan 21 03:41:11 PM PST 24
Peak memory 273460 kb
Host smart-44e83bce-af71-4514-96e4-52666f5bbb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854642933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3854642933
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1214513245
Short name T652
Test name
Test status
Simulation time 10034460100 ps
CPU time 58.9 seconds
Started Jan 21 03:41:01 PM PST 24
Finished Jan 21 03:42:01 PM PST 24
Peak memory 285944 kb
Host smart-273b22ab-b3af-4353-9290-bb129ddfa7a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214513245 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1214513245
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3932593744
Short name T159
Test name
Test status
Simulation time 26629800 ps
CPU time 13.66 seconds
Started Jan 21 03:40:54 PM PST 24
Finished Jan 21 03:41:08 PM PST 24
Peak memory 264148 kb
Host smart-ac483d05-fe55-4b53-a6c1-c8fc540d811a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932593744 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3932593744
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1717107120
Short name T908
Test name
Test status
Simulation time 2878144600 ps
CPU time 266.44 seconds
Started Jan 21 04:14:36 PM PST 24
Finished Jan 21 04:19:03 PM PST 24
Peak memory 259764 kb
Host smart-a62f4396-b49d-4b2d-b58b-34b64bf64d2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717107120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1717107120
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3801732720
Short name T738
Test name
Test status
Simulation time 2738738900 ps
CPU time 155.95 seconds
Started Jan 21 03:40:45 PM PST 24
Finished Jan 21 03:43:22 PM PST 24
Peak memory 293184 kb
Host smart-b8838920-5219-441c-84b4-58864d60e68e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801732720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3801732720
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.11565379
Short name T412
Test name
Test status
Simulation time 18019660100 ps
CPU time 188.83 seconds
Started Jan 21 04:00:10 PM PST 24
Finished Jan 21 04:03:21 PM PST 24
Peak memory 288912 kb
Host smart-95a73c91-51ec-47c5-a19c-d7e5f75bc903
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11565379 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.11565379
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.3243422551
Short name T211
Test name
Test status
Simulation time 3304656500 ps
CPU time 64.29 seconds
Started Jan 21 03:40:47 PM PST 24
Finished Jan 21 03:41:52 PM PST 24
Peak memory 258720 kb
Host smart-3f11c48f-3934-49ad-bef0-5ee95c3fc81a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243422551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3
243422551
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.574753063
Short name T549
Test name
Test status
Simulation time 46468200 ps
CPU time 13.42 seconds
Started Jan 21 03:40:53 PM PST 24
Finished Jan 21 03:41:07 PM PST 24
Peak memory 264376 kb
Host smart-f41fb49b-68bf-4478-a886-c381390c318d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574753063 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.574753063
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2274626093
Short name T772
Test name
Test status
Simulation time 8597637400 ps
CPU time 254.79 seconds
Started Jan 21 04:06:27 PM PST 24
Finished Jan 21 04:10:48 PM PST 24
Peak memory 271320 kb
Host smart-293b32b8-788b-4779-998d-0144444cc1ed
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274626093 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.2274626093
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.512145860
Short name T230
Test name
Test status
Simulation time 1496881400 ps
CPU time 528.79 seconds
Started Jan 21 05:23:09 PM PST 24
Finished Jan 21 05:31:59 PM PST 24
Peak memory 264332 kb
Host smart-c683b544-7da6-4442-82ee-122e97e00bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512145860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.512145860
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.3211721270
Short name T840
Test name
Test status
Simulation time 19185000 ps
CPU time 14.71 seconds
Started Jan 21 03:40:55 PM PST 24
Finished Jan 21 03:41:11 PM PST 24
Peak memory 263928 kb
Host smart-831d0e50-e8f3-4cbd-abb9-614e07f47322
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211721270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.3211721270
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.2656572246
Short name T523
Test name
Test status
Simulation time 3071112800 ps
CPU time 606.42 seconds
Started Jan 21 04:38:55 PM PST 24
Finished Jan 21 04:49:02 PM PST 24
Peak memory 280400 kb
Host smart-40ef327a-531c-4e04-9e23-5f00f53d7da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656572246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2656572246
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2025445261
Short name T282
Test name
Test status
Simulation time 132648500 ps
CPU time 38.7 seconds
Started Jan 21 03:49:08 PM PST 24
Finished Jan 21 03:49:50 PM PST 24
Peak memory 272856 kb
Host smart-97edc168-1d39-4dfd-9d6d-53cf2bfd5c80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025445261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2025445261
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.4258816290
Short name T597
Test name
Test status
Simulation time 7715948900 ps
CPU time 504.5 seconds
Started Jan 21 03:40:47 PM PST 24
Finished Jan 21 03:49:13 PM PST 24
Peak memory 307644 kb
Host smart-c19c68b6-cbf6-4b18-8da3-b03b265d4f92
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258816290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.4258816290
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2194324102
Short name T531
Test name
Test status
Simulation time 42971700 ps
CPU time 32.22 seconds
Started Jan 21 03:40:53 PM PST 24
Finished Jan 21 03:41:25 PM PST 24
Peak memory 273596 kb
Host smart-b2c948d8-9cba-4914-a24b-49358ba9bf54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194324102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2194324102
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1176158582
Short name T925
Test name
Test status
Simulation time 73828600 ps
CPU time 27.97 seconds
Started Jan 21 03:53:52 PM PST 24
Finished Jan 21 03:54:21 PM PST 24
Peak memory 264432 kb
Host smart-035d003c-1f61-4487-b5c7-53b4e4fa9f84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176158582 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1176158582
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.4198931
Short name T938
Test name
Test status
Simulation time 2760567700 ps
CPU time 218.09 seconds
Started Jan 21 03:58:39 PM PST 24
Finished Jan 21 04:02:19 PM PST 24
Peak memory 280484 kb
Host smart-93a6f559-5653-48da-bbe6-79ea86f643cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.4198931
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1620482848
Short name T777
Test name
Test status
Simulation time 2556167800 ps
CPU time 202.59 seconds
Started Jan 21 03:40:43 PM PST 24
Finished Jan 21 03:44:06 PM PST 24
Peak memory 264328 kb
Host smart-9f9560d1-9ae3-475b-8cde-33389ed94c9f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620482848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.1620482848
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1051764559
Short name T40
Test name
Test status
Simulation time 30170300 ps
CPU time 13.48 seconds
Started Jan 21 03:34:24 PM PST 24
Finished Jan 21 03:34:40 PM PST 24
Peak memory 264328 kb
Host smart-20448210-7c7f-4c97-99f5-09192a0d0498
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051764559 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1051764559
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2270500149
Short name T891
Test name
Test status
Simulation time 38550300 ps
CPU time 13.51 seconds
Started Jan 21 03:34:34 PM PST 24
Finished Jan 21 03:34:48 PM PST 24
Peak memory 264292 kb
Host smart-17a83e66-698c-4faf-bceb-f357c58d5bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270500149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
270500149
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.2512522061
Short name T968
Test name
Test status
Simulation time 22430600 ps
CPU time 13.63 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 03:34:43 PM PST 24
Peak memory 262996 kb
Host smart-0bf775d0-5021-4d6e-8d5a-fb2f1c93bd79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512522061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.2512522061
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1482420407
Short name T500
Test name
Test status
Simulation time 13241000 ps
CPU time 15.53 seconds
Started Jan 21 03:57:08 PM PST 24
Finished Jan 21 03:57:25 PM PST 24
Peak memory 273520 kb
Host smart-23936e3b-7581-429d-a322-29d28af8e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482420407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1482420407
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.545788616
Short name T153
Test name
Test status
Simulation time 118422900 ps
CPU time 103.99 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 03:36:14 PM PST 24
Peak memory 280772 kb
Host smart-9f124780-b1d6-4e7a-b610-cf67ee2505bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545788616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_derr_detect.545788616
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2871167007
Short name T158
Test name
Test status
Simulation time 1452113000 ps
CPU time 359.07 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 03:40:21 PM PST 24
Peak memory 261352 kb
Host smart-a5bf256d-fe26-48f3-8aad-c9d89a537a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871167007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2871167007
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.561987713
Short name T135
Test name
Test status
Simulation time 10096993200 ps
CPU time 2323.86 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 04:13:06 PM PST 24
Peak memory 263064 kb
Host smart-d253b9c3-bdcc-42c8-a7b4-93e325f4142f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561987713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erro
r_mp.561987713
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.274930794
Short name T1059
Test name
Test status
Simulation time 567237300 ps
CPU time 2023.25 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 04:08:09 PM PST 24
Peak memory 264028 kb
Host smart-52d18bf7-821c-447b-9435-9ef88e06e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274930794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.274930794
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.858602227
Short name T468
Test name
Test status
Simulation time 1118267900 ps
CPU time 826.23 seconds
Started Jan 21 03:34:17 PM PST 24
Finished Jan 21 03:48:08 PM PST 24
Peak memory 264344 kb
Host smart-6a3ca3a7-e360-4cbb-9569-acb540906a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858602227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.858602227
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.518971603
Short name T94
Test name
Test status
Simulation time 401242145100 ps
CPU time 2354.38 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 04:13:44 PM PST 24
Peak memory 263944 kb
Host smart-32bb7962-d018-4883-bd35-0248ede66851
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518971603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.518971603
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3517717936
Short name T290
Test name
Test status
Simulation time 22085000 ps
CPU time 27.28 seconds
Started Jan 21 03:34:18 PM PST 24
Finished Jan 21 03:34:50 PM PST 24
Peak memory 260808 kb
Host smart-80108e8c-66cc-4951-b79f-7841b9575bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517717936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3517717936
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.747769513
Short name T96
Test name
Test status
Simulation time 10022347400 ps
CPU time 102.57 seconds
Started Jan 21 03:34:40 PM PST 24
Finished Jan 21 03:36:25 PM PST 24
Peak memory 297100 kb
Host smart-66478fd5-8311-4e87-b39d-414c2d4faf71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747769513 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.747769513
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3979860649
Short name T1044
Test name
Test status
Simulation time 62532100 ps
CPU time 13.28 seconds
Started Jan 21 03:34:33 PM PST 24
Finished Jan 21 03:34:47 PM PST 24
Peak memory 264228 kb
Host smart-bebceb95-d5af-4541-8d97-c20a9e55fc2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979860649 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3979860649
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.1759928153
Short name T81
Test name
Test status
Simulation time 147704837400 ps
CPU time 1780.69 seconds
Started Jan 21 03:34:18 PM PST 24
Finished Jan 21 04:04:03 PM PST 24
Peak memory 262628 kb
Host smart-528595b2-33d6-48c0-8003-7c2adc2d3fe2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759928153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.1759928153
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.584346715
Short name T821
Test name
Test status
Simulation time 80131184400 ps
CPU time 726.09 seconds
Started Jan 21 03:34:12 PM PST 24
Finished Jan 21 03:46:26 PM PST 24
Peak memory 262712 kb
Host smart-2b33ea29-b6c8-4573-bce5-5c0894459e4a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584346715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.584346715
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.3758382182
Short name T538
Test name
Test status
Simulation time 77816336800 ps
CPU time 155.65 seconds
Started Jan 21 03:34:14 PM PST 24
Finished Jan 21 03:36:56 PM PST 24
Peak memory 261092 kb
Host smart-5604af0c-3ffd-45c5-9c41-951d43d1a989
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758382182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.3758382182
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.1642521143
Short name T264
Test name
Test status
Simulation time 55392463700 ps
CPU time 659.09 seconds
Started Jan 21 03:34:16 PM PST 24
Finished Jan 21 03:45:21 PM PST 24
Peak memory 335756 kb
Host smart-4a9451e5-638b-4eb9-8677-e6fe7c7e6b34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642521143 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.1642521143
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2807106694
Short name T498
Test name
Test status
Simulation time 1286107800 ps
CPU time 168.19 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:37:14 PM PST 24
Peak memory 292052 kb
Host smart-fe74502e-6c87-40a2-8fe9-e8d6d3d2b724
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807106694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2807106694
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.878487902
Short name T499
Test name
Test status
Simulation time 16282479400 ps
CPU time 211.59 seconds
Started Jan 21 03:34:32 PM PST 24
Finished Jan 21 03:38:05 PM PST 24
Peak memory 283012 kb
Host smart-9a1c0d9f-10a9-416c-bcc9-d020092366d8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878487902 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.878487902
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2787375125
Short name T1017
Test name
Test status
Simulation time 177924614900 ps
CPU time 491.45 seconds
Started Jan 21 03:34:19 PM PST 24
Finished Jan 21 03:42:34 PM PST 24
Peak memory 264244 kb
Host smart-fa1b02cb-dcc4-40c2-8ba7-8d9d55b1de74
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278
7375125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2787375125
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.1737265547
Short name T945
Test name
Test status
Simulation time 7052026400 ps
CPU time 59.85 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:35:26 PM PST 24
Peak memory 258112 kb
Host smart-6b0577a8-d214-439f-821f-49288403a116
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737265547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1737265547
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2138558932
Short name T949
Test name
Test status
Simulation time 53253900 ps
CPU time 13.65 seconds
Started Jan 21 03:34:41 PM PST 24
Finished Jan 21 03:34:56 PM PST 24
Peak memory 264360 kb
Host smart-12cdfce2-cbde-4d05-af91-089affe72755
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138558932 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2138558932
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.3540574865
Short name T149
Test name
Test status
Simulation time 1826585000 ps
CPU time 72.58 seconds
Started Jan 21 03:34:21 PM PST 24
Finished Jan 21 03:35:37 PM PST 24
Peak memory 258184 kb
Host smart-bf689809-be41-4c92-8301-4b4c69d31322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540574865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3540574865
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.1280403201
Short name T879
Test name
Test status
Simulation time 1210350700 ps
CPU time 175.66 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 03:37:25 PM PST 24
Peak memory 292564 kb
Host smart-a04b8389-fb51-4968-9c83-d2e124392185
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280403201 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1280403201
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.156186049
Short name T217
Test name
Test status
Simulation time 149411900 ps
CPU time 19.71 seconds
Started Jan 21 05:22:13 PM PST 24
Finished Jan 21 05:22:33 PM PST 24
Peak memory 264508 kb
Host smart-8c10f15d-62f7-4854-92c3-54070670174a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=156186049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.156186049
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4115071877
Short name T797
Test name
Test status
Simulation time 14994201700 ps
CPU time 299.61 seconds
Started Jan 21 03:34:19 PM PST 24
Finished Jan 21 03:39:24 PM PST 24
Peak memory 264292 kb
Host smart-d1b939b4-889f-49a3-b238-b62e1a1f7148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115071877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4115071877
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2115647693
Short name T862
Test name
Test status
Simulation time 93757600 ps
CPU time 15.25 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:34:44 PM PST 24
Peak memory 264396 kb
Host smart-d0507400-1bf9-42c1-b4e9-663820c26602
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115647693 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2115647693
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1588076171
Short name T15
Test name
Test status
Simulation time 17296200 ps
CPU time 14.04 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:34:40 PM PST 24
Peak memory 264456 kb
Host smart-539fd9bb-ef40-4521-ba02-e79b476173c2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588076171 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1588076171
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.773830309
Short name T161
Test name
Test status
Simulation time 62574700 ps
CPU time 13.9 seconds
Started Jan 21 03:34:20 PM PST 24
Finished Jan 21 03:34:38 PM PST 24
Peak memory 264324 kb
Host smart-391275f2-9678-4418-9ed6-d0e7eed112bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773830309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_rese
t.773830309
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2717173685
Short name T143
Test name
Test status
Simulation time 165302900 ps
CPU time 1467.72 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 03:58:49 PM PST 24
Peak memory 286000 kb
Host smart-9fd16758-7554-4a66-a608-9f18b062f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717173685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2717173685
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1267961202
Short name T963
Test name
Test status
Simulation time 572832300 ps
CPU time 103.87 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:36:13 PM PST 24
Peak memory 263868 kb
Host smart-b2f4e1bc-90a1-42c2-8bb7-59453b530cbd
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267961202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1267961202
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.2311109200
Short name T338
Test name
Test status
Simulation time 821682700 ps
CPU time 32.03 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:34:58 PM PST 24
Peak memory 277776 kb
Host smart-ce88c931-86bf-4d1f-a665-d77812ff6980
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311109200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.2311109200
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2859547510
Short name T125
Test name
Test status
Simulation time 258412100 ps
CPU time 37.57 seconds
Started Jan 21 03:34:22 PM PST 24
Finished Jan 21 03:35:03 PM PST 24
Peak memory 272672 kb
Host smart-2ab71bbc-9484-4d41-b641-f6476f02dca1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859547510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2859547510
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.665065434
Short name T804
Test name
Test status
Simulation time 67924200 ps
CPU time 21.44 seconds
Started Jan 21 03:34:20 PM PST 24
Finished Jan 21 03:34:46 PM PST 24
Peak memory 264464 kb
Host smart-b86d6e6c-7872-4a2f-afcc-115a17cdd0b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665065434 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.665065434
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2160584871
Short name T623
Test name
Test status
Simulation time 23393200 ps
CPU time 23.03 seconds
Started Jan 21 03:34:32 PM PST 24
Finished Jan 21 03:34:57 PM PST 24
Peak memory 264484 kb
Host smart-deab3fbd-084d-43bb-8b2e-ae3deb1b6cfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160584871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2160584871
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.19304209
Short name T583
Test name
Test status
Simulation time 1606431500 ps
CPU time 92.53 seconds
Started Jan 21 03:34:23 PM PST 24
Finished Jan 21 03:35:59 PM PST 24
Peak memory 280560 kb
Host smart-c0ffa85a-0be2-4518-b830-21e7fa57bf15
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19304209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_ro.19304209
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.95925143
Short name T844
Test name
Test status
Simulation time 575190800 ps
CPU time 136.48 seconds
Started Jan 21 03:34:28 PM PST 24
Finished Jan 21 03:36:46 PM PST 24
Peak memory 280816 kb
Host smart-1e490f44-6d4a-4103-b844-8e36f0fbb6f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
95925143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.95925143
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.2656101772
Short name T249
Test name
Test status
Simulation time 1458724900 ps
CPU time 135.49 seconds
Started Jan 21 03:34:31 PM PST 24
Finished Jan 21 03:36:48 PM PST 24
Peak memory 280880 kb
Host smart-84aa9c03-b378-4da2-b1fe-c557fb4d7aae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656101772 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2656101772
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1870565709
Short name T53
Test name
Test status
Simulation time 7936299100 ps
CPU time 519.19 seconds
Started Jan 21 03:34:31 PM PST 24
Finished Jan 21 03:43:12 PM PST 24
Peak memory 312308 kb
Host smart-2138fc22-0e2a-49de-b211-e3d3a26af45d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870565709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.1870565709
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2450714634
Short name T69
Test name
Test status
Simulation time 43732138600 ps
CPU time 746.6 seconds
Started Jan 21 03:34:39 PM PST 24
Finished Jan 21 03:47:08 PM PST 24
Peak memory 337656 kb
Host smart-6a32a0fb-a39d-4d7c-8942-484e1e435aa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450714634 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.2450714634
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.3504796600
Short name T728
Test name
Test status
Simulation time 85125400 ps
CPU time 33.39 seconds
Started Jan 21 03:34:19 PM PST 24
Finished Jan 21 03:34:57 PM PST 24
Peak memory 271016 kb
Host smart-f9aa96e3-fb29-43c0-a11b-861a97f88193
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504796600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.3504796600
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.3572357557
Short name T603
Test name
Test status
Simulation time 49628300 ps
CPU time 31.51 seconds
Started Jan 21 03:34:39 PM PST 24
Finished Jan 21 03:35:14 PM PST 24
Peak memory 270960 kb
Host smart-683d471c-0b57-4937-abe7-e91d4148e7f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572357557 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.3572357557
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.400186148
Short name T1011
Test name
Test status
Simulation time 3141521100 ps
CPU time 453.81 seconds
Started Jan 21 03:34:17 PM PST 24
Finished Jan 21 03:41:56 PM PST 24
Peak memory 310604 kb
Host smart-f697ca9a-1332-475e-8d3e-95a31b2c4317
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400186148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_se
rr.400186148
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1896606313
Short name T379
Test name
Test status
Simulation time 2819441600 ps
CPU time 68.1 seconds
Started Jan 21 03:34:32 PM PST 24
Finished Jan 21 03:35:42 PM PST 24
Peak memory 262072 kb
Host smart-80b614c9-4883-40de-8fc8-79356f93efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896606313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1896606313
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3550056749
Short name T629
Test name
Test status
Simulation time 11528268600 ps
CPU time 72.24 seconds
Started Jan 21 03:34:25 PM PST 24
Finished Jan 21 03:35:39 PM PST 24
Peak memory 264396 kb
Host smart-60b2c520-4eb3-4592-8654-0e34d5b5725a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550056749 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3550056749
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3920812538
Short name T766
Test name
Test status
Simulation time 767727000 ps
CPU time 53.08 seconds
Started Jan 21 03:34:19 PM PST 24
Finished Jan 21 03:35:16 PM PST 24
Peak memory 272524 kb
Host smart-d40a7098-d9fe-4888-8233-8c3abfec0674
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920812538 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3920812538
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2660520284
Short name T985
Test name
Test status
Simulation time 49081500 ps
CPU time 98.42 seconds
Started Jan 21 03:34:15 PM PST 24
Finished Jan 21 03:36:00 PM PST 24
Peak memory 273544 kb
Host smart-cc7d040a-f7fe-4333-9072-8674c6102c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660520284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2660520284
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.929806884
Short name T959
Test name
Test status
Simulation time 22421000 ps
CPU time 23.87 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:34:53 PM PST 24
Peak memory 257088 kb
Host smart-e8e879c9-4ecb-41cf-bd0a-5221f4c91a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929806884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.929806884
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.3982581344
Short name T967
Test name
Test status
Simulation time 173335500 ps
CPU time 875.84 seconds
Started Jan 21 03:34:22 PM PST 24
Finished Jan 21 03:49:01 PM PST 24
Peak memory 281844 kb
Host smart-6d6f08bd-fc28-41c2-80e2-1020687ab77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982581344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.3982581344
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3583479539
Short name T1003
Test name
Test status
Simulation time 28072400 ps
CPU time 26.29 seconds
Started Jan 21 03:34:19 PM PST 24
Finished Jan 21 03:34:51 PM PST 24
Peak memory 258032 kb
Host smart-146fd4a9-bfaa-465b-a13c-0f90c9609735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583479539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3583479539
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.942943598
Short name T675
Test name
Test status
Simulation time 1989804700 ps
CPU time 161.28 seconds
Started Jan 21 03:59:21 PM PST 24
Finished Jan 21 04:02:04 PM PST 24
Peak memory 264520 kb
Host smart-1b59137a-344c-4595-a46a-d224165b55f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942943598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_wo.942943598
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.4251874678
Short name T615
Test name
Test status
Simulation time 270848300 ps
CPU time 13.85 seconds
Started Jan 21 03:41:17 PM PST 24
Finished Jan 21 03:41:31 PM PST 24
Peak memory 263536 kb
Host smart-fc7c7611-36fb-4fd7-a13b-afdafa81089c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251874678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
4251874678
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.22213179
Short name T813
Test name
Test status
Simulation time 47217600 ps
CPU time 15.73 seconds
Started Jan 21 03:41:12 PM PST 24
Finished Jan 21 03:41:29 PM PST 24
Peak memory 273592 kb
Host smart-c3152135-9311-4a80-8aea-da6651cbd4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22213179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.22213179
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.4293416190
Short name T440
Test name
Test status
Simulation time 13050400 ps
CPU time 22.47 seconds
Started Jan 21 03:41:14 PM PST 24
Finished Jan 21 03:41:37 PM PST 24
Peak memory 264464 kb
Host smart-f1a5ad79-1082-4e8a-8d36-0d64fa7eec6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293416190 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.4293416190
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1664064297
Short name T189
Test name
Test status
Simulation time 4320417600 ps
CPU time 188.8 seconds
Started Jan 21 04:41:47 PM PST 24
Finished Jan 21 04:44:57 PM PST 24
Peak memory 261080 kb
Host smart-7a2a19a9-ed3c-474f-90fa-e9f48ab4ac2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664064297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.1664064297
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.1736511731
Short name T27
Test name
Test status
Simulation time 9084732700 ps
CPU time 165.17 seconds
Started Jan 21 03:40:59 PM PST 24
Finished Jan 21 03:43:45 PM PST 24
Peak memory 291092 kb
Host smart-97fa86f5-6d63-4d79-88c2-2acee121ce4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736511731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.1736511731
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3533494158
Short name T677
Test name
Test status
Simulation time 27797364200 ps
CPU time 195.85 seconds
Started Jan 21 04:00:20 PM PST 24
Finished Jan 21 04:03:38 PM PST 24
Peak memory 282992 kb
Host smart-8330490f-254b-42d6-a430-154ddb5ae5ce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533494158 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3533494158
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1152714200
Short name T757
Test name
Test status
Simulation time 73204100 ps
CPU time 110.06 seconds
Started Jan 21 03:40:59 PM PST 24
Finished Jan 21 03:42:50 PM PST 24
Peak memory 258088 kb
Host smart-cb4111cc-72e7-45bb-9eae-8d5a1eed09b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152714200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1152714200
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3538047491
Short name T482
Test name
Test status
Simulation time 46519900 ps
CPU time 14.15 seconds
Started Jan 21 04:05:35 PM PST 24
Finished Jan 21 04:05:56 PM PST 24
Peak memory 264336 kb
Host smart-0a52dec1-e7aa-473a-8209-632569b23562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538047491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.3538047491
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3387648136
Short name T60
Test name
Test status
Simulation time 186979700 ps
CPU time 35.04 seconds
Started Jan 21 03:41:16 PM PST 24
Finished Jan 21 03:41:52 PM PST 24
Peak memory 264488 kb
Host smart-22d3d78f-5504-4cf9-af0e-caf627da9447
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387648136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3387648136
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1186003560
Short name T551
Test name
Test status
Simulation time 6184902700 ps
CPU time 72.17 seconds
Started Jan 21 03:41:17 PM PST 24
Finished Jan 21 03:42:30 PM PST 24
Peak memory 258036 kb
Host smart-f7b03fb3-d86d-459d-a67d-c0b99c3dfc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186003560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1186003560
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1319046183
Short name T753
Test name
Test status
Simulation time 43358800 ps
CPU time 99.19 seconds
Started Jan 21 03:41:00 PM PST 24
Finished Jan 21 03:42:40 PM PST 24
Peak memory 273628 kb
Host smart-c6ce49c2-676d-437c-b4e0-e567c4dc7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319046183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1319046183
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.1079596026
Short name T691
Test name
Test status
Simulation time 77958000 ps
CPU time 13.59 seconds
Started Jan 21 03:41:18 PM PST 24
Finished Jan 21 03:41:32 PM PST 24
Peak memory 264160 kb
Host smart-f99a980b-e8bf-4be1-b83b-ecdb02aa5750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079596026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
1079596026
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2810324304
Short name T418
Test name
Test status
Simulation time 51964000 ps
CPU time 16.59 seconds
Started Jan 21 05:15:22 PM PST 24
Finished Jan 21 05:15:40 PM PST 24
Peak memory 273616 kb
Host smart-eb8b9bbd-cd1b-43c4-82f4-01b2f296365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810324304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2810324304
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.9156095
Short name T858
Test name
Test status
Simulation time 4525591900 ps
CPU time 182.25 seconds
Started Jan 21 04:04:42 PM PST 24
Finished Jan 21 04:07:45 PM PST 24
Peak memory 261008 kb
Host smart-4d8023de-a64a-41b2-9691-5a05a1fa0d6c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9156095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_
sec_otp.9156095
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.818890901
Short name T717
Test name
Test status
Simulation time 1192772100 ps
CPU time 156.78 seconds
Started Jan 21 03:41:12 PM PST 24
Finished Jan 21 03:43:50 PM PST 24
Peak memory 288992 kb
Host smart-27e8cc8d-f4d1-4abe-9f9f-fc27a86217fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818890901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_intr_rd.818890901
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2837217026
Short name T517
Test name
Test status
Simulation time 8847759000 ps
CPU time 188.51 seconds
Started Jan 21 03:41:13 PM PST 24
Finished Jan 21 03:44:23 PM PST 24
Peak memory 283020 kb
Host smart-4bc772fa-b086-4340-bb7a-808ed7dd3e6b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837217026 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2837217026
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.2655289041
Short name T854
Test name
Test status
Simulation time 61738600 ps
CPU time 13.41 seconds
Started Jan 21 03:41:13 PM PST 24
Finished Jan 21 03:41:27 PM PST 24
Peak memory 264332 kb
Host smart-a2ad0653-1116-4899-bf4e-0b71c5a23d2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655289041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.2655289041
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3523390055
Short name T920
Test name
Test status
Simulation time 1475782700 ps
CPU time 37.26 seconds
Started Jan 21 05:16:54 PM PST 24
Finished Jan 21 05:17:33 PM PST 24
Peak memory 264524 kb
Host smart-2fcb6bee-30bf-4b95-a804-2fcdce695251
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523390055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3523390055
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3380306184
Short name T653
Test name
Test status
Simulation time 82720100 ps
CPU time 35.92 seconds
Started Jan 21 04:27:23 PM PST 24
Finished Jan 21 04:28:00 PM PST 24
Peak memory 272684 kb
Host smart-5d483a57-cc65-473f-993d-a3d3c27523ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380306184 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3380306184
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.1369887529
Short name T899
Test name
Test status
Simulation time 5119536700 ps
CPU time 68.35 seconds
Started Jan 21 04:03:52 PM PST 24
Finished Jan 21 04:05:03 PM PST 24
Peak memory 258116 kb
Host smart-f668e763-a447-41f3-bf0c-6dc2b98d8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369887529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.1369887529
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.946426182
Short name T417
Test name
Test status
Simulation time 140207900 ps
CPU time 14.07 seconds
Started Jan 21 03:41:31 PM PST 24
Finished Jan 21 03:41:46 PM PST 24
Peak memory 264404 kb
Host smart-6ff44c8d-568e-4b12-8d99-393393529f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946426182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.946426182
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3067653987
Short name T519
Test name
Test status
Simulation time 49312300 ps
CPU time 15.66 seconds
Started Jan 21 03:41:28 PM PST 24
Finished Jan 21 03:41:44 PM PST 24
Peak memory 282840 kb
Host smart-7b2b76e6-0bf2-4fc4-acd6-180982781df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067653987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3067653987
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.1106022090
Short name T99
Test name
Test status
Simulation time 10603400 ps
CPU time 22.06 seconds
Started Jan 21 03:41:27 PM PST 24
Finished Jan 21 03:41:50 PM PST 24
Peak memory 264396 kb
Host smart-12e7203a-4373-4a07-a0a3-2ff57c68db58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106022090 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.1106022090
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.4155403215
Short name T768
Test name
Test status
Simulation time 8662755500 ps
CPU time 172.15 seconds
Started Jan 21 03:41:19 PM PST 24
Finished Jan 21 03:44:12 PM PST 24
Peak memory 260860 kb
Host smart-19377bd7-53ec-4447-a0a2-27dcb9d23690
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155403215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.4155403215
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3932667924
Short name T1009
Test name
Test status
Simulation time 2209181900 ps
CPU time 158.42 seconds
Started Jan 21 03:41:18 PM PST 24
Finished Jan 21 03:43:57 PM PST 24
Peak memory 292312 kb
Host smart-e991b83a-a536-4050-b38b-c0e7400ef352
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932667924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3932667924
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4165247920
Short name T718
Test name
Test status
Simulation time 34118633400 ps
CPU time 206.52 seconds
Started Jan 21 03:41:27 PM PST 24
Finished Jan 21 03:44:54 PM PST 24
Peak memory 282920 kb
Host smart-b421057d-d899-4a01-951e-a1a531e84dcc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165247920 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.4165247920
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2530617661
Short name T75
Test name
Test status
Simulation time 67614800 ps
CPU time 130.73 seconds
Started Jan 21 03:41:19 PM PST 24
Finished Jan 21 03:43:31 PM PST 24
Peak memory 258200 kb
Host smart-f673cf2d-30ff-493c-9858-41813d5073dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530617661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2530617661
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3349452099
Short name T888
Test name
Test status
Simulation time 39417900 ps
CPU time 13.62 seconds
Started Jan 21 03:41:28 PM PST 24
Finished Jan 21 03:41:42 PM PST 24
Peak memory 264320 kb
Host smart-1a94f3e9-b4a8-490e-a6c8-9ad4390306a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349452099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3349452099
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.216937011
Short name T322
Test name
Test status
Simulation time 183274600 ps
CPU time 34.9 seconds
Started Jan 21 03:41:31 PM PST 24
Finished Jan 21 03:42:07 PM PST 24
Peak memory 265432 kb
Host smart-6fbe9c3c-6b47-4676-b059-83bb9f091e49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216937011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_rw_evict.216937011
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.1874931114
Short name T999
Test name
Test status
Simulation time 34916600 ps
CPU time 30.99 seconds
Started Jan 21 03:41:30 PM PST 24
Finished Jan 21 03:42:02 PM PST 24
Peak memory 264376 kb
Host smart-47bd9382-77d1-43b6-9bc1-e168ee08a913
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874931114 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.1874931114
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1645727928
Short name T366
Test name
Test status
Simulation time 1932192300 ps
CPU time 70.83 seconds
Started Jan 21 03:41:28 PM PST 24
Finished Jan 21 03:42:40 PM PST 24
Peak memory 261552 kb
Host smart-689b90cd-5ac0-49d6-a65d-f06d103772b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645727928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1645727928
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.2126478702
Short name T124
Test name
Test status
Simulation time 102623300 ps
CPU time 171.82 seconds
Started Jan 21 03:41:18 PM PST 24
Finished Jan 21 03:44:11 PM PST 24
Peak memory 276956 kb
Host smart-0ab1d144-1daa-4099-a420-e9d8143152d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126478702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2126478702
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.2093700744
Short name T791
Test name
Test status
Simulation time 46904400 ps
CPU time 14.18 seconds
Started Jan 21 03:41:36 PM PST 24
Finished Jan 21 03:41:50 PM PST 24
Peak memory 264364 kb
Host smart-a0319274-1f62-446e-9cfd-e73b96a0862d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093700744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
2093700744
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.1640937095
Short name T354
Test name
Test status
Simulation time 37614700 ps
CPU time 21.99 seconds
Started Jan 21 03:41:40 PM PST 24
Finished Jan 21 03:42:03 PM PST 24
Peak memory 264420 kb
Host smart-2e76e37b-b56b-46d3-8ccb-b0bd57336615
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640937095 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.1640937095
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2156230744
Short name T761
Test name
Test status
Simulation time 10199466300 ps
CPU time 217.03 seconds
Started Jan 21 03:41:28 PM PST 24
Finished Jan 21 03:45:05 PM PST 24
Peak memory 261440 kb
Host smart-ea6e4ed5-d3c1-4216-9136-ea08b1a0aaa6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156230744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.2156230744
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.1643369547
Short name T9
Test name
Test status
Simulation time 4475236100 ps
CPU time 159.86 seconds
Started Jan 21 03:41:32 PM PST 24
Finished Jan 21 03:44:13 PM PST 24
Peak memory 292272 kb
Host smart-8d9a8172-a30e-434a-a36e-4db1f955d286
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643369547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.1643369547
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.664929471
Short name T614
Test name
Test status
Simulation time 46322560500 ps
CPU time 263.57 seconds
Started Jan 21 03:41:32 PM PST 24
Finished Jan 21 03:45:56 PM PST 24
Peak memory 283024 kb
Host smart-f7255eac-7f89-498e-b81b-dbf8144baa9d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664929471 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.664929471
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3943832237
Short name T160
Test name
Test status
Simulation time 157039500 ps
CPU time 13.56 seconds
Started Jan 21 03:41:32 PM PST 24
Finished Jan 21 03:41:46 PM PST 24
Peak memory 264296 kb
Host smart-bf440eee-d83b-47d6-9140-29dbaee3ee73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943832237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3943832237
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.3504147374
Short name T1031
Test name
Test status
Simulation time 57654700 ps
CPU time 33.23 seconds
Started Jan 21 05:39:27 PM PST 24
Finished Jan 21 05:40:06 PM PST 24
Peak memory 265496 kb
Host smart-7943db55-429e-4e92-a297-2e22657b5b8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504147374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.3504147374
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.4010471118
Short name T397
Test name
Test status
Simulation time 105704600 ps
CPU time 32.09 seconds
Started Jan 21 03:41:28 PM PST 24
Finished Jan 21 03:42:01 PM PST 24
Peak memory 274716 kb
Host smart-d6542c23-45cb-4fca-b39a-d1c64358ba43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010471118 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.4010471118
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1955176815
Short name T381
Test name
Test status
Simulation time 1741406300 ps
CPU time 65.77 seconds
Started Jan 21 03:41:34 PM PST 24
Finished Jan 21 03:42:41 PM PST 24
Peak memory 258104 kb
Host smart-8b7daa4a-0559-4ca7-9ae3-986031aeaafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955176815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1955176815
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.2516735711
Short name T456
Test name
Test status
Simulation time 22850300 ps
CPU time 76.35 seconds
Started Jan 21 03:41:31 PM PST 24
Finished Jan 21 03:42:48 PM PST 24
Peak memory 264252 kb
Host smart-d5055f72-6e8b-4ab2-8a7f-5393b97a4f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516735711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2516735711
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.834619760
Short name T414
Test name
Test status
Simulation time 95997200 ps
CPU time 14 seconds
Started Jan 21 03:41:47 PM PST 24
Finished Jan 21 03:42:01 PM PST 24
Peak memory 264432 kb
Host smart-2d643403-1708-4173-bbea-171747ee4291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834619760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.834619760
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2318093766
Short name T1056
Test name
Test status
Simulation time 13174200 ps
CPU time 13.4 seconds
Started Jan 21 03:41:46 PM PST 24
Finished Jan 21 03:42:00 PM PST 24
Peak memory 282924 kb
Host smart-f94d698d-3993-4e7b-81d0-947d0fc44211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318093766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2318093766
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1249802596
Short name T39
Test name
Test status
Simulation time 59018210500 ps
CPU time 135.48 seconds
Started Jan 21 03:58:36 PM PST 24
Finished Jan 21 04:00:53 PM PST 24
Peak memory 261188 kb
Host smart-ed85b465-0d5f-4704-8c08-98195d24cc70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249802596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1249802596
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.897051471
Short name T928
Test name
Test status
Simulation time 8292323600 ps
CPU time 166.18 seconds
Started Jan 21 03:41:37 PM PST 24
Finished Jan 21 03:44:24 PM PST 24
Peak memory 292208 kb
Host smart-b134f792-a40f-4be9-91b3-f05b55eb9c48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897051471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.897051471
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.4292760984
Short name T958
Test name
Test status
Simulation time 35273740400 ps
CPU time 192.58 seconds
Started Jan 21 03:41:37 PM PST 24
Finished Jan 21 03:44:50 PM PST 24
Peak memory 283044 kb
Host smart-cae0cde9-6775-4360-9b2d-202adee5bc44
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292760984 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.4292760984
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2602685274
Short name T852
Test name
Test status
Simulation time 63306800 ps
CPU time 13.57 seconds
Started Jan 21 03:41:35 PM PST 24
Finished Jan 21 03:41:49 PM PST 24
Peak memory 264348 kb
Host smart-354b5dab-4da7-4544-89ec-820eead791cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602685274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.2602685274
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.4200365234
Short name T955
Test name
Test status
Simulation time 34244300 ps
CPU time 29.25 seconds
Started Jan 21 03:41:35 PM PST 24
Finished Jan 21 03:42:05 PM PST 24
Peak memory 264492 kb
Host smart-72de01f7-80ef-4321-b19f-cd4a9acc1ce3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200365234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.4200365234
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3543944852
Short name T574
Test name
Test status
Simulation time 53240300 ps
CPU time 32.05 seconds
Started Jan 21 03:41:47 PM PST 24
Finished Jan 21 03:42:19 PM PST 24
Peak memory 275160 kb
Host smart-3a1952e9-782a-4c93-b872-7d029d6e65b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543944852 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3543944852
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3801499931
Short name T470
Test name
Test status
Simulation time 8690876700 ps
CPU time 73.63 seconds
Started Jan 21 03:41:50 PM PST 24
Finished Jan 21 03:43:04 PM PST 24
Peak memory 258052 kb
Host smart-66e655b6-de5f-4e71-900b-3a45c95d72be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801499931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3801499931
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3613686958
Short name T859
Test name
Test status
Simulation time 119181900 ps
CPU time 123.23 seconds
Started Jan 21 03:41:38 PM PST 24
Finished Jan 21 03:43:42 PM PST 24
Peak memory 273972 kb
Host smart-1dd89bd2-d2ad-4928-9e84-f0853b104505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613686958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3613686958
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.432316395
Short name T452
Test name
Test status
Simulation time 77231000 ps
CPU time 13.76 seconds
Started Jan 21 03:41:53 PM PST 24
Finished Jan 21 03:42:08 PM PST 24
Peak memory 264056 kb
Host smart-84b8120c-9e16-4cde-9163-6a77aecb1fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432316395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.432316395
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1860180176
Short name T676
Test name
Test status
Simulation time 52714000 ps
CPU time 15.7 seconds
Started Jan 21 03:41:58 PM PST 24
Finished Jan 21 03:42:14 PM PST 24
Peak memory 273644 kb
Host smart-8f8b052a-1c95-4332-8a6b-06170966164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860180176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1860180176
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1197385287
Short name T29
Test name
Test status
Simulation time 18129600 ps
CPU time 22.15 seconds
Started Jan 21 03:41:54 PM PST 24
Finished Jan 21 03:42:17 PM PST 24
Peak memory 264356 kb
Host smart-dab4f70d-b23c-437f-a4c6-d5becfc0660a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197385287 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1197385287
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1408584930
Short name T622
Test name
Test status
Simulation time 5933306200 ps
CPU time 205.53 seconds
Started Jan 21 03:41:50 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 260968 kb
Host smart-cd28e54a-fbd4-480a-bdcb-29c1597e9dce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408584930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1408584930
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.610505278
Short name T122
Test name
Test status
Simulation time 2450003900 ps
CPU time 165.27 seconds
Started Jan 21 03:41:47 PM PST 24
Finished Jan 21 03:44:33 PM PST 24
Peak memory 290496 kb
Host smart-39d9be46-5d9b-4054-bd8e-80f85e94a429
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610505278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.610505278
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1337227797
Short name T1041
Test name
Test status
Simulation time 32997667200 ps
CPU time 230.72 seconds
Started Jan 21 03:41:47 PM PST 24
Finished Jan 21 03:45:38 PM PST 24
Peak memory 282928 kb
Host smart-db2cd577-6908-4ede-a004-1073b58992c5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337227797 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1337227797
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1433249191
Short name T13
Test name
Test status
Simulation time 39944100 ps
CPU time 132.17 seconds
Started Jan 21 03:41:46 PM PST 24
Finished Jan 21 03:43:59 PM PST 24
Peak memory 258148 kb
Host smart-20c88f4d-33e2-4399-af62-bb092a4c25dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433249191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1433249191
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2605411129
Short name T1010
Test name
Test status
Simulation time 62508400 ps
CPU time 13.47 seconds
Started Jan 21 04:02:11 PM PST 24
Finished Jan 21 04:02:26 PM PST 24
Peak memory 264364 kb
Host smart-9722a7fc-699d-4790-b9e4-b2bd9a7eccca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605411129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.2605411129
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.1405682656
Short name T1016
Test name
Test status
Simulation time 42854500 ps
CPU time 31.36 seconds
Started Jan 21 04:05:22 PM PST 24
Finished Jan 21 04:06:00 PM PST 24
Peak memory 270968 kb
Host smart-1b614b0c-f8e0-420d-80e3-5ee9c884dbcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405682656 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.1405682656
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1295670398
Short name T116
Test name
Test status
Simulation time 1834262100 ps
CPU time 59.63 seconds
Started Jan 21 04:36:23 PM PST 24
Finished Jan 21 04:37:24 PM PST 24
Peak memory 262724 kb
Host smart-93dc65d9-c1d8-409f-a94d-80f70497c520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295670398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1295670398
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3221617280
Short name T663
Test name
Test status
Simulation time 40057500 ps
CPU time 171.45 seconds
Started Jan 21 03:41:48 PM PST 24
Finished Jan 21 03:44:40 PM PST 24
Peak memory 274572 kb
Host smart-6ef3bd9f-5812-4133-81c1-7300363dab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221617280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3221617280
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.3092986357
Short name T814
Test name
Test status
Simulation time 47000100 ps
CPU time 14.02 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:42:18 PM PST 24
Peak memory 264508 kb
Host smart-0c7a4ec5-7e02-4a0b-85fa-ba1c278a4088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092986357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
3092986357
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.752005018
Short name T323
Test name
Test status
Simulation time 16842300 ps
CPU time 13.31 seconds
Started Jan 21 03:42:03 PM PST 24
Finished Jan 21 03:42:18 PM PST 24
Peak memory 273536 kb
Host smart-e6958fbe-1e62-47a1-953a-56925d6832ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752005018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.752005018
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.1993798790
Short name T559
Test name
Test status
Simulation time 17262000 ps
CPU time 22.55 seconds
Started Jan 21 03:42:04 PM PST 24
Finished Jan 21 03:42:27 PM PST 24
Peak memory 264300 kb
Host smart-66ec10a5-eb54-4a30-8ec2-b55c17372f3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993798790 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.1993798790
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.643700280
Short name T628
Test name
Test status
Simulation time 12102366000 ps
CPU time 108.94 seconds
Started Jan 21 03:41:54 PM PST 24
Finished Jan 21 03:43:44 PM PST 24
Peak memory 260952 kb
Host smart-7773f1af-bea5-44f1-b8b1-27e26600cdf9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643700280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.643700280
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3857547954
Short name T964
Test name
Test status
Simulation time 1395868200 ps
CPU time 177.2 seconds
Started Jan 21 03:41:52 PM PST 24
Finished Jan 21 03:44:50 PM PST 24
Peak memory 288956 kb
Host smart-27497ebf-98bc-49f2-bbe8-e03d685d9f1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857547954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3857547954
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1832989238
Short name T331
Test name
Test status
Simulation time 28242981700 ps
CPU time 227.65 seconds
Started Jan 21 03:41:55 PM PST 24
Finished Jan 21 03:45:43 PM PST 24
Peak memory 282960 kb
Host smart-2ae2dcb7-4f72-4abc-994b-7eca5d0d9c82
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832989238 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1832989238
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.845804411
Short name T563
Test name
Test status
Simulation time 72782600 ps
CPU time 13.84 seconds
Started Jan 21 03:41:52 PM PST 24
Finished Jan 21 03:42:06 PM PST 24
Peak memory 264352 kb
Host smart-a0fa9150-f402-4b79-b325-e335b740df63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845804411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_res
et.845804411
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.3659917946
Short name T593
Test name
Test status
Simulation time 32823300 ps
CPU time 28.43 seconds
Started Jan 21 04:01:05 PM PST 24
Finished Jan 21 04:01:34 PM PST 24
Peak memory 273916 kb
Host smart-628bdcee-8c2c-4fa2-8f76-87a3e9b78bc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659917946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.3659917946
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1125203868
Short name T564
Test name
Test status
Simulation time 74223900 ps
CPU time 29.28 seconds
Started Jan 21 04:02:29 PM PST 24
Finished Jan 21 04:03:07 PM PST 24
Peak memory 274036 kb
Host smart-a54db379-52a7-4cb4-98ce-dbb8c27453a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125203868 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1125203868
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3118146536
Short name T570
Test name
Test status
Simulation time 185346700 ps
CPU time 169.29 seconds
Started Jan 21 04:08:20 PM PST 24
Finished Jan 21 04:11:13 PM PST 24
Peak memory 277296 kb
Host smart-40f66682-ee6d-41a5-ae2b-8998e47bcaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118146536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3118146536
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.404388416
Short name T826
Test name
Test status
Simulation time 139211300 ps
CPU time 13.8 seconds
Started Jan 21 03:42:04 PM PST 24
Finished Jan 21 03:42:18 PM PST 24
Peak memory 264192 kb
Host smart-67f1578e-a61e-4be9-b6f5-3e36301908dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404388416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.404388416
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.212784207
Short name T860
Test name
Test status
Simulation time 42492000 ps
CPU time 15.72 seconds
Started Jan 21 03:42:03 PM PST 24
Finished Jan 21 03:42:20 PM PST 24
Peak memory 273548 kb
Host smart-d13d7e70-3f8b-4b5c-961e-e681fea6c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212784207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.212784207
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2595677585
Short name T846
Test name
Test status
Simulation time 2070916900 ps
CPU time 45.47 seconds
Started Jan 21 03:42:01 PM PST 24
Finished Jan 21 03:42:48 PM PST 24
Peak memory 260916 kb
Host smart-1be65614-fb67-4c98-a2a0-f17b6b0981a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595677585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.2595677585
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3165677312
Short name T409
Test name
Test status
Simulation time 1263939600 ps
CPU time 168.67 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:44:51 PM PST 24
Peak memory 291320 kb
Host smart-8ed02151-37e4-4d6f-a893-50c4e70cd137
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165677312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3165677312
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3402220466
Short name T507
Test name
Test status
Simulation time 44191463500 ps
CPU time 285.13 seconds
Started Jan 21 03:42:03 PM PST 24
Finished Jan 21 03:46:49 PM PST 24
Peak memory 282968 kb
Host smart-94c03d0d-57a9-4e2e-a181-c7b1e2a4ff65
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402220466 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3402220466
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.3702329226
Short name T836
Test name
Test status
Simulation time 39718100 ps
CPU time 110.75 seconds
Started Jan 21 03:42:03 PM PST 24
Finished Jan 21 03:43:55 PM PST 24
Peak memory 258344 kb
Host smart-4f382cc6-cbfc-4c5b-81c8-75f6fb8c0035
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702329226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.3702329226
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1374996762
Short name T370
Test name
Test status
Simulation time 68469300 ps
CPU time 13.63 seconds
Started Jan 21 04:15:15 PM PST 24
Finished Jan 21 04:15:29 PM PST 24
Peak memory 264292 kb
Host smart-8d1643f7-3fb6-43f4-8aff-ea7abb0aa82e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374996762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.1374996762
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3939261545
Short name T913
Test name
Test status
Simulation time 183636700 ps
CPU time 32.45 seconds
Started Jan 21 03:42:01 PM PST 24
Finished Jan 21 03:42:35 PM PST 24
Peak memory 272604 kb
Host smart-9536bea3-ce93-408b-bfe4-fde9cd6c7dd2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939261545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3939261545
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2267918632
Short name T402
Test name
Test status
Simulation time 27212700 ps
CPU time 28.38 seconds
Started Jan 21 03:42:04 PM PST 24
Finished Jan 21 03:42:33 PM PST 24
Peak memory 272664 kb
Host smart-4681375f-4724-4015-9c09-6aa59b1128de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267918632 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2267918632
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.420269841
Short name T363
Test name
Test status
Simulation time 1522293700 ps
CPU time 69.11 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:43:12 PM PST 24
Peak memory 258116 kb
Host smart-5004aebd-8351-427d-a865-9185529c45f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420269841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.420269841
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3447684216
Short name T736
Test name
Test status
Simulation time 77998700 ps
CPU time 212.97 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:45:37 PM PST 24
Peak memory 275496 kb
Host smart-8012961f-ff9d-4876-9f88-8270e139ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447684216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3447684216
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2272967069
Short name T472
Test name
Test status
Simulation time 31304900 ps
CPU time 13.65 seconds
Started Jan 21 03:42:23 PM PST 24
Finished Jan 21 03:42:43 PM PST 24
Peak memory 264380 kb
Host smart-9925e5e4-7fac-43a5-9a65-a59a2ebb9a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272967069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2272967069
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2092916311
Short name T503
Test name
Test status
Simulation time 101138200 ps
CPU time 15.94 seconds
Started Jan 21 03:42:26 PM PST 24
Finished Jan 21 03:42:46 PM PST 24
Peak memory 273588 kb
Host smart-58fd60d5-dbc6-48e6-bcf2-937afee3210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092916311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2092916311
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.4279354543
Short name T448
Test name
Test status
Simulation time 12143800 ps
CPU time 20.81 seconds
Started Jan 21 03:42:13 PM PST 24
Finished Jan 21 03:42:34 PM PST 24
Peak memory 264372 kb
Host smart-9b374358-7fe8-422e-8b22-0c1508ac8ef1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279354543 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.4279354543
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.598135299
Short name T178
Test name
Test status
Simulation time 1933134200 ps
CPU time 58.47 seconds
Started Jan 21 04:00:28 PM PST 24
Finished Jan 21 04:01:28 PM PST 24
Peak memory 261180 kb
Host smart-24a14149-1b8b-4052-a042-103e187996a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598135299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h
w_sec_otp.598135299
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.1054739306
Short name T26
Test name
Test status
Simulation time 2307599900 ps
CPU time 163.81 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:44:47 PM PST 24
Peak memory 283232 kb
Host smart-1044ae5e-d9f9-47f8-b7d6-63526ba17053
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054739306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.1054739306
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.987426641
Short name T514
Test name
Test status
Simulation time 9055734200 ps
CPU time 224.42 seconds
Started Jan 21 03:42:02 PM PST 24
Finished Jan 21 03:45:48 PM PST 24
Peak memory 283020 kb
Host smart-5bedf397-1e15-4108-957c-1020b9c4786b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987426641 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.987426641
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2105433163
Short name T1047
Test name
Test status
Simulation time 49479800 ps
CPU time 13.5 seconds
Started Jan 21 03:42:13 PM PST 24
Finished Jan 21 03:42:27 PM PST 24
Peak memory 264296 kb
Host smart-1cdad442-31f1-411a-8964-04390dff94b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105433163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2105433163
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1605577017
Short name T788
Test name
Test status
Simulation time 30285900 ps
CPU time 31.77 seconds
Started Jan 21 03:42:12 PM PST 24
Finished Jan 21 03:42:44 PM PST 24
Peak memory 274052 kb
Host smart-bbf4e029-8dde-47ea-8383-b5bf157adc96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605577017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1605577017
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2099525598
Short name T403
Test name
Test status
Simulation time 73728600 ps
CPU time 31.39 seconds
Started Jan 21 03:42:11 PM PST 24
Finished Jan 21 03:42:43 PM PST 24
Peak memory 265532 kb
Host smart-bffbe88b-928f-41ca-a10e-5d9971e1a214
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099525598 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2099525598
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.2131960525
Short name T188
Test name
Test status
Simulation time 2569854600 ps
CPU time 70.49 seconds
Started Jan 21 03:42:23 PM PST 24
Finished Jan 21 03:43:41 PM PST 24
Peak memory 261492 kb
Host smart-9cac7c36-91de-46b3-9320-85450cd4ffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131960525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2131960525
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.3562302014
Short name T3
Test name
Test status
Simulation time 240924900 ps
CPU time 220.79 seconds
Started Jan 21 04:05:59 PM PST 24
Finished Jan 21 04:09:47 PM PST 24
Peak memory 280376 kb
Host smart-ac701faf-9a60-48c5-9fd8-52f854577977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562302014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3562302014
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.1074615138
Short name T638
Test name
Test status
Simulation time 44018800 ps
CPU time 13.5 seconds
Started Jan 21 03:42:26 PM PST 24
Finished Jan 21 03:42:44 PM PST 24
Peak memory 264260 kb
Host smart-1df5dfae-f0f6-4d5b-8d3e-86de71edad7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074615138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
1074615138
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1720892316
Short name T495
Test name
Test status
Simulation time 17565500 ps
CPU time 15.42 seconds
Started Jan 21 03:42:26 PM PST 24
Finished Jan 21 03:42:46 PM PST 24
Peak memory 273524 kb
Host smart-3e12a30d-7762-4987-a885-53881dedc7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720892316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1720892316
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2161667153
Short name T357
Test name
Test status
Simulation time 28153900 ps
CPU time 21.89 seconds
Started Jan 21 03:42:27 PM PST 24
Finished Jan 21 03:42:52 PM PST 24
Peak memory 272628 kb
Host smart-2434fad9-c4ad-40c4-8eed-9e628431f3ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161667153 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2161667153
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3521970315
Short name T743
Test name
Test status
Simulation time 3378903800 ps
CPU time 267.46 seconds
Started Jan 21 03:42:24 PM PST 24
Finished Jan 21 03:46:58 PM PST 24
Peak memory 261144 kb
Host smart-9578084b-17e1-4b7a-a71f-85d2a82a07f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521970315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3521970315
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.4106142725
Short name T779
Test name
Test status
Simulation time 17028584100 ps
CPU time 136.5 seconds
Started Jan 21 03:42:27 PM PST 24
Finished Jan 21 03:44:47 PM PST 24
Peak memory 292120 kb
Host smart-454173a2-fba6-45e3-a4e7-dd3b70bf754a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106142725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.4106142725
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1104319684
Short name T146
Test name
Test status
Simulation time 9328383700 ps
CPU time 205.55 seconds
Started Jan 21 03:42:24 PM PST 24
Finished Jan 21 03:45:56 PM PST 24
Peak memory 292140 kb
Host smart-492f4dd8-e6b5-4004-96bd-29cdbbf7ed1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104319684 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1104319684
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1049967093
Short name T747
Test name
Test status
Simulation time 65546800 ps
CPU time 13.58 seconds
Started Jan 21 03:42:25 PM PST 24
Finished Jan 21 03:42:44 PM PST 24
Peak memory 263004 kb
Host smart-88726949-4412-483e-b68d-25120b457a2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049967093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.1049967093
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1534187766
Short name T673
Test name
Test status
Simulation time 42115500 ps
CPU time 31.71 seconds
Started Jan 21 03:42:26 PM PST 24
Finished Jan 21 03:43:02 PM PST 24
Peak memory 265500 kb
Host smart-81f1db1c-a0e0-407b-9c51-e128aaefea58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534187766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1534187766
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2262447947
Short name T1028
Test name
Test status
Simulation time 49994700 ps
CPU time 33.67 seconds
Started Jan 21 03:42:34 PM PST 24
Finished Jan 21 03:43:09 PM PST 24
Peak memory 264460 kb
Host smart-f9c69b25-e851-4553-ba90-c09616994965
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262447947 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2262447947
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.448761464
Short name T877
Test name
Test status
Simulation time 3664550400 ps
CPU time 65.61 seconds
Started Jan 21 03:42:28 PM PST 24
Finished Jan 21 03:43:37 PM PST 24
Peak memory 258076 kb
Host smart-ec5673e4-e565-487a-bdd9-c504c7d996f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448761464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.448761464
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3875637975
Short name T798
Test name
Test status
Simulation time 70485900 ps
CPU time 169.45 seconds
Started Jan 21 03:42:25 PM PST 24
Finished Jan 21 03:45:20 PM PST 24
Peak memory 274596 kb
Host smart-6ab0169b-db05-4591-85fa-4224fd5390a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875637975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3875637975
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.3279991776
Short name T172
Test name
Test status
Simulation time 64994600 ps
CPU time 14.11 seconds
Started Jan 21 03:35:06 PM PST 24
Finished Jan 21 03:35:21 PM PST 24
Peak memory 264192 kb
Host smart-f1a3825c-b3c7-400d-875e-1da3e9425c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279991776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3
279991776
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.963179310
Short name T267
Test name
Test status
Simulation time 72854400 ps
CPU time 13.83 seconds
Started Jan 21 03:35:04 PM PST 24
Finished Jan 21 03:35:18 PM PST 24
Peak memory 264284 kb
Host smart-33e67a82-7043-413f-82c3-10afc1ffb242
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963179310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.963179310
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.167905362
Short name T183
Test name
Test status
Simulation time 40997300 ps
CPU time 15.85 seconds
Started Jan 21 03:35:04 PM PST 24
Finished Jan 21 03:35:21 PM PST 24
Peak memory 273508 kb
Host smart-a1b895c3-daa5-4844-b4f5-630e1a31a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167905362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.167905362
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.94721076
Short name T202
Test name
Test status
Simulation time 118788900 ps
CPU time 104.57 seconds
Started Jan 21 03:34:45 PM PST 24
Finished Jan 21 03:36:32 PM PST 24
Peak memory 272672 kb
Host smart-4be7d824-161b-4a16-921b-92723105025d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94721076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_derr_detect.94721076
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.370320473
Short name T152
Test name
Test status
Simulation time 2132958200 ps
CPU time 392.9 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:41:02 PM PST 24
Peak memory 261364 kb
Host smart-96995ac5-5eab-4989-913c-29d926a3cc7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370320473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.370320473
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.245153338
Short name T533
Test name
Test status
Simulation time 18884895000 ps
CPU time 2202.15 seconds
Started Jan 21 03:34:35 PM PST 24
Finished Jan 21 04:11:19 PM PST 24
Peak memory 262752 kb
Host smart-574623e1-71ef-41b3-b7e5-bc4e8bb3eb80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245153338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erro
r_mp.245153338
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2846180665
Short name T165
Test name
Test status
Simulation time 1082790900 ps
CPU time 2774.42 seconds
Started Jan 21 03:57:09 PM PST 24
Finished Jan 21 04:43:25 PM PST 24
Peak memory 264284 kb
Host smart-af738804-641e-4ed5-ac38-eea684bd80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846180665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2846180665
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3149630024
Short name T228
Test name
Test status
Simulation time 1382333600 ps
CPU time 780.74 seconds
Started Jan 21 03:49:07 PM PST 24
Finished Jan 21 04:02:11 PM PST 24
Peak memory 264296 kb
Host smart-c6b99db9-70da-4522-bc3d-57b19c4a9c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149630024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3149630024
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.250930689
Short name T170
Test name
Test status
Simulation time 287528700 ps
CPU time 34.19 seconds
Started Jan 21 03:52:49 PM PST 24
Finished Jan 21 03:53:24 PM PST 24
Peak memory 272540 kb
Host smart-037896ee-04b8-4a3f-a84c-b209c9b1a715
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250930689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.250930689
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3376677787
Short name T82
Test name
Test status
Simulation time 921280718200 ps
CPU time 2256.63 seconds
Started Jan 21 03:34:40 PM PST 24
Finished Jan 21 04:12:20 PM PST 24
Peak memory 263240 kb
Host smart-0274546c-41a2-477b-8227-f6fe263653d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376677787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3376677787
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2677309787
Short name T87
Test name
Test status
Simulation time 10012227300 ps
CPU time 127.56 seconds
Started Jan 21 03:35:05 PM PST 24
Finished Jan 21 03:37:14 PM PST 24
Peak memory 328104 kb
Host smart-bf12212f-9bbc-4adc-a81b-85a442b472f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677309787 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2677309787
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.993687
Short name T492
Test name
Test status
Simulation time 48288200 ps
CPU time 13.18 seconds
Started Jan 21 03:57:07 PM PST 24
Finished Jan 21 03:57:21 PM PST 24
Peak memory 264292 kb
Host smart-4ea832ea-a7bd-4679-863c-c366c289c09a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993687 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.993687
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1340361867
Short name T415
Test name
Test status
Simulation time 2260538100 ps
CPU time 185.97 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:37:34 PM PST 24
Peak memory 261128 kb
Host smart-b4b53b42-4641-4510-b29c-0716f1ca9d02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340361867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1340361867
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.1132968648
Short name T262
Test name
Test status
Simulation time 3690631400 ps
CPU time 490.67 seconds
Started Jan 21 03:34:44 PM PST 24
Finished Jan 21 03:42:57 PM PST 24
Peak memory 313572 kb
Host smart-97361796-40fc-4c59-948c-5a9316152820
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132968648 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.1132968648
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.953664500
Short name T483
Test name
Test status
Simulation time 58364365300 ps
CPU time 260.96 seconds
Started Jan 21 03:34:52 PM PST 24
Finished Jan 21 03:39:14 PM PST 24
Peak memory 292272 kb
Host smart-0f8020cb-9b7c-4a36-a8e6-d97943e664ad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953664500 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.953664500
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3486732680
Short name T933
Test name
Test status
Simulation time 3390841000 ps
CPU time 100.71 seconds
Started Jan 21 03:34:47 PM PST 24
Finished Jan 21 03:36:31 PM PST 24
Peak memory 264324 kb
Host smart-fe85b0e9-364b-4a4b-b662-f92fd1098cb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486732680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3486732680
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2513051563
Short name T445
Test name
Test status
Simulation time 11645467000 ps
CPU time 67.31 seconds
Started Jan 21 04:01:29 PM PST 24
Finished Jan 21 04:02:39 PM PST 24
Peak memory 258112 kb
Host smart-23c53c56-ea66-4216-8946-3cad18a93295
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513051563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2513051563
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3393256059
Short name T668
Test name
Test status
Simulation time 27397700 ps
CPU time 13.84 seconds
Started Jan 21 03:35:06 PM PST 24
Finished Jan 21 03:35:21 PM PST 24
Peak memory 264348 kb
Host smart-6f483f62-ce0e-4427-93fd-58fca70bca4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393256059 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3393256059
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1002406402
Short name T156
Test name
Test status
Simulation time 1588225100 ps
CPU time 70.28 seconds
Started Jan 21 04:10:40 PM PST 24
Finished Jan 21 04:11:51 PM PST 24
Peak memory 258264 kb
Host smart-e41a7bfc-9b45-4de9-b29e-7771d8b862a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002406402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1002406402
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.2941346281
Short name T115
Test name
Test status
Simulation time 62547773100 ps
CPU time 464.21 seconds
Started Jan 21 03:34:34 PM PST 24
Finished Jan 21 03:42:20 PM PST 24
Peak memory 272056 kb
Host smart-43b4559c-8170-4ac2-9c32-30fd4449e738
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941346281 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.2941346281
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.4169058778
Short name T37
Test name
Test status
Simulation time 3439543200 ps
CPU time 180.32 seconds
Started Jan 21 03:34:50 PM PST 24
Finished Jan 21 03:37:52 PM PST 24
Peak memory 280776 kb
Host smart-a0f45b10-b18a-4e54-a79a-45b2bbc7a7f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169058778 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.4169058778
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1670500659
Short name T219
Test name
Test status
Simulation time 45229100 ps
CPU time 14.09 seconds
Started Jan 21 04:04:44 PM PST 24
Finished Jan 21 04:05:00 PM PST 24
Peak memory 264468 kb
Host smart-bff3f676-5463-4657-8aa1-27df93a6716e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1670500659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1670500659
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1330721928
Short name T457
Test name
Test status
Simulation time 92307300 ps
CPU time 228.54 seconds
Started Jan 21 03:34:34 PM PST 24
Finished Jan 21 03:38:24 PM PST 24
Peak memory 259792 kb
Host smart-4466a23f-4cd2-4ae1-8000-76aadc966d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330721928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1330721928
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.416644101
Short name T163
Test name
Test status
Simulation time 109628800 ps
CPU time 14.49 seconds
Started Jan 21 03:35:06 PM PST 24
Finished Jan 21 03:35:21 PM PST 24
Peak memory 264432 kb
Host smart-9abf0acf-ab88-4f35-966e-d8e795c0a524
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416644101 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.416644101
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1022854309
Short name T594
Test name
Test status
Simulation time 34617800 ps
CPU time 13.52 seconds
Started Jan 21 03:34:52 PM PST 24
Finished Jan 21 03:35:06 PM PST 24
Peak memory 264356 kb
Host smart-8883e8b5-db3d-4312-b28c-45d7f2c629d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022854309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1022854309
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.354827874
Short name T134
Test name
Test status
Simulation time 8882956500 ps
CPU time 1187.16 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:54:16 PM PST 24
Peak memory 283088 kb
Host smart-c3919cdc-2721-43eb-bf8e-cd7c3229e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354827874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.354827874
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1845562844
Short name T279
Test name
Test status
Simulation time 1793519700 ps
CPU time 213.98 seconds
Started Jan 21 04:29:36 PM PST 24
Finished Jan 21 04:33:10 PM PST 24
Peak memory 263984 kb
Host smart-215145f8-f180-4dd1-b1b6-a0bcd83e31fb
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845562844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1845562844
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.890870027
Short name T391
Test name
Test status
Simulation time 1214284300 ps
CPU time 38.25 seconds
Started Jan 21 03:34:52 PM PST 24
Finished Jan 21 03:35:31 PM PST 24
Peak memory 272660 kb
Host smart-3706d2e0-579f-403b-8610-de7f2d34fc73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890870027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.890870027
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2522952008
Short name T1015
Test name
Test status
Simulation time 32494800 ps
CPU time 22.93 seconds
Started Jan 21 04:00:26 PM PST 24
Finished Jan 21 04:00:50 PM PST 24
Peak memory 264420 kb
Host smart-d9bbacb0-023e-4af0-b0f8-f19a746a34be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522952008 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2522952008
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2935548074
Short name T866
Test name
Test status
Simulation time 29747500 ps
CPU time 22.18 seconds
Started Jan 21 03:34:45 PM PST 24
Finished Jan 21 03:35:10 PM PST 24
Peak memory 264424 kb
Host smart-b9408126-59b5-4d6b-936c-bb598426f501
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935548074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2935548074
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2552181987
Short name T548
Test name
Test status
Simulation time 1792977400 ps
CPU time 139.96 seconds
Started Jan 21 04:50:09 PM PST 24
Finished Jan 21 04:52:31 PM PST 24
Peak memory 279316 kb
Host smart-f944263b-52ea-4fd1-bbce-9d7fb3697183
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552181987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.2552181987
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2903345777
Short name T508
Test name
Test status
Simulation time 585151400 ps
CPU time 130.5 seconds
Started Jan 21 03:34:44 PM PST 24
Finished Jan 21 03:36:56 PM PST 24
Peak memory 280828 kb
Host smart-acb59043-4863-4a38-800b-a8c9ccb91b31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2903345777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2903345777
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.2488728919
Short name T488
Test name
Test status
Simulation time 2167072400 ps
CPU time 116.4 seconds
Started Jan 21 03:34:44 PM PST 24
Finished Jan 21 03:36:42 PM PST 24
Peak memory 292568 kb
Host smart-2bda927a-e3ab-4284-a35d-3fd0e6770536
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488728919 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2488728919
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1222548367
Short name T214
Test name
Test status
Simulation time 16972513700 ps
CPU time 540.96 seconds
Started Jan 21 03:34:38 PM PST 24
Finished Jan 21 03:43:40 PM PST 24
Peak memory 313508 kb
Host smart-ca2a9c57-4028-4916-8ad5-29fb4f8ca63f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222548367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.1222548367
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1821169346
Short name T396
Test name
Test status
Simulation time 48090000 ps
CPU time 34.19 seconds
Started Jan 21 04:42:09 PM PST 24
Finished Jan 21 04:42:44 PM PST 24
Peak memory 274068 kb
Host smart-dd1ed8fe-601b-4a87-ab85-c27af1822b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821169346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1821169346
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1464190332
Short name T400
Test name
Test status
Simulation time 38059100 ps
CPU time 34.12 seconds
Started Jan 21 04:54:32 PM PST 24
Finished Jan 21 04:55:06 PM PST 24
Peak memory 274904 kb
Host smart-abc6fb30-f719-4edd-898d-5eec1b4fefbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464190332 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1464190332
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.678302463
Short name T67
Test name
Test status
Simulation time 3807743500 ps
CPU time 648.63 seconds
Started Jan 21 03:34:46 PM PST 24
Finished Jan 21 03:45:38 PM PST 24
Peak memory 313544 kb
Host smart-818e9ba2-f1ca-4b5f-a03c-adec00e35cb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678302463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_se
rr.678302463
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1023752574
Short name T185
Test name
Test status
Simulation time 5574588600 ps
CPU time 4926.29 seconds
Started Jan 21 03:34:52 PM PST 24
Finished Jan 21 04:57:00 PM PST 24
Peak memory 282120 kb
Host smart-b3196caf-f358-4784-8bab-83760a71c683
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023752574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1023752574
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.4258126684
Short name T377
Test name
Test status
Simulation time 4294299800 ps
CPU time 83.02 seconds
Started Jan 21 05:45:23 PM PST 24
Finished Jan 21 05:46:47 PM PST 24
Peak memory 262464 kb
Host smart-6edccd90-65fd-4fde-bf83-855d95c585c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258126684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.4258126684
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.1909598735
Short name T123
Test name
Test status
Simulation time 2337927000 ps
CPU time 66.76 seconds
Started Jan 21 04:01:24 PM PST 24
Finished Jan 21 04:02:32 PM PST 24
Peak memory 264500 kb
Host smart-c9892c92-8847-4536-a069-d4b56658ab7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909598735 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.1909598735
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.270642629
Short name T471
Test name
Test status
Simulation time 983264400 ps
CPU time 54.48 seconds
Started Jan 21 03:34:49 PM PST 24
Finished Jan 21 03:35:46 PM PST 24
Peak memory 271380 kb
Host smart-131f9112-7977-40d6-9cfa-3b9486fbef73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270642629 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.270642629
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.91511853
Short name T832
Test name
Test status
Simulation time 122544600 ps
CPU time 97.11 seconds
Started Jan 21 03:34:34 PM PST 24
Finished Jan 21 03:36:12 PM PST 24
Peak memory 274664 kb
Host smart-df937c92-44ce-4182-862e-4fcd7bcce8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91511853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.91511853
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.937162447
Short name T487
Test name
Test status
Simulation time 51449000 ps
CPU time 23.53 seconds
Started Jan 21 03:34:41 PM PST 24
Finished Jan 21 03:35:06 PM PST 24
Peak memory 257952 kb
Host smart-8b210334-1ebd-4585-8892-82fb84332241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937162447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.937162447
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.2235027986
Short name T333
Test name
Test status
Simulation time 256130400 ps
CPU time 1018.72 seconds
Started Jan 21 03:34:50 PM PST 24
Finished Jan 21 03:51:51 PM PST 24
Peak memory 288872 kb
Host smart-002c7cfa-c99a-4568-9bba-d5b09535092b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235027986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.2235027986
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3924637785
Short name T611
Test name
Test status
Simulation time 46853300 ps
CPU time 26.58 seconds
Started Jan 21 03:34:27 PM PST 24
Finished Jan 21 03:34:55 PM PST 24
Peak memory 258028 kb
Host smart-4d54dabc-ea89-4d22-918a-309491ec36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924637785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3924637785
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.2694849388
Short name T647
Test name
Test status
Simulation time 2259301200 ps
CPU time 194.5 seconds
Started Jan 21 03:34:49 PM PST 24
Finished Jan 21 03:38:06 PM PST 24
Peak memory 264312 kb
Host smart-51858ff6-ffd5-4256-927f-41711e302fc1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694849388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_wo.2694849388
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.3318408437
Short name T815
Test name
Test status
Simulation time 72953300 ps
CPU time 13.97 seconds
Started Jan 21 03:42:36 PM PST 24
Finished Jan 21 03:42:51 PM PST 24
Peak memory 264344 kb
Host smart-c26cc1e7-e351-4883-9812-7d860259e8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318408437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
3318408437
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2523579420
Short name T635
Test name
Test status
Simulation time 15202500 ps
CPU time 16.1 seconds
Started Jan 21 03:42:36 PM PST 24
Finished Jan 21 03:42:53 PM PST 24
Peak memory 273596 kb
Host smart-372616b6-6d06-4ed9-828f-2b652de077f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523579420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2523579420
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2033823911
Short name T1060
Test name
Test status
Simulation time 23191150900 ps
CPU time 283.51 seconds
Started Jan 21 03:42:26 PM PST 24
Finished Jan 21 03:47:14 PM PST 24
Peak memory 261120 kb
Host smart-07733a60-a0e2-4040-9c7a-ce44c2dc05a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033823911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.2033823911
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.3219804993
Short name T921
Test name
Test status
Simulation time 1108699400 ps
CPU time 156.7 seconds
Started Jan 21 03:42:39 PM PST 24
Finished Jan 21 03:45:17 PM PST 24
Peak memory 291280 kb
Host smart-fe43e792-442b-4f16-b0b6-a90df69092da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219804993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.3219804993
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3565218563
Short name T1048
Test name
Test status
Simulation time 33363248500 ps
CPU time 217.34 seconds
Started Jan 21 03:42:36 PM PST 24
Finished Jan 21 03:46:14 PM PST 24
Peak memory 292076 kb
Host smart-6bed2059-e61b-4b48-b2c9-459f65149d8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565218563 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3565218563
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2487249912
Short name T922
Test name
Test status
Simulation time 30237200 ps
CPU time 31.59 seconds
Started Jan 21 03:42:34 PM PST 24
Finished Jan 21 03:43:07 PM PST 24
Peak memory 272660 kb
Host smart-23db1a26-405e-4c2a-8b4d-43f7ba6cd7d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487249912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2487249912
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3459858505
Short name T733
Test name
Test status
Simulation time 44022600 ps
CPU time 31.33 seconds
Started Jan 21 03:42:38 PM PST 24
Finished Jan 21 03:43:10 PM PST 24
Peak memory 272664 kb
Host smart-edab54ea-85e2-4fbc-aa16-9c54ef0381fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459858505 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3459858505
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1899024607
Short name T1012
Test name
Test status
Simulation time 1100879900 ps
CPU time 57.06 seconds
Started Jan 21 03:42:36 PM PST 24
Finished Jan 21 03:43:34 PM PST 24
Peak memory 258104 kb
Host smart-42807e41-0c5e-44a3-a4bc-1a77e3857a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899024607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1899024607
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.1108828814
Short name T893
Test name
Test status
Simulation time 70369100 ps
CPU time 124.03 seconds
Started Jan 21 03:42:29 PM PST 24
Finished Jan 21 03:44:38 PM PST 24
Peak memory 273784 kb
Host smart-74f5c0a1-1f81-4111-a319-59f5aece084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108828814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1108828814
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.28318546
Short name T805
Test name
Test status
Simulation time 365742400 ps
CPU time 14.33 seconds
Started Jan 21 03:42:55 PM PST 24
Finished Jan 21 03:43:13 PM PST 24
Peak memory 264220 kb
Host smart-9b854377-9b44-41db-9a39-2125ee641ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.28318546
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.805982850
Short name T669
Test name
Test status
Simulation time 48961400 ps
CPU time 13.38 seconds
Started Jan 21 03:43:03 PM PST 24
Finished Jan 21 03:43:19 PM PST 24
Peak memory 273468 kb
Host smart-6d831f67-a50b-4304-a089-93a684d79737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805982850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.805982850
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.3665305909
Short name T28
Test name
Test status
Simulation time 25719900 ps
CPU time 20.62 seconds
Started Jan 21 03:42:44 PM PST 24
Finished Jan 21 03:43:06 PM PST 24
Peak memory 264432 kb
Host smart-d6757fc3-897d-4683-9a1a-15f935013daa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665305909 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.3665305909
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3425488819
Short name T42
Test name
Test status
Simulation time 2870671800 ps
CPU time 224.82 seconds
Started Jan 21 03:42:38 PM PST 24
Finished Jan 21 03:46:24 PM PST 24
Peak memory 261260 kb
Host smart-1e13d41c-81f8-4fa7-af67-b63f42d1fe36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425488819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3425488819
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.2302410470
Short name T213
Test name
Test status
Simulation time 2182909800 ps
CPU time 172.79 seconds
Started Jan 21 03:42:39 PM PST 24
Finished Jan 21 03:45:33 PM PST 24
Peak memory 290196 kb
Host smart-cc751f93-bb8c-4233-9b8a-013ad9314a00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302410470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.2302410470
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2000211382
Short name T263
Test name
Test status
Simulation time 16064289000 ps
CPU time 216.66 seconds
Started Jan 21 03:42:36 PM PST 24
Finished Jan 21 03:46:14 PM PST 24
Peak memory 282928 kb
Host smart-cac7b3b6-320a-4e8f-879e-3bd8a8159b74
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000211382 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2000211382
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3618360179
Short name T730
Test name
Test status
Simulation time 79098700 ps
CPU time 31.46 seconds
Started Jan 21 03:42:44 PM PST 24
Finished Jan 21 03:43:17 PM PST 24
Peak memory 270956 kb
Host smart-bb6cdfd3-39f9-4317-8859-977c9a7d9de1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618360179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3618360179
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3978903557
Short name T64
Test name
Test status
Simulation time 235448600 ps
CPU time 29.25 seconds
Started Jan 21 03:42:45 PM PST 24
Finished Jan 21 03:43:16 PM PST 24
Peak memory 265456 kb
Host smart-2586d08f-5638-4613-aca4-9f506d9b461e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978903557 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3978903557
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3211822825
Short name T362
Test name
Test status
Simulation time 350027700 ps
CPU time 52.54 seconds
Started Jan 21 03:42:43 PM PST 24
Finished Jan 21 03:43:37 PM PST 24
Peak memory 261608 kb
Host smart-87d0c6f4-f07f-49ea-aa0b-a00655afb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211822825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3211822825
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.256787013
Short name T849
Test name
Test status
Simulation time 159918100 ps
CPU time 99.4 seconds
Started Jan 21 03:42:35 PM PST 24
Finished Jan 21 03:44:16 PM PST 24
Peak memory 273804 kb
Host smart-741c9c97-31e3-4a8c-8313-bb6b57182ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256787013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.256787013
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.269275813
Short name T451
Test name
Test status
Simulation time 92695400 ps
CPU time 13.7 seconds
Started Jan 21 03:42:54 PM PST 24
Finished Jan 21 03:43:12 PM PST 24
Peak memory 264192 kb
Host smart-1975eaff-4644-4312-99a3-581f71b0a854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269275813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.269275813
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.834748945
Short name T1027
Test name
Test status
Simulation time 49856400 ps
CPU time 13.51 seconds
Started Jan 21 03:43:03 PM PST 24
Finished Jan 21 03:43:20 PM PST 24
Peak memory 273592 kb
Host smart-370cc832-54cd-4ce9-9555-33120414d381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834748945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.834748945
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.516503298
Short name T693
Test name
Test status
Simulation time 4791595000 ps
CPU time 183.95 seconds
Started Jan 21 03:42:56 PM PST 24
Finished Jan 21 03:46:04 PM PST 24
Peak memory 283028 kb
Host smart-a170e195-d461-47f3-b340-4c8d24a687d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516503298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flas
h_ctrl_intr_rd.516503298
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1901482892
Short name T509
Test name
Test status
Simulation time 17008192600 ps
CPU time 210.64 seconds
Started Jan 21 03:43:00 PM PST 24
Finished Jan 21 03:46:33 PM PST 24
Peak memory 282936 kb
Host smart-770a527a-060e-4ce3-b44f-0efb7cbb14cc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901482892 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1901482892
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.408291854
Short name T604
Test name
Test status
Simulation time 84705500 ps
CPU time 31.64 seconds
Started Jan 21 03:42:58 PM PST 24
Finished Jan 21 03:43:32 PM PST 24
Peak memory 271004 kb
Host smart-8b7c3f5b-777e-4825-9440-76cee084f6c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408291854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.408291854
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1018665393
Short name T914
Test name
Test status
Simulation time 83209900 ps
CPU time 31.55 seconds
Started Jan 21 03:43:02 PM PST 24
Finished Jan 21 03:43:37 PM PST 24
Peak memory 274152 kb
Host smart-ee8ad931-6d30-4556-af61-3ea137a100c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018665393 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1018665393
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3324786110
Short name T1052
Test name
Test status
Simulation time 8922312700 ps
CPU time 62.59 seconds
Started Jan 21 03:43:01 PM PST 24
Finished Jan 21 03:44:08 PM PST 24
Peak memory 258076 kb
Host smart-a72b439a-3041-4c49-8a66-f574c58edde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324786110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3324786110
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.876469324
Short name T828
Test name
Test status
Simulation time 64856100 ps
CPU time 120.07 seconds
Started Jan 21 03:42:58 PM PST 24
Finished Jan 21 03:45:01 PM PST 24
Peak memory 274156 kb
Host smart-56a395e6-d1bf-4dfb-85b3-7e5db858bc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876469324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.876469324
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.3565041209
Short name T1000
Test name
Test status
Simulation time 92863300 ps
CPU time 14.3 seconds
Started Jan 21 04:03:57 PM PST 24
Finished Jan 21 04:04:12 PM PST 24
Peak memory 264388 kb
Host smart-a0e3309d-f1bc-41f9-8ddb-157721c4a27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565041209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
3565041209
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.3937456736
Short name T735
Test name
Test status
Simulation time 72237200 ps
CPU time 15.86 seconds
Started Jan 21 03:43:01 PM PST 24
Finished Jan 21 03:43:21 PM PST 24
Peak memory 273628 kb
Host smart-2ff9827f-eec3-4711-8b4d-4e06049a1768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937456736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3937456736
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.2889730374
Short name T324
Test name
Test status
Simulation time 14789764000 ps
CPU time 150.56 seconds
Started Jan 21 03:43:01 PM PST 24
Finished Jan 21 03:45:34 PM PST 24
Peak memory 261172 kb
Host smart-7c404471-df01-419e-ae94-69a24e3e4c64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889730374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.2889730374
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2183374417
Short name T1018
Test name
Test status
Simulation time 2374987100 ps
CPU time 175.31 seconds
Started Jan 21 03:43:00 PM PST 24
Finished Jan 21 03:45:57 PM PST 24
Peak memory 291320 kb
Host smart-26f072ed-d5b3-4a3a-982d-e45f25835313
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183374417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2183374417
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1185130696
Short name T802
Test name
Test status
Simulation time 17586790200 ps
CPU time 215.16 seconds
Started Jan 21 03:43:02 PM PST 24
Finished Jan 21 03:46:40 PM PST 24
Peak memory 290620 kb
Host smart-d6a3173f-7272-47b3-8311-d7e105307437
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185130696 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1185130696
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.3589722503
Short name T79
Test name
Test status
Simulation time 81221000 ps
CPU time 132.21 seconds
Started Jan 21 03:43:01 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 258172 kb
Host smart-915b5350-51b0-4f49-a85d-b0075358ee0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589722503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.3589722503
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1653964769
Short name T829
Test name
Test status
Simulation time 49563300 ps
CPU time 34.04 seconds
Started Jan 21 04:06:26 PM PST 24
Finished Jan 21 04:07:06 PM PST 24
Peak memory 276464 kb
Host smart-acc67f82-9a20-481f-8315-bfdc03bb87c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653964769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1653964769
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.381923336
Short name T781
Test name
Test status
Simulation time 73446700 ps
CPU time 31.27 seconds
Started Jan 21 03:43:08 PM PST 24
Finished Jan 21 03:43:54 PM PST 24
Peak memory 270964 kb
Host smart-75854c27-f02c-47ff-ac04-f5fe735e8fa3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381923336 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.381923336
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.3993236516
Short name T934
Test name
Test status
Simulation time 29262600 ps
CPU time 73.41 seconds
Started Jan 21 03:42:56 PM PST 24
Finished Jan 21 03:44:14 PM PST 24
Peak memory 273256 kb
Host smart-d944938b-9b02-42ff-98cd-7d08bee35303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993236516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3993236516
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2649342534
Short name T320
Test name
Test status
Simulation time 31346300 ps
CPU time 13.5 seconds
Started Jan 21 03:43:09 PM PST 24
Finished Jan 21 03:43:36 PM PST 24
Peak memory 264172 kb
Host smart-89625ab0-028a-43f7-b724-298f6b5d3ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649342534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2649342534
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1092804346
Short name T589
Test name
Test status
Simulation time 79600100 ps
CPU time 16.65 seconds
Started Jan 21 04:28:13 PM PST 24
Finished Jan 21 04:28:30 PM PST 24
Peak memory 273496 kb
Host smart-3d8afcf3-7d12-4b11-8984-87c44848c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092804346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1092804346
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1559319539
Short name T355
Test name
Test status
Simulation time 31998400 ps
CPU time 21.91 seconds
Started Jan 21 03:43:09 PM PST 24
Finished Jan 21 03:43:45 PM PST 24
Peak memory 273764 kb
Host smart-328da468-164f-4c73-bb79-17d1bb6be821
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559319539 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1559319539
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3153929154
Short name T864
Test name
Test status
Simulation time 1593901600 ps
CPU time 73.09 seconds
Started Jan 21 03:51:52 PM PST 24
Finished Jan 21 03:53:06 PM PST 24
Peak memory 261416 kb
Host smart-76243f2f-0ad0-482d-b858-66a3a003f5bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153929154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3153929154
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2455342822
Short name T686
Test name
Test status
Simulation time 2374797800 ps
CPU time 152.79 seconds
Started Jan 21 03:43:07 PM PST 24
Finished Jan 21 03:45:55 PM PST 24
Peak memory 292260 kb
Host smart-bf3c4bc7-8009-4f8e-bbe6-ae6999dc9d4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455342822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2455342822
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.925178618
Short name T1037
Test name
Test status
Simulation time 8412020100 ps
CPU time 228.29 seconds
Started Jan 21 03:43:08 PM PST 24
Finished Jan 21 03:47:11 PM PST 24
Peak memory 292236 kb
Host smart-f6741dbd-279b-4eb9-b45b-964639e824d4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925178618 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.925178618
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1041654212
Short name T721
Test name
Test status
Simulation time 27773500 ps
CPU time 31.81 seconds
Started Jan 21 03:43:08 PM PST 24
Finished Jan 21 03:43:54 PM PST 24
Peak memory 272616 kb
Host smart-fb598bde-7e8e-4aee-9e70-78392736bbbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041654212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1041654212
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1329948175
Short name T876
Test name
Test status
Simulation time 43704000 ps
CPU time 31.46 seconds
Started Jan 21 03:43:10 PM PST 24
Finished Jan 21 03:43:54 PM PST 24
Peak memory 272656 kb
Host smart-898d6c13-fb71-41ff-ba5a-147873faf373
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329948175 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1329948175
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3834936646
Short name T527
Test name
Test status
Simulation time 2853363600 ps
CPU time 68.98 seconds
Started Jan 21 03:43:09 PM PST 24
Finished Jan 21 03:44:32 PM PST 24
Peak memory 258160 kb
Host smart-a8aea4f9-4180-4479-b13d-c7ff8a8f5a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834936646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3834936646
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3926010254
Short name T332
Test name
Test status
Simulation time 89091500 ps
CPU time 96.44 seconds
Started Jan 21 03:53:45 PM PST 24
Finished Jan 21 03:55:22 PM PST 24
Peak memory 274936 kb
Host smart-01102c13-eb1f-4aaa-9d76-91b540e16bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926010254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3926010254
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.1023374647
Short name T782
Test name
Test status
Simulation time 39197300 ps
CPU time 13.87 seconds
Started Jan 21 03:43:26 PM PST 24
Finished Jan 21 03:43:43 PM PST 24
Peak memory 264308 kb
Host smart-6c6cdfb9-f5de-493f-81a0-773c46451b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023374647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
1023374647
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.4097436999
Short name T1026
Test name
Test status
Simulation time 27419700 ps
CPU time 15.49 seconds
Started Jan 21 03:43:29 PM PST 24
Finished Jan 21 03:43:47 PM PST 24
Peak memory 274264 kb
Host smart-33e82066-5adb-46cb-a83b-f40bc81aefea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097436999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.4097436999
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2906022574
Short name T775
Test name
Test status
Simulation time 8122568100 ps
CPU time 114.07 seconds
Started Jan 21 03:43:19 PM PST 24
Finished Jan 21 03:45:21 PM PST 24
Peak memory 261188 kb
Host smart-441d0e61-2ab9-4e01-99a2-f88f75b80d8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906022574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2906022574
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1835961457
Short name T758
Test name
Test status
Simulation time 6299401500 ps
CPU time 170.6 seconds
Started Jan 21 03:43:21 PM PST 24
Finished Jan 21 03:46:19 PM PST 24
Peak memory 282852 kb
Host smart-adce6251-e269-4912-ab8d-19a9186599af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835961457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1835961457
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.465866257
Short name T808
Test name
Test status
Simulation time 86945715900 ps
CPU time 258.34 seconds
Started Jan 21 03:43:24 PM PST 24
Finished Jan 21 03:47:47 PM PST 24
Peak memory 283004 kb
Host smart-a5f2bc4d-e10a-436a-b992-9ff1d9c0beac
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465866257 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.465866257
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.3538682476
Short name T93
Test name
Test status
Simulation time 37202500 ps
CPU time 110.79 seconds
Started Jan 21 03:43:18 PM PST 24
Finished Jan 21 03:45:18 PM PST 24
Peak memory 258448 kb
Host smart-09bd804f-b0fd-401f-bf5a-65d3368199e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538682476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.3538682476
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.2366818077
Short name T484
Test name
Test status
Simulation time 37651000 ps
CPU time 31.58 seconds
Started Jan 21 03:43:18 PM PST 24
Finished Jan 21 03:43:58 PM PST 24
Peak memory 270936 kb
Host smart-48ddc9b3-1252-408d-acdb-62fd7296a5d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366818077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.2366818077
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.486284965
Short name T291
Test name
Test status
Simulation time 48197500 ps
CPU time 31.35 seconds
Started Jan 21 03:43:24 PM PST 24
Finished Jan 21 03:44:00 PM PST 24
Peak memory 265416 kb
Host smart-bf73ce56-0101-4346-9850-72519420fdbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486284965 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.486284965
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2523541596
Short name T376
Test name
Test status
Simulation time 1220627600 ps
CPU time 63.09 seconds
Started Jan 21 03:43:28 PM PST 24
Finished Jan 21 03:44:34 PM PST 24
Peak memory 258068 kb
Host smart-faadd448-d964-4323-b30a-94b42773c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523541596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2523541596
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.2751756943
Short name T995
Test name
Test status
Simulation time 17386400 ps
CPU time 72.95 seconds
Started Jan 21 03:43:09 PM PST 24
Finished Jan 21 03:44:36 PM PST 24
Peak memory 274352 kb
Host smart-8e6f4cda-d12e-4584-9ea8-d0a5f711cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751756943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2751756943
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.960228146
Short name T467
Test name
Test status
Simulation time 60067300 ps
CPU time 13.83 seconds
Started Jan 21 03:43:40 PM PST 24
Finished Jan 21 03:43:56 PM PST 24
Peak memory 264236 kb
Host smart-dd7bbde7-1f41-4252-b29c-54c53b49aaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960228146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.960228146
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.1616896609
Short name T566
Test name
Test status
Simulation time 18294300 ps
CPU time 15.88 seconds
Started Jan 21 03:43:27 PM PST 24
Finished Jan 21 03:43:45 PM PST 24
Peak memory 273652 kb
Host smart-3ffe111d-1ee3-4506-8f80-88fe808134ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616896609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1616896609
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.2926652643
Short name T449
Test name
Test status
Simulation time 36106000 ps
CPU time 21.24 seconds
Started Jan 21 03:43:28 PM PST 24
Finished Jan 21 03:43:52 PM PST 24
Peak memory 264468 kb
Host smart-64156849-5af3-499f-8806-a835fe86f7a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926652643 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.2926652643
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3269312222
Short name T861
Test name
Test status
Simulation time 17808757800 ps
CPU time 129.09 seconds
Started Jan 21 03:43:28 PM PST 24
Finished Jan 21 03:45:40 PM PST 24
Peak memory 261156 kb
Host smart-a34f0dd0-8e26-46e5-8785-07716ade7609
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269312222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3269312222
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.1431394866
Short name T716
Test name
Test status
Simulation time 5228195900 ps
CPU time 180.98 seconds
Started Jan 21 03:43:27 PM PST 24
Finished Jan 21 03:46:31 PM PST 24
Peak memory 292228 kb
Host smart-7c7aad14-053f-420f-acdb-7550eaef6c2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431394866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.1431394866
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.882056221
Short name T886
Test name
Test status
Simulation time 17517831300 ps
CPU time 245.24 seconds
Started Jan 21 03:43:27 PM PST 24
Finished Jan 21 03:47:35 PM PST 24
Peak memory 282956 kb
Host smart-4baeede8-e87c-4dbb-a001-29e0411b8f7d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882056221 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.882056221
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2395441449
Short name T285
Test name
Test status
Simulation time 105107900 ps
CPU time 32.7 seconds
Started Jan 21 03:43:26 PM PST 24
Finished Jan 21 03:44:02 PM PST 24
Peak memory 264440 kb
Host smart-41216c76-cbfe-4579-bfdf-ffba10e19aea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395441449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2395441449
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2783676128
Short name T774
Test name
Test status
Simulation time 38150500 ps
CPU time 31.41 seconds
Started Jan 21 03:43:28 PM PST 24
Finished Jan 21 03:44:01 PM PST 24
Peak memory 270980 kb
Host smart-dcae249d-832a-45d1-b656-37f2acb4926b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783676128 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2783676128
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.2033363342
Short name T954
Test name
Test status
Simulation time 988334300 ps
CPU time 64.57 seconds
Started Jan 21 03:43:25 PM PST 24
Finished Jan 21 03:44:34 PM PST 24
Peak memory 261320 kb
Host smart-f1a2bf1b-bbd5-4ce5-8f94-7f7b8648340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033363342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2033363342
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2677228880
Short name T632
Test name
Test status
Simulation time 21237100 ps
CPU time 124.81 seconds
Started Jan 21 03:43:27 PM PST 24
Finished Jan 21 03:45:35 PM PST 24
Peak memory 277128 kb
Host smart-17b88065-3b22-4b24-9b8a-795ad48b7a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677228880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2677228880
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.3080990283
Short name T885
Test name
Test status
Simulation time 33167300 ps
CPU time 13.55 seconds
Started Jan 21 03:43:47 PM PST 24
Finished Jan 21 03:44:01 PM PST 24
Peak memory 264196 kb
Host smart-09e63846-fa06-413f-b67c-58972f28de9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080990283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
3080990283
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1444699814
Short name T948
Test name
Test status
Simulation time 65548800 ps
CPU time 13.51 seconds
Started Jan 21 03:43:46 PM PST 24
Finished Jan 21 03:44:00 PM PST 24
Peak memory 273420 kb
Host smart-b37e152e-f5fe-47db-9a7f-988c0bc49259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444699814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1444699814
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.3223266290
Short name T732
Test name
Test status
Simulation time 25175700 ps
CPU time 20.55 seconds
Started Jan 21 03:43:36 PM PST 24
Finished Jan 21 03:43:58 PM PST 24
Peak memory 264360 kb
Host smart-090dba9c-8771-4d5f-9cdf-ad819bedde24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223266290 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.3223266290
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.867873107
Short name T796
Test name
Test status
Simulation time 13140964400 ps
CPU time 98.24 seconds
Started Jan 21 03:43:45 PM PST 24
Finished Jan 21 03:45:24 PM PST 24
Peak memory 261224 kb
Host smart-a67f5b70-ff2c-40bd-b1e9-53a8581e3fc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867873107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h
w_sec_otp.867873107
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.491491052
Short name T917
Test name
Test status
Simulation time 941119200 ps
CPU time 145.97 seconds
Started Jan 21 03:43:37 PM PST 24
Finished Jan 21 03:46:05 PM PST 24
Peak memory 292288 kb
Host smart-8646d870-4625-4f05-a3be-a9383ceaeeb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491491052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_intr_rd.491491052
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3245549563
Short name T411
Test name
Test status
Simulation time 8472874200 ps
CPU time 181.06 seconds
Started Jan 21 03:43:45 PM PST 24
Finished Jan 21 03:46:47 PM PST 24
Peak memory 288976 kb
Host smart-bc980a7f-8a19-469f-98b8-9627232c19cd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245549563 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3245549563
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.4264460511
Short name T731
Test name
Test status
Simulation time 203948400 ps
CPU time 34.59 seconds
Started Jan 21 03:43:42 PM PST 24
Finished Jan 21 03:44:17 PM PST 24
Peak memory 265468 kb
Host smart-cd8a2d33-963d-403b-a9fe-4298830a188e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264460511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.4264460511
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2739703250
Short name T870
Test name
Test status
Simulation time 52276900 ps
CPU time 31.47 seconds
Started Jan 21 03:43:41 PM PST 24
Finished Jan 21 03:44:14 PM PST 24
Peak memory 272632 kb
Host smart-08b0ab3e-8c59-4340-b580-00f285509342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739703250 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2739703250
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3665357208
Short name T5
Test name
Test status
Simulation time 545647600 ps
CPU time 62.04 seconds
Started Jan 21 03:43:37 PM PST 24
Finished Jan 21 03:44:41 PM PST 24
Peak memory 260796 kb
Host smart-21d1619b-f5e0-47af-bd72-972efe00140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665357208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3665357208
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.43521405
Short name T729
Test name
Test status
Simulation time 66568200 ps
CPU time 196.25 seconds
Started Jan 21 03:43:44 PM PST 24
Finished Jan 21 03:47:01 PM PST 24
Peak memory 274720 kb
Host smart-b8ab61bb-323a-4dba-89b0-f28bbcb5f311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43521405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.43521405
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2767150606
Short name T532
Test name
Test status
Simulation time 29171800 ps
CPU time 13.62 seconds
Started Jan 21 03:43:50 PM PST 24
Finished Jan 21 03:44:06 PM PST 24
Peak memory 264368 kb
Host smart-ec57fbe4-5744-4927-9075-ca6e93649220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767150606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2767150606
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.435486911
Short name T555
Test name
Test status
Simulation time 22077800 ps
CPU time 16.04 seconds
Started Jan 21 03:43:45 PM PST 24
Finished Jan 21 03:44:02 PM PST 24
Peak memory 273528 kb
Host smart-026b6cf0-f28c-4c69-aaf5-5f923ec950d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435486911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.435486911
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.436237226
Short name T326
Test name
Test status
Simulation time 3412661600 ps
CPU time 197.54 seconds
Started Jan 21 03:43:47 PM PST 24
Finished Jan 21 03:47:05 PM PST 24
Peak memory 259304 kb
Host smart-28b80ae7-c1a4-4772-abe9-52c12857511f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436237226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.436237226
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.246628693
Short name T868
Test name
Test status
Simulation time 1319260700 ps
CPU time 175.57 seconds
Started Jan 21 03:43:45 PM PST 24
Finished Jan 21 03:46:42 PM PST 24
Peak memory 292208 kb
Host smart-fbca41f2-c715-47ad-a633-429dae0dcaa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246628693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas
h_ctrl_intr_rd.246628693
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3191599735
Short name T794
Test name
Test status
Simulation time 8210197800 ps
CPU time 200.68 seconds
Started Jan 21 03:43:46 PM PST 24
Finished Jan 21 03:47:08 PM PST 24
Peak memory 283148 kb
Host smart-a8abf2b5-bc6e-45c8-b945-f1f7bc7aef08
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191599735 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.3191599735
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1315685527
Short name T822
Test name
Test status
Simulation time 36411100 ps
CPU time 110.64 seconds
Started Jan 21 03:43:50 PM PST 24
Finished Jan 21 03:45:43 PM PST 24
Peak memory 258020 kb
Host smart-79f77709-53b5-4038-b8dd-ec6f0e7197f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315685527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1315685527
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.865824504
Short name T543
Test name
Test status
Simulation time 58057500 ps
CPU time 31.56 seconds
Started Jan 21 03:43:43 PM PST 24
Finished Jan 21 03:44:15 PM PST 24
Peak memory 275884 kb
Host smart-c7667b38-3fa8-4293-857d-542742a38b0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865824504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_rw_evict.865824504
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.517708931
Short name T750
Test name
Test status
Simulation time 279550900 ps
CPU time 31.71 seconds
Started Jan 21 03:43:47 PM PST 24
Finished Jan 21 03:44:19 PM PST 24
Peak memory 270964 kb
Host smart-27e7d938-1c9b-4e71-b84c-dc2ab896eec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517708931 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.517708931
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.962124458
Short name T1045
Test name
Test status
Simulation time 3057569200 ps
CPU time 70.11 seconds
Started Jan 21 03:43:46 PM PST 24
Finished Jan 21 03:44:57 PM PST 24
Peak memory 258172 kb
Host smart-b5a8d3a3-fffe-4438-b974-6fe924bf2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962124458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.962124458
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.1019602935
Short name T530
Test name
Test status
Simulation time 40765000 ps
CPU time 99.59 seconds
Started Jan 21 03:43:50 PM PST 24
Finished Jan 21 03:45:32 PM PST 24
Peak memory 265172 kb
Host smart-674357ee-504c-4937-a6bc-fd84f400fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019602935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1019602935
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.1637023864
Short name T903
Test name
Test status
Simulation time 48359300 ps
CPU time 13.68 seconds
Started Jan 21 03:44:00 PM PST 24
Finished Jan 21 03:44:15 PM PST 24
Peak memory 264392 kb
Host smart-0ed17c24-4404-40a6-851c-aabc07466af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637023864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
1637023864
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.209708882
Short name T556
Test name
Test status
Simulation time 21834500 ps
CPU time 13.81 seconds
Started Jan 21 03:44:00 PM PST 24
Finished Jan 21 03:44:15 PM PST 24
Peak memory 273612 kb
Host smart-b0b19c0f-74d7-4b63-83ec-0bb58cb6e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209708882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.209708882
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3803595539
Short name T722
Test name
Test status
Simulation time 31371800 ps
CPU time 21.29 seconds
Started Jan 21 03:44:00 PM PST 24
Finished Jan 21 03:44:23 PM PST 24
Peak memory 264276 kb
Host smart-a503f303-9db8-4b47-a356-677bc28e98e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803595539 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3803595539
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1348869477
Short name T682
Test name
Test status
Simulation time 4539931200 ps
CPU time 171.85 seconds
Started Jan 21 03:43:50 PM PST 24
Finished Jan 21 03:46:44 PM PST 24
Peak memory 261380 kb
Host smart-867723fc-11cb-4a44-8ab0-b4381c05e248
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348869477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.1348869477
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.3121201996
Short name T212
Test name
Test status
Simulation time 4277548900 ps
CPU time 145.74 seconds
Started Jan 21 03:43:50 PM PST 24
Finished Jan 21 03:46:18 PM PST 24
Peak memory 292120 kb
Host smart-fe0aaf17-28fe-4cf7-b5d2-9a6b04632edf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121201996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.3121201996
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1803633348
Short name T598
Test name
Test status
Simulation time 17770957300 ps
CPU time 240.88 seconds
Started Jan 21 03:43:51 PM PST 24
Finished Jan 21 03:47:53 PM PST 24
Peak memory 282956 kb
Host smart-35012a0c-965e-44e8-9edf-482869022093
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803633348 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1803633348
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.2431564621
Short name T283
Test name
Test status
Simulation time 52895500 ps
CPU time 32.33 seconds
Started Jan 21 03:43:59 PM PST 24
Finished Jan 21 03:44:33 PM PST 24
Peak memory 275436 kb
Host smart-2de24063-67a1-46d6-b25d-579720255bf6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431564621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.2431564621
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2901332158
Short name T24
Test name
Test status
Simulation time 69231100 ps
CPU time 31.53 seconds
Started Jan 21 03:44:00 PM PST 24
Finished Jan 21 03:44:33 PM PST 24
Peak memory 273852 kb
Host smart-206328e9-3494-4880-9d81-081cc687aab5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901332158 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2901332158
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.2224864750
Short name T365
Test name
Test status
Simulation time 1300138100 ps
CPU time 63.86 seconds
Started Jan 21 03:44:01 PM PST 24
Finished Jan 21 03:45:06 PM PST 24
Peak memory 262780 kb
Host smart-70040808-c7fb-42d7-9677-2d9b04eedcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224864750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2224864750
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.2299541415
Short name T897
Test name
Test status
Simulation time 58761200 ps
CPU time 96.96 seconds
Started Jan 21 04:08:39 PM PST 24
Finished Jan 21 04:10:17 PM PST 24
Peak memory 273784 kb
Host smart-70894b78-1499-4635-bb4d-bef9ec680809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299541415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2299541415
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.296877346
Short name T506
Test name
Test status
Simulation time 93936900 ps
CPU time 13.86 seconds
Started Jan 21 03:35:50 PM PST 24
Finished Jan 21 03:36:05 PM PST 24
Peak memory 264200 kb
Host smart-e6996b36-bfb9-4814-a881-d86cfc09e211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296877346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.296877346
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.337907203
Short name T972
Test name
Test status
Simulation time 77049000 ps
CPU time 13.72 seconds
Started Jan 21 03:35:41 PM PST 24
Finished Jan 21 03:35:55 PM PST 24
Peak memory 264332 kb
Host smart-aa37c742-9a98-45da-abbe-5d51a2e8a147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337907203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.337907203
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.269839347
Short name T944
Test name
Test status
Simulation time 26377800 ps
CPU time 15.95 seconds
Started Jan 21 03:35:41 PM PST 24
Finished Jan 21 03:35:59 PM PST 24
Peak memory 273668 kb
Host smart-ae61a45b-fc5f-40cc-9792-b11d549343ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269839347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.269839347
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2043016074
Short name T1032
Test name
Test status
Simulation time 1425251300 ps
CPU time 339.45 seconds
Started Jan 21 03:35:10 PM PST 24
Finished Jan 21 03:40:50 PM PST 24
Peak memory 261348 kb
Host smart-b12260a5-b8ed-4703-9ded-4b5c88ed7737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043016074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2043016074
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.3396678468
Short name T23
Test name
Test status
Simulation time 4433624800 ps
CPU time 2407.77 seconds
Started Jan 21 03:35:32 PM PST 24
Finished Jan 21 04:15:41 PM PST 24
Peak memory 262864 kb
Host smart-2a9a1a6c-f42d-4c57-bf37-591527a53e23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396678468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.3396678468
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.3097314161
Short name T171
Test name
Test status
Simulation time 1395354000 ps
CPU time 1951.82 seconds
Started Jan 21 03:35:26 PM PST 24
Finished Jan 21 04:07:59 PM PST 24
Peak memory 264476 kb
Host smart-75e434f4-48f3-449f-aaa5-60a281d6beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097314161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3097314161
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.1274388139
Short name T720
Test name
Test status
Simulation time 1355392200 ps
CPU time 780.99 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:48:32 PM PST 24
Peak memory 264296 kb
Host smart-bbdfb160-b993-488b-a694-f932508282b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274388139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1274388139
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.3751658697
Short name T50
Test name
Test status
Simulation time 1600988300 ps
CPU time 26.54 seconds
Started Jan 21 03:35:22 PM PST 24
Finished Jan 21 03:35:50 PM PST 24
Peak memory 264300 kb
Host smart-1277943b-d254-456a-bf1d-b8b7b58972e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751658697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.3751658697
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.210064403
Short name T401
Test name
Test status
Simulation time 356332600 ps
CPU time 36.46 seconds
Started Jan 21 03:35:42 PM PST 24
Finished Jan 21 03:36:20 PM PST 24
Peak memory 272536 kb
Host smart-d0cb7cc3-1f17-439a-8efb-aac879bf02fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210064403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_fs_sup.210064403
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3554729420
Short name T810
Test name
Test status
Simulation time 311262168200 ps
CPU time 2165.2 seconds
Started Jan 21 04:02:02 PM PST 24
Finished Jan 21 04:38:11 PM PST 24
Peak memory 264356 kb
Host smart-d3e86be7-5211-4863-801b-1805791a2393
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554729420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3554729420
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.1117420998
Short name T883
Test name
Test status
Simulation time 193908000 ps
CPU time 48.56 seconds
Started Jan 21 03:35:13 PM PST 24
Finished Jan 21 03:36:03 PM PST 24
Peak memory 260716 kb
Host smart-600a6efa-484c-43f2-9b96-1d0e90782e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117420998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1117420998
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1561471067
Short name T89
Test name
Test status
Simulation time 10019502200 ps
CPU time 164.8 seconds
Started Jan 21 03:35:43 PM PST 24
Finished Jan 21 03:38:29 PM PST 24
Peak memory 282572 kb
Host smart-62aaab09-d4a1-44a2-891e-22fa148f63f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561471067 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1561471067
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.4001947360
Short name T337
Test name
Test status
Simulation time 25732700 ps
CPU time 13.79 seconds
Started Jan 21 04:28:10 PM PST 24
Finished Jan 21 04:28:24 PM PST 24
Peak memory 264316 kb
Host smart-2623b9c0-b1b9-4294-afe1-1b41210becb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001947360 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.4001947360
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1763060578
Short name T562
Test name
Test status
Simulation time 7291910500 ps
CPU time 41.64 seconds
Started Jan 21 04:05:29 PM PST 24
Finished Jan 21 04:06:21 PM PST 24
Peak memory 260868 kb
Host smart-50c0a476-c5ac-407e-bcac-92dcbaeba0b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763060578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1763060578
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3546254876
Short name T670
Test name
Test status
Simulation time 4926942100 ps
CPU time 177.25 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:38:26 PM PST 24
Peak memory 283340 kb
Host smart-ce860a87-aee7-4fce-a3a8-e717c171721a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546254876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3546254876
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2952220137
Short name T784
Test name
Test status
Simulation time 10184672400 ps
CPU time 218.59 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:39:10 PM PST 24
Peak memory 283012 kb
Host smart-f51a3121-f15e-4134-aa6a-7180bf827e4e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952220137 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2952220137
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.3822216279
Short name T521
Test name
Test status
Simulation time 18146360800 ps
CPU time 112 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:37:22 PM PST 24
Peak memory 264340 kb
Host smart-8434fd31-27d0-4e4b-8153-b0d2c12b2d99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822216279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.3822216279
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1972920859
Short name T630
Test name
Test status
Simulation time 100521807500 ps
CPU time 437.56 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:42:47 PM PST 24
Peak memory 264208 kb
Host smart-618c3f4e-75bc-45f4-9736-2e19b2e9a530
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197
2920859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1972920859
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.286406405
Short name T138
Test name
Test status
Simulation time 3803744500 ps
CPU time 64.46 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:36:33 PM PST 24
Peak memory 258072 kb
Host smart-66edfc58-ef45-4d7a-9e3d-5c0d649dfeda
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286406405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.286406405
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.62163460
Short name T151
Test name
Test status
Simulation time 1543661900 ps
CPU time 71.58 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:36:40 PM PST 24
Peak memory 258120 kb
Host smart-7a63b80e-81bf-4da5-a5e8-b3387a1ebc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62163460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.62163460
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2871365972
Short name T111
Test name
Test status
Simulation time 20815825400 ps
CPU time 318.17 seconds
Started Jan 21 03:35:21 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 272200 kb
Host smart-59a3e7f5-84ac-4ed5-9330-bd34fd9799ab
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871365972 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.2871365972
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.2631859977
Short name T667
Test name
Test status
Simulation time 1208727200 ps
CPU time 200.89 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:38:52 PM PST 24
Peak memory 293448 kb
Host smart-d81742bb-d694-495b-94f4-605ba3459c42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631859977 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2631859977
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2326694346
Short name T286
Test name
Test status
Simulation time 23514400 ps
CPU time 16.1 seconds
Started Jan 21 04:16:47 PM PST 24
Finished Jan 21 04:17:05 PM PST 24
Peak memory 263184 kb
Host smart-fa193639-3013-4daf-a7fa-7014d202dc8b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2326694346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2326694346
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3383269419
Short name T932
Test name
Test status
Simulation time 710783300 ps
CPU time 294.94 seconds
Started Jan 21 03:52:07 PM PST 24
Finished Jan 21 03:57:04 PM PST 24
Peak memory 260768 kb
Host smart-ff55f830-3a09-4a69-bb3b-f33059c93e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383269419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3383269419
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3995286654
Short name T884
Test name
Test status
Simulation time 95399700 ps
CPU time 18.8 seconds
Started Jan 21 03:35:44 PM PST 24
Finished Jan 21 03:36:04 PM PST 24
Peak memory 264480 kb
Host smart-8149663c-c9c3-4fdd-ad88-e9dc7a2e8bc3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995286654 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3995286654
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1281325291
Short name T931
Test name
Test status
Simulation time 31538600 ps
CPU time 13.85 seconds
Started Jan 21 03:35:43 PM PST 24
Finished Jan 21 03:35:58 PM PST 24
Peak memory 264488 kb
Host smart-fd1dcb31-a838-49c9-a5e9-98e3a3e04ae3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281325291 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1281325291
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.4076807116
Short name T608
Test name
Test status
Simulation time 89644600 ps
CPU time 13.45 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:35:44 PM PST 24
Peak memory 264372 kb
Host smart-b6c41dd4-a669-459a-b0d6-3bb535bd096e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076807116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.4076807116
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.924274191
Short name T525
Test name
Test status
Simulation time 2844008300 ps
CPU time 924.49 seconds
Started Jan 21 03:35:11 PM PST 24
Finished Jan 21 03:50:39 PM PST 24
Peak memory 282460 kb
Host smart-a1c4ebb2-88cf-48ca-a206-17d24a115a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924274191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.924274191
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1619807348
Short name T979
Test name
Test status
Simulation time 328207500 ps
CPU time 99.86 seconds
Started Jan 21 04:26:05 PM PST 24
Finished Jan 21 04:27:47 PM PST 24
Peak memory 263384 kb
Host smart-5f5d1a7d-c711-4fb1-8ccc-f8d52b81a029
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619807348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1619807348
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2709370158
Short name T907
Test name
Test status
Simulation time 261146300 ps
CPU time 35.15 seconds
Started Jan 21 03:35:41 PM PST 24
Finished Jan 21 03:36:18 PM PST 24
Peak memory 265424 kb
Host smart-e5807de9-a5a6-4c27-85e7-25bef585af33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709370158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2709370158
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1680313131
Short name T902
Test name
Test status
Simulation time 34016200 ps
CPU time 21.68 seconds
Started Jan 21 03:35:28 PM PST 24
Finished Jan 21 03:35:50 PM PST 24
Peak memory 264372 kb
Host smart-e40d2118-69be-40b1-a5dc-c51a5111c534
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680313131 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1680313131
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2833139247
Short name T863
Test name
Test status
Simulation time 90954700 ps
CPU time 23.08 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:35:51 PM PST 24
Peak memory 263108 kb
Host smart-00b6b997-4ccc-429d-909a-404a2a397429
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833139247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2833139247
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.2379310654
Short name T655
Test name
Test status
Simulation time 489654200 ps
CPU time 104.45 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:37:13 PM PST 24
Peak memory 280576 kb
Host smart-0c51f92d-91b4-40ef-87ce-ca703e07cc67
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379310654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.2379310654
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2335969321
Short name T198
Test name
Test status
Simulation time 1350045000 ps
CPU time 152.05 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:38:03 PM PST 24
Peak memory 280776 kb
Host smart-74ddf421-bb60-456e-a750-13af7a1686f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2335969321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2335969321
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2552593691
Short name T520
Test name
Test status
Simulation time 2483162900 ps
CPU time 124.27 seconds
Started Jan 21 03:35:32 PM PST 24
Finished Jan 21 03:37:37 PM PST 24
Peak memory 294116 kb
Host smart-14f5a16b-188e-4651-ae7e-0dd3ae99a1e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552593691 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2552593691
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.338778247
Short name T783
Test name
Test status
Simulation time 14253071300 ps
CPU time 503.93 seconds
Started Jan 21 03:35:27 PM PST 24
Finished Jan 21 03:43:51 PM PST 24
Peak memory 312196 kb
Host smart-e72605e1-c5b0-4db7-a724-77400b48fa17
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338778247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr
l_rw.338778247
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.1487065144
Short name T855
Test name
Test status
Simulation time 34967300 ps
CPU time 32.26 seconds
Started Jan 21 03:35:28 PM PST 24
Finished Jan 21 03:36:01 PM PST 24
Peak memory 276432 kb
Host smart-c1024290-69f1-40cb-bb9f-09c1f6c17ad1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487065144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.1487065144
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2451945995
Short name T789
Test name
Test status
Simulation time 32100400 ps
CPU time 31.85 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:36:03 PM PST 24
Peak memory 273724 kb
Host smart-6372c0a7-e96e-4035-bb0f-16a8b271e8cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451945995 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2451945995
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.702589897
Short name T7
Test name
Test status
Simulation time 3713212100 ps
CPU time 613.59 seconds
Started Jan 21 03:35:28 PM PST 24
Finished Jan 21 03:45:42 PM PST 24
Peak memory 318432 kb
Host smart-f2c0bd19-ccea-4de7-91c0-f7e3afea0342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702589897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_se
rr.702589897
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3893452297
Short name T31
Test name
Test status
Simulation time 1997387600 ps
CPU time 4949.37 seconds
Started Jan 21 03:35:45 PM PST 24
Finished Jan 21 04:58:16 PM PST 24
Peak memory 282028 kb
Host smart-329eefd6-11f9-446b-bd09-7700874306e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893452297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3893452297
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.3198440227
Short name T894
Test name
Test status
Simulation time 2567768700 ps
CPU time 71.48 seconds
Started Jan 21 03:35:42 PM PST 24
Finished Jan 21 03:36:55 PM PST 24
Peak memory 257552 kb
Host smart-8a75d971-a074-41da-b9ec-ec8a110cf567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198440227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3198440227
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1641799862
Short name T569
Test name
Test status
Simulation time 2408842000 ps
CPU time 73.85 seconds
Started Jan 21 03:35:30 PM PST 24
Finished Jan 21 03:36:45 PM PST 24
Peak memory 264440 kb
Host smart-73d23910-56f5-485e-b752-ab6f9ca8c6ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641799862 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1641799862
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.455898884
Short name T601
Test name
Test status
Simulation time 1792329400 ps
CPU time 43.52 seconds
Started Jan 21 03:50:17 PM PST 24
Finished Jan 21 03:51:03 PM PST 24
Peak memory 272600 kb
Host smart-4f0def86-6064-42b3-bc68-607a1bad5854
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455898884 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.455898884
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.968879856
Short name T1014
Test name
Test status
Simulation time 32543500 ps
CPU time 51.61 seconds
Started Jan 21 03:57:40 PM PST 24
Finished Jan 21 03:58:32 PM PST 24
Peak memory 268904 kb
Host smart-e5b886dc-830a-4be9-828e-2a355fbc83c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968879856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.968879856
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.67118552
Short name T437
Test name
Test status
Simulation time 14865900 ps
CPU time 26.08 seconds
Started Jan 21 03:57:27 PM PST 24
Finished Jan 21 03:57:54 PM PST 24
Peak memory 257976 kb
Host smart-0a6ab27d-c212-41da-bbdd-3f2f226d9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67118552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.67118552
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.968680910
Short name T800
Test name
Test status
Simulation time 187650500 ps
CPU time 845.19 seconds
Started Jan 21 03:35:40 PM PST 24
Finished Jan 21 03:49:46 PM PST 24
Peak memory 282580 kb
Host smart-f8a354b5-ed3c-46e8-a980-190e11992857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968680910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.968680910
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2569514144
Short name T461
Test name
Test status
Simulation time 42297800 ps
CPU time 26.25 seconds
Started Jan 21 03:59:25 PM PST 24
Finished Jan 21 03:59:52 PM PST 24
Peak memory 258068 kb
Host smart-6ccfe967-0346-40c8-b67f-0936ab41cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569514144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2569514144
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.403990603
Short name T453
Test name
Test status
Simulation time 1548076000 ps
CPU time 128.26 seconds
Started Jan 21 03:35:29 PM PST 24
Finished Jan 21 03:37:39 PM PST 24
Peak memory 264372 kb
Host smart-3234a8ff-ffe7-4470-b203-38c54ea941f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403990603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_wo.403990603
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.4181821547
Short name T613
Test name
Test status
Simulation time 167730700 ps
CPU time 13.86 seconds
Started Jan 21 03:44:12 PM PST 24
Finished Jan 21 03:44:26 PM PST 24
Peak memory 264368 kb
Host smart-26c5aa58-289f-4864-a7e7-c2aef62b0a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181821547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
4181821547
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3719885484
Short name T969
Test name
Test status
Simulation time 29146300 ps
CPU time 13.77 seconds
Started Jan 21 03:44:09 PM PST 24
Finished Jan 21 03:44:23 PM PST 24
Peak memory 273544 kb
Host smart-3350eede-a97a-4eb9-972a-65415fda3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719885484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3719885484
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1466762606
Short name T420
Test name
Test status
Simulation time 9364477400 ps
CPU time 153.98 seconds
Started Jan 21 03:44:00 PM PST 24
Finished Jan 21 03:46:36 PM PST 24
Peak memory 261340 kb
Host smart-ce0b1358-937a-4551-a5e5-db7152b0521f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466762606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1466762606
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2224447024
Short name T368
Test name
Test status
Simulation time 582956800 ps
CPU time 57.89 seconds
Started Jan 21 03:44:11 PM PST 24
Finished Jan 21 03:45:10 PM PST 24
Peak memory 262668 kb
Host smart-f3bd79ac-bb40-4b73-88ed-ebf1688c1eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224447024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2224447024
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1946859591
Short name T1034
Test name
Test status
Simulation time 46905600 ps
CPU time 146.24 seconds
Started Jan 21 03:43:59 PM PST 24
Finished Jan 21 03:46:27 PM PST 24
Peak memory 275992 kb
Host smart-263e432c-f1e4-4a2a-b1f8-6b63923fe1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946859591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1946859591
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.4153460124
Short name T1057
Test name
Test status
Simulation time 74594400 ps
CPU time 14.09 seconds
Started Jan 21 03:44:08 PM PST 24
Finished Jan 21 03:44:23 PM PST 24
Peak memory 264216 kb
Host smart-9bf6a74c-ccba-446e-b9aa-e76df9889f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153460124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
4153460124
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2182577851
Short name T771
Test name
Test status
Simulation time 14266300 ps
CPU time 13.35 seconds
Started Jan 21 03:44:09 PM PST 24
Finished Jan 21 03:44:23 PM PST 24
Peak memory 273588 kb
Host smart-6bb888ad-c663-4d18-8437-2d2b30168c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182577851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2182577851
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.377420446
Short name T515
Test name
Test status
Simulation time 6923178400 ps
CPU time 71.9 seconds
Started Jan 21 04:00:41 PM PST 24
Finished Jan 21 04:01:54 PM PST 24
Peak memory 261232 kb
Host smart-2f54f4ce-5716-4154-99d0-5ea9c42cc46e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377420446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.377420446
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.348459842
Short name T926
Test name
Test status
Simulation time 381191500 ps
CPU time 55.65 seconds
Started Jan 21 03:44:09 PM PST 24
Finished Jan 21 03:45:06 PM PST 24
Peak memory 260920 kb
Host smart-ba28482e-a076-4b1f-8e49-fd45e67190b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348459842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.348459842
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.459591493
Short name T960
Test name
Test status
Simulation time 44985000 ps
CPU time 96.56 seconds
Started Jan 21 03:53:55 PM PST 24
Finished Jan 21 03:55:32 PM PST 24
Peak memory 275060 kb
Host smart-52b73b0b-edd5-4704-92ba-a68e7cf8911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459591493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.459591493
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.3365374248
Short name T1043
Test name
Test status
Simulation time 25121400 ps
CPU time 13.63 seconds
Started Jan 21 03:44:32 PM PST 24
Finished Jan 21 03:44:46 PM PST 24
Peak memory 264240 kb
Host smart-3eb82549-0ab6-47e5-8fbc-32287dfeb96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365374248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
3365374248
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.877262217
Short name T1035
Test name
Test status
Simulation time 49987400 ps
CPU time 13.5 seconds
Started Jan 21 03:44:33 PM PST 24
Finished Jan 21 03:44:48 PM PST 24
Peak memory 282960 kb
Host smart-75ce3cae-de2e-4138-afe5-5f2dc6763e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877262217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.877262217
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2679103264
Short name T974
Test name
Test status
Simulation time 2669974300 ps
CPU time 100.49 seconds
Started Jan 21 03:44:12 PM PST 24
Finished Jan 21 03:45:53 PM PST 24
Peak memory 261092 kb
Host smart-f50695a1-db32-4ede-8f7d-72c7b422a166
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679103264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2679103264
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2203802774
Short name T817
Test name
Test status
Simulation time 135574400 ps
CPU time 111.48 seconds
Started Jan 21 03:44:12 PM PST 24
Finished Jan 21 03:46:04 PM PST 24
Peak memory 260608 kb
Host smart-569785fd-cee7-41d5-916b-e18cc85b9583
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203802774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2203802774
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.4059516648
Short name T946
Test name
Test status
Simulation time 1826000100 ps
CPU time 56.93 seconds
Started Jan 21 03:44:23 PM PST 24
Finished Jan 21 03:45:20 PM PST 24
Peak memory 261644 kb
Host smart-835f1d53-d716-4ed7-aae4-a38ae6c2a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059516648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.4059516648
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.3992386121
Short name T916
Test name
Test status
Simulation time 63093300 ps
CPU time 168.93 seconds
Started Jan 21 03:44:10 PM PST 24
Finished Jan 21 03:47:00 PM PST 24
Peak memory 275848 kb
Host smart-9e7db398-645d-4ea6-bd4e-0630143f6b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992386121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3992386121
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2026889022
Short name T578
Test name
Test status
Simulation time 34568900 ps
CPU time 13.63 seconds
Started Jan 21 03:44:23 PM PST 24
Finished Jan 21 03:44:38 PM PST 24
Peak memory 264424 kb
Host smart-6a688ce2-b0dc-4c6e-8b73-d9ac5f42196c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026889022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2026889022
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3894370016
Short name T22
Test name
Test status
Simulation time 16832500 ps
CPU time 13.59 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:44:39 PM PST 24
Peak memory 273504 kb
Host smart-08af6efc-f1a0-4dcc-aec8-a1fdb99765f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894370016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3894370016
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.359198890
Short name T358
Test name
Test status
Simulation time 34740100 ps
CPU time 22.57 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:44:47 PM PST 24
Peak memory 264384 kb
Host smart-dba69682-5276-488a-8f9b-def3440a004c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359198890 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.359198890
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1707042654
Short name T329
Test name
Test status
Simulation time 8361172600 ps
CPU time 133.1 seconds
Started Jan 21 03:44:22 PM PST 24
Finished Jan 21 03:46:36 PM PST 24
Peak memory 259232 kb
Host smart-de74d078-3072-4067-a26a-20b8692bf43f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707042654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1707042654
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3814519754
Short name T380
Test name
Test status
Simulation time 1527858100 ps
CPU time 68.03 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:45:32 PM PST 24
Peak memory 258088 kb
Host smart-d635ece3-8aa5-440d-acdf-8da288283762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814519754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3814519754
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.3381335791
Short name T648
Test name
Test status
Simulation time 125150600 ps
CPU time 146.44 seconds
Started Jan 21 03:44:33 PM PST 24
Finished Jan 21 03:47:01 PM PST 24
Peak memory 274472 kb
Host smart-05261514-7ba5-47d8-a0da-75f196ea59f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381335791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3381335791
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.1064964154
Short name T462
Test name
Test status
Simulation time 126649600 ps
CPU time 14.2 seconds
Started Jan 21 03:44:23 PM PST 24
Finished Jan 21 03:44:38 PM PST 24
Peak memory 264292 kb
Host smart-acd83bbb-3c3a-41c7-bba8-8cad546ad397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064964154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
1064964154
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2407744975
Short name T801
Test name
Test status
Simulation time 16107900 ps
CPU time 15.62 seconds
Started Jan 21 03:44:25 PM PST 24
Finished Jan 21 03:44:41 PM PST 24
Peak memory 273632 kb
Host smart-188846de-c9a2-4753-be49-3071f6f7999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407744975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2407744975
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.332849496
Short name T816
Test name
Test status
Simulation time 28415000 ps
CPU time 22.16 seconds
Started Jan 21 03:44:22 PM PST 24
Finished Jan 21 03:44:45 PM PST 24
Peak memory 264488 kb
Host smart-571b3244-60a8-4e1c-a466-29deec6cd160
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332849496 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.332849496
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1235118070
Short name T937
Test name
Test status
Simulation time 40060800700 ps
CPU time 159.43 seconds
Started Jan 21 03:44:33 PM PST 24
Finished Jan 21 03:47:14 PM PST 24
Peak memory 261148 kb
Host smart-60e628ea-e314-4a9e-a611-aa24734a7910
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235118070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1235118070
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1154365295
Short name T848
Test name
Test status
Simulation time 2511370900 ps
CPU time 63.77 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:45:29 PM PST 24
Peak memory 258100 kb
Host smart-9faab2f1-d045-4387-aa30-5a78d2c7b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154365295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1154365295
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.1154826709
Short name T469
Test name
Test status
Simulation time 40462500 ps
CPU time 123.82 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:46:29 PM PST 24
Peak memory 277068 kb
Host smart-b573dead-e4b2-46ff-b483-c9e09ba4cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154826709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1154826709
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.2961561925
Short name T455
Test name
Test status
Simulation time 24302900 ps
CPU time 13.54 seconds
Started Jan 21 03:44:33 PM PST 24
Finished Jan 21 03:44:47 PM PST 24
Peak memory 264400 kb
Host smart-b6868444-453c-43b7-b993-aed6950d2f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961561925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
2961561925
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.431100567
Short name T900
Test name
Test status
Simulation time 95801500 ps
CPU time 15.6 seconds
Started Jan 21 03:44:32 PM PST 24
Finished Jan 21 03:44:49 PM PST 24
Peak memory 273800 kb
Host smart-ab24b68c-5f99-49ab-8f8d-96f00bebc161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431100567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.431100567
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2602073592
Short name T356
Test name
Test status
Simulation time 21075600 ps
CPU time 21.34 seconds
Started Jan 21 03:44:32 PM PST 24
Finished Jan 21 03:44:54 PM PST 24
Peak memory 272620 kb
Host smart-c042d753-ade4-45e2-9f55-c9735202fbb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602073592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2602073592
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.524951565
Short name T991
Test name
Test status
Simulation time 2811430900 ps
CPU time 105.62 seconds
Started Jan 21 03:44:37 PM PST 24
Finished Jan 21 03:46:23 PM PST 24
Peak memory 261100 kb
Host smart-e7c3fd41-075e-4f3c-8900-1e6a019e9c9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524951565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_h
w_sec_otp.524951565
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3220814394
Short name T1036
Test name
Test status
Simulation time 592888900 ps
CPU time 67.97 seconds
Started Jan 21 03:44:32 PM PST 24
Finished Jan 21 03:45:41 PM PST 24
Peak memory 262736 kb
Host smart-c8707cfa-6c29-4aab-a5ce-53fd420cb594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220814394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3220814394
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.31879422
Short name T193
Test name
Test status
Simulation time 138225000 ps
CPU time 196.97 seconds
Started Jan 21 03:44:37 PM PST 24
Finished Jan 21 03:47:55 PM PST 24
Peak memory 275224 kb
Host smart-f538ac49-aa1f-47b1-a7c5-a069838e49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31879422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.31879422
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1756345938
Short name T173
Test name
Test status
Simulation time 95343700 ps
CPU time 13.5 seconds
Started Jan 21 03:44:46 PM PST 24
Finished Jan 21 03:45:01 PM PST 24
Peak memory 264100 kb
Host smart-4abf6111-7a3b-464a-9dad-61b3a3893d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756345938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1756345938
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.365103262
Short name T940
Test name
Test status
Simulation time 24423400 ps
CPU time 13.38 seconds
Started Jan 21 03:44:34 PM PST 24
Finished Jan 21 03:44:48 PM PST 24
Peak memory 282768 kb
Host smart-bcd0ec27-a699-409a-a4ea-253f92cd2aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365103262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.365103262
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3138938007
Short name T35
Test name
Test status
Simulation time 20079900 ps
CPU time 20.9 seconds
Started Jan 21 03:44:32 PM PST 24
Finished Jan 21 03:44:54 PM PST 24
Peak memory 264404 kb
Host smart-74d59f2f-f107-4270-acc7-bd66c05b265c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138938007 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3138938007
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3884621324
Short name T890
Test name
Test status
Simulation time 15759538200 ps
CPU time 62.46 seconds
Started Jan 21 03:44:35 PM PST 24
Finished Jan 21 03:45:39 PM PST 24
Peak memory 261128 kb
Host smart-01785e99-efa3-4675-b05a-9e21352f711c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884621324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3884621324
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3999225429
Short name T996
Test name
Test status
Simulation time 263898900 ps
CPU time 131.66 seconds
Started Jan 21 03:44:37 PM PST 24
Finished Jan 21 03:46:49 PM PST 24
Peak memory 258664 kb
Host smart-6fdc1234-f1db-419c-9529-6bc82c61f47e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999225429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3999225429
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.1417048347
Short name T956
Test name
Test status
Simulation time 9238519100 ps
CPU time 76.11 seconds
Started Jan 21 03:44:34 PM PST 24
Finished Jan 21 03:45:51 PM PST 24
Peak memory 261368 kb
Host smart-321fb189-c913-43c1-8244-79f131ecadf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417048347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1417048347
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3032093115
Short name T806
Test name
Test status
Simulation time 333610800 ps
CPU time 73.15 seconds
Started Jan 21 03:44:38 PM PST 24
Finished Jan 21 03:45:52 PM PST 24
Peak memory 264380 kb
Host smart-799b192d-a083-483d-84ba-2637d17676c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032093115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3032093115
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3960071579
Short name T553
Test name
Test status
Simulation time 32983700 ps
CPU time 13.79 seconds
Started Jan 21 03:44:46 PM PST 24
Finished Jan 21 03:45:01 PM PST 24
Peak memory 264272 kb
Host smart-53be863c-69b6-48e1-be95-df4caeeeb5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960071579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3960071579
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.845726153
Short name T715
Test name
Test status
Simulation time 42876800 ps
CPU time 13.65 seconds
Started Jan 21 03:44:44 PM PST 24
Finished Jan 21 03:44:59 PM PST 24
Peak memory 273428 kb
Host smart-71cbab91-2358-4d9f-8b44-4ef48dd29105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845726153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.845726153
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2235085839
Short name T983
Test name
Test status
Simulation time 164849900 ps
CPU time 22.88 seconds
Started Jan 21 03:44:45 PM PST 24
Finished Jan 21 03:45:09 PM PST 24
Peak memory 264344 kb
Host smart-c077ef06-27f0-4a70-8c0b-87bec330208d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235085839 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2235085839
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2019632797
Short name T539
Test name
Test status
Simulation time 1169596200 ps
CPU time 102.99 seconds
Started Jan 21 03:44:48 PM PST 24
Finished Jan 21 03:46:32 PM PST 24
Peak memory 261436 kb
Host smart-8f916544-43b2-43af-97e9-4ab01ef62df4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019632797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2019632797
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.3616771386
Short name T375
Test name
Test status
Simulation time 7056889200 ps
CPU time 73.11 seconds
Started Jan 21 03:44:46 PM PST 24
Finished Jan 21 03:46:00 PM PST 24
Peak memory 258100 kb
Host smart-e44d839b-212a-4dca-8397-e2452905f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616771386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3616771386
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.750869806
Short name T1050
Test name
Test status
Simulation time 53638900 ps
CPU time 99.7 seconds
Started Jan 21 03:44:44 PM PST 24
Finished Jan 21 03:46:24 PM PST 24
Peak memory 274376 kb
Host smart-270efb6c-1fbf-4ae2-b6c4-260d58a23c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750869806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.750869806
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1703564084
Short name T618
Test name
Test status
Simulation time 180699700 ps
CPU time 13.78 seconds
Started Jan 21 03:44:58 PM PST 24
Finished Jan 21 03:45:13 PM PST 24
Peak memory 264416 kb
Host smart-442a928c-63ad-4ecc-8e54-9fa561e01ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703564084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1703564084
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.2417734512
Short name T764
Test name
Test status
Simulation time 45974000 ps
CPU time 15.95 seconds
Started Jan 21 03:44:56 PM PST 24
Finished Jan 21 03:45:13 PM PST 24
Peak memory 273536 kb
Host smart-d70f7964-1f66-4ba6-928a-1d2087515771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417734512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2417734512
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1624426631
Short name T971
Test name
Test status
Simulation time 40189500 ps
CPU time 22.18 seconds
Started Jan 21 03:44:59 PM PST 24
Finished Jan 21 03:45:22 PM PST 24
Peak memory 264368 kb
Host smart-ce70912e-740d-4757-bffe-92af044e1af1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624426631 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1624426631
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.624173549
Short name T867
Test name
Test status
Simulation time 613094900 ps
CPU time 33.86 seconds
Started Jan 21 03:44:47 PM PST 24
Finished Jan 21 03:45:22 PM PST 24
Peak memory 261140 kb
Host smart-0c08f542-c92a-48c6-bdc7-db3ac677bb9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624173549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.624173549
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.1614046289
Short name T1022
Test name
Test status
Simulation time 90945800 ps
CPU time 131.6 seconds
Started Jan 21 03:44:45 PM PST 24
Finished Jan 21 03:46:58 PM PST 24
Peak memory 258472 kb
Host smart-843d0a69-ae31-4765-8cfa-9df1254031a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614046289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.1614046289
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.1009453056
Short name T168
Test name
Test status
Simulation time 2591556400 ps
CPU time 79.79 seconds
Started Jan 21 03:44:57 PM PST 24
Finished Jan 21 03:46:18 PM PST 24
Peak memory 258124 kb
Host smart-97d4c6e3-a6cf-4755-8b9b-f69a16492710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009453056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1009453056
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.1420180746
Short name T540
Test name
Test status
Simulation time 31219800 ps
CPU time 124.42 seconds
Started Jan 21 03:44:47 PM PST 24
Finished Jan 21 03:46:52 PM PST 24
Peak memory 277164 kb
Host smart-7f4d80cd-4e2a-49e1-9dd3-39b1b9d3479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420180746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1420180746
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.612887163
Short name T435
Test name
Test status
Simulation time 59139600 ps
CPU time 13.27 seconds
Started Jan 21 03:45:00 PM PST 24
Finished Jan 21 03:45:14 PM PST 24
Peak memory 264384 kb
Host smart-17ee7e2f-b7ad-4c26-ae6b-f4a16281b895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612887163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.612887163
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.692380855
Short name T534
Test name
Test status
Simulation time 17484700 ps
CPU time 13.43 seconds
Started Jan 21 03:45:00 PM PST 24
Finished Jan 21 03:45:15 PM PST 24
Peak memory 273516 kb
Host smart-66f60821-806b-409a-8894-eec1c6e36a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692380855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.692380855
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.4072986035
Short name T554
Test name
Test status
Simulation time 11475300 ps
CPU time 20.53 seconds
Started Jan 21 03:45:03 PM PST 24
Finished Jan 21 03:45:24 PM PST 24
Peak memory 264416 kb
Host smart-bb0805ab-bc88-46c1-996e-6ee5c849a543
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072986035 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.4072986035
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1311596396
Short name T436
Test name
Test status
Simulation time 3725338000 ps
CPU time 96.19 seconds
Started Jan 21 03:45:01 PM PST 24
Finished Jan 21 03:46:38 PM PST 24
Peak memory 261096 kb
Host smart-5983a122-2e86-41a0-a4f3-86d9ed61495a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311596396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.1311596396
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.738366937
Short name T394
Test name
Test status
Simulation time 630070900 ps
CPU time 60.23 seconds
Started Jan 21 03:45:02 PM PST 24
Finished Jan 21 03:46:03 PM PST 24
Peak memory 261384 kb
Host smart-0e45958a-1f8e-43a2-822a-a6ecca5830a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738366937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.738366937
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1619847897
Short name T695
Test name
Test status
Simulation time 28830000 ps
CPU time 96.58 seconds
Started Jan 21 03:45:01 PM PST 24
Finished Jan 21 03:46:38 PM PST 24
Peak memory 273624 kb
Host smart-bcf7ae48-f39b-4d6f-89f1-bba3add3c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619847897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1619847897
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.724237137
Short name T795
Test name
Test status
Simulation time 286013700 ps
CPU time 14.25 seconds
Started Jan 21 04:13:27 PM PST 24
Finished Jan 21 04:13:45 PM PST 24
Peak memory 264268 kb
Host smart-93a73157-6690-418f-8b60-de0b7b57e97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724237137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.724237137
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1212812460
Short name T184
Test name
Test status
Simulation time 15874200 ps
CPU time 16.04 seconds
Started Jan 21 03:36:08 PM PST 24
Finished Jan 21 03:36:25 PM PST 24
Peak memory 273472 kb
Host smart-b58552f5-9591-47d5-95cc-ef669119975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212812460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1212812460
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2800928361
Short name T780
Test name
Test status
Simulation time 10806376300 ps
CPU time 2363.07 seconds
Started Jan 21 03:35:49 PM PST 24
Finished Jan 21 04:15:14 PM PST 24
Peak memory 264296 kb
Host smart-b9265680-939a-4bd7-88f2-3b80c01679ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800928361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2800928361
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.3153545546
Short name T703
Test name
Test status
Simulation time 1792043000 ps
CPU time 923.23 seconds
Started Jan 21 03:35:50 PM PST 24
Finished Jan 21 03:51:15 PM PST 24
Peak memory 264276 kb
Host smart-9411f295-be62-45e1-af0d-375cad4d5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153545546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3153545546
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2693844153
Short name T44
Test name
Test status
Simulation time 280273700 ps
CPU time 23.26 seconds
Started Jan 21 03:35:49 PM PST 24
Finished Jan 21 03:36:14 PM PST 24
Peak memory 264256 kb
Host smart-4af30c50-6e67-4cdb-86c4-2d6277c6c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693844153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2693844153
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.4275509699
Short name T83
Test name
Test status
Simulation time 26013800 ps
CPU time 13.46 seconds
Started Jan 21 03:36:07 PM PST 24
Finished Jan 21 03:36:21 PM PST 24
Peak memory 264256 kb
Host smart-252940ef-67a0-4b07-8509-692394143729
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275509699 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.4275509699
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3090770141
Short name T1004
Test name
Test status
Simulation time 130174379800 ps
CPU time 796.72 seconds
Started Jan 21 03:35:50 PM PST 24
Finished Jan 21 03:49:08 PM PST 24
Peak memory 262424 kb
Host smart-92df6cb2-5e9d-4b88-b380-c5d324f877d3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090770141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3090770141
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2381736894
Short name T659
Test name
Test status
Simulation time 4357641500 ps
CPU time 118.32 seconds
Started Jan 21 03:35:51 PM PST 24
Finished Jan 21 03:37:50 PM PST 24
Peak memory 261160 kb
Host smart-4d580403-dcdc-482d-9cea-065db59a13c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381736894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.2381736894
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.3059576339
Short name T501
Test name
Test status
Simulation time 1319698300 ps
CPU time 160.49 seconds
Started Jan 21 03:36:01 PM PST 24
Finished Jan 21 03:38:43 PM PST 24
Peak memory 292360 kb
Host smart-0d863e5d-9cea-4bcb-a66c-50db83ac146a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059576339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.3059576339
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3982383868
Short name T1030
Test name
Test status
Simulation time 8198330900 ps
CPU time 222.44 seconds
Started Jan 21 03:36:06 PM PST 24
Finished Jan 21 03:39:50 PM PST 24
Peak memory 282952 kb
Host smart-da220bea-6a04-4573-b710-21f571499d98
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982383868 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3982383868
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2073450109
Short name T892
Test name
Test status
Simulation time 5727858000 ps
CPU time 112.98 seconds
Started Jan 21 03:36:00 PM PST 24
Finished Jan 21 03:37:55 PM PST 24
Peak memory 264284 kb
Host smart-81c3ed29-53d5-4541-92b1-f01a2ef2aece
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073450109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2073450109
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.677282359
Short name T792
Test name
Test status
Simulation time 177471300100 ps
CPU time 582.88 seconds
Started Jan 21 03:36:05 PM PST 24
Finished Jan 21 03:45:48 PM PST 24
Peak memory 264352 kb
Host smart-c68d5fd0-8c31-4a25-87b7-ad47d0f4f233
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677
282359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.677282359
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.2957768847
Short name T117
Test name
Test status
Simulation time 3869661300 ps
CPU time 90.18 seconds
Started Jan 21 03:35:51 PM PST 24
Finished Jan 21 03:37:22 PM PST 24
Peak memory 257736 kb
Host smart-96396e44-5d21-4fbf-a9c0-5b0cce8417e0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957768847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2957768847
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.891321748
Short name T610
Test name
Test status
Simulation time 25178000 ps
CPU time 13.64 seconds
Started Jan 21 03:36:08 PM PST 24
Finished Jan 21 03:36:23 PM PST 24
Peak memory 264336 kb
Host smart-71828d53-8455-4363-9de5-2d73f17075db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891321748 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.891321748
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2651943732
Short name T109
Test name
Test status
Simulation time 41023556900 ps
CPU time 802.47 seconds
Started Jan 21 03:58:01 PM PST 24
Finished Jan 21 04:11:24 PM PST 24
Peak memory 271088 kb
Host smart-4e9d784c-8b70-4cd2-b143-6e94255cf1df
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651943732 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2651943732
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1573277642
Short name T698
Test name
Test status
Simulation time 26660400 ps
CPU time 68.98 seconds
Started Jan 21 03:35:50 PM PST 24
Finished Jan 21 03:37:01 PM PST 24
Peak memory 263368 kb
Host smart-05c2de22-a6db-44b5-8ce6-daf93646f00d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573277642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1573277642
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.1609279825
Short name T413
Test name
Test status
Simulation time 75495600 ps
CPU time 13.66 seconds
Started Jan 21 03:36:04 PM PST 24
Finished Jan 21 03:36:18 PM PST 24
Peak memory 264308 kb
Host smart-7a171aca-9c89-4d91-9495-a96f8370c535
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609279825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.1609279825
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.150982409
Short name T127
Test name
Test status
Simulation time 3156918900 ps
CPU time 609.76 seconds
Started Jan 21 03:35:50 PM PST 24
Finished Jan 21 03:46:01 PM PST 24
Peak memory 280780 kb
Host smart-a6bd0acd-5968-46f3-a70a-cfab9f2f90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150982409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.150982409
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2139771512
Short name T128
Test name
Test status
Simulation time 721804200 ps
CPU time 38.09 seconds
Started Jan 21 03:36:09 PM PST 24
Finished Jan 21 03:36:49 PM PST 24
Peak memory 265468 kb
Host smart-e061c04f-a4a6-42a4-9e92-a45aabdde889
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139771512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2139771512
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.4049020410
Short name T210
Test name
Test status
Simulation time 924271200 ps
CPU time 102.42 seconds
Started Jan 21 03:35:49 PM PST 24
Finished Jan 21 03:37:33 PM PST 24
Peak memory 280556 kb
Host smart-32e2bda0-4be3-4a55-bcd4-0022c6e7d62c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049020410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.4049020410
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.364131830
Short name T208
Test name
Test status
Simulation time 4470508800 ps
CPU time 141.42 seconds
Started Jan 21 03:36:10 PM PST 24
Finished Jan 21 03:38:33 PM PST 24
Peak memory 280784 kb
Host smart-f19f9ba6-1f9d-4365-8c5f-3d8283661889
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
364131830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.364131830
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.351852130
Short name T51
Test name
Test status
Simulation time 7877293600 ps
CPU time 532.24 seconds
Started Jan 21 03:35:49 PM PST 24
Finished Jan 21 03:44:43 PM PST 24
Peak memory 311848 kb
Host smart-fe103bc3-02cc-405a-897b-42b8f7fcbdb7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351852130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctr
l_rw.351852130
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.1203174097
Short name T383
Test name
Test status
Simulation time 3473962900 ps
CPU time 530.18 seconds
Started Jan 21 03:36:06 PM PST 24
Finished Jan 21 03:44:57 PM PST 24
Peak memory 325964 kb
Host smart-736cbfad-4f60-4fbb-bf67-af1bc0442296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203174097 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.1203174097
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.2181003155
Short name T696
Test name
Test status
Simulation time 103675000 ps
CPU time 32.25 seconds
Started Jan 21 03:36:04 PM PST 24
Finished Jan 21 03:36:37 PM PST 24
Peak memory 270940 kb
Host smart-a35e30c5-131e-4645-a95e-86547fc59601
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181003155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.2181003155
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3424203415
Short name T289
Test name
Test status
Simulation time 71529200 ps
CPU time 31.72 seconds
Started Jan 21 03:36:08 PM PST 24
Finished Jan 21 03:36:40 PM PST 24
Peak memory 272692 kb
Host smart-987d9491-6ed7-415c-a061-076d82deaa9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424203415 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3424203415
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1784252471
Short name T72
Test name
Test status
Simulation time 6381512700 ps
CPU time 513.77 seconds
Started Jan 21 03:36:04 PM PST 24
Finished Jan 21 03:44:39 PM PST 24
Peak memory 318452 kb
Host smart-2be99744-9931-498c-9545-0db5f44afecf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784252471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.1784252471
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3386457783
Short name T699
Test name
Test status
Simulation time 7063724900 ps
CPU time 70.15 seconds
Started Jan 21 03:53:49 PM PST 24
Finished Jan 21 03:55:01 PM PST 24
Peak memory 258164 kb
Host smart-dd9869fc-7f65-422c-8203-9575e2884d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386457783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3386457783
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3014339386
Short name T631
Test name
Test status
Simulation time 1850299800 ps
CPU time 150.5 seconds
Started Jan 21 03:35:51 PM PST 24
Finished Jan 21 03:38:22 PM PST 24
Peak memory 264052 kb
Host smart-e6b36e7b-4a8a-4b54-b79a-695016103da3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014339386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.3014339386
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.4195632221
Short name T767
Test name
Test status
Simulation time 45875900 ps
CPU time 15.87 seconds
Started Jan 21 03:44:59 PM PST 24
Finished Jan 21 03:45:15 PM PST 24
Peak memory 273748 kb
Host smart-d0ede280-965c-4f36-885a-7d53896734e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195632221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.4195632221
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3663142101
Short name T545
Test name
Test status
Simulation time 145512900 ps
CPU time 129.64 seconds
Started Jan 21 03:45:04 PM PST 24
Finished Jan 21 03:47:14 PM PST 24
Peak memory 259388 kb
Host smart-bf54e6ad-e7e8-461e-9b6d-0c731c17ce6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663142101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3663142101
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.2046534097
Short name T1051
Test name
Test status
Simulation time 69347000 ps
CPU time 13.47 seconds
Started Jan 21 03:45:02 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 273740 kb
Host smart-d709e5f2-f2dd-46b5-a0c7-2add225a2aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046534097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2046534097
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3227615860
Short name T752
Test name
Test status
Simulation time 75884700 ps
CPU time 111.02 seconds
Started Jan 21 03:45:03 PM PST 24
Finished Jan 21 03:46:55 PM PST 24
Peak memory 258480 kb
Host smart-ca381aad-9202-4c4f-8b8f-7b1b075e19f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227615860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3227615860
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.676686982
Short name T790
Test name
Test status
Simulation time 40156500 ps
CPU time 16.13 seconds
Started Jan 21 03:44:59 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 273652 kb
Host smart-2e60b838-fd9a-4d8e-88c8-e68ec8ed91b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676686982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.676686982
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.4057949072
Short name T359
Test name
Test status
Simulation time 237595200 ps
CPU time 13.54 seconds
Started Jan 21 03:45:01 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 273736 kb
Host smart-079f5d3c-24ac-4a9b-ba74-bd8b4e1838db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057949072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.4057949072
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.3003855540
Short name T544
Test name
Test status
Simulation time 71353700 ps
CPU time 131.43 seconds
Started Jan 21 03:44:59 PM PST 24
Finished Jan 21 03:47:12 PM PST 24
Peak memory 258500 kb
Host smart-295dae8c-252a-46e9-872f-c70455fead76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003855540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.3003855540
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.3706142964
Short name T542
Test name
Test status
Simulation time 13269900 ps
CPU time 15.55 seconds
Started Jan 21 03:45:09 PM PST 24
Finished Jan 21 03:45:25 PM PST 24
Peak memory 273544 kb
Host smart-58a3d221-7499-4dbc-b19a-84807f5225a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706142964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3706142964
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.3188531605
Short name T634
Test name
Test status
Simulation time 53700500 ps
CPU time 15.99 seconds
Started Jan 21 04:09:02 PM PST 24
Finished Jan 21 04:09:20 PM PST 24
Peak memory 273632 kb
Host smart-7970d911-562e-4fc8-92bf-3bee59cf26f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188531605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3188531605
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1733082954
Short name T1001
Test name
Test status
Simulation time 148189300 ps
CPU time 110.81 seconds
Started Jan 21 03:45:06 PM PST 24
Finished Jan 21 03:46:58 PM PST 24
Peak memory 259372 kb
Host smart-befc8227-e48e-4c50-85f1-9813058ec10d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733082954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1733082954
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2791307253
Short name T649
Test name
Test status
Simulation time 46545500 ps
CPU time 16.01 seconds
Started Jan 21 03:45:02 PM PST 24
Finished Jan 21 03:45:19 PM PST 24
Peak memory 273600 kb
Host smart-f0481a9a-4c9b-48f5-badd-7704fd1e0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791307253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2791307253
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3610161358
Short name T442
Test name
Test status
Simulation time 40586900 ps
CPU time 16.23 seconds
Started Jan 21 04:14:36 PM PST 24
Finished Jan 21 04:14:53 PM PST 24
Peak memory 282908 kb
Host smart-2f42974d-2b47-4f71-a481-5306e25ed1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610161358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3610161358
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3402100279
Short name T957
Test name
Test status
Simulation time 70097200 ps
CPU time 133.07 seconds
Started Jan 21 03:45:06 PM PST 24
Finished Jan 21 03:47:20 PM PST 24
Peak memory 258032 kb
Host smart-eb3c4e95-73a6-4ec4-b8fb-0f61251eefe6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402100279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3402100279
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2368745802
Short name T537
Test name
Test status
Simulation time 25169000 ps
CPU time 15.8 seconds
Started Jan 21 03:45:10 PM PST 24
Finished Jan 21 03:45:27 PM PST 24
Peak memory 273440 kb
Host smart-1abaa968-9b1c-42f9-a86f-2ef73b8e9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368745802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2368745802
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.1389385293
Short name T602
Test name
Test status
Simulation time 15782600 ps
CPU time 15.34 seconds
Started Jan 21 03:45:09 PM PST 24
Finished Jan 21 03:45:25 PM PST 24
Peak memory 273692 kb
Host smart-8c2dee25-fb77-4e75-9710-ac61723960d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389385293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.1389385293
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3662854492
Short name T742
Test name
Test status
Simulation time 184765400 ps
CPU time 14.35 seconds
Started Jan 21 03:36:36 PM PST 24
Finished Jan 21 03:36:54 PM PST 24
Peak memory 264420 kb
Host smart-2170ade1-ef86-410d-9c7f-ad846caf9577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662854492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
662854492
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3056853138
Short name T463
Test name
Test status
Simulation time 30123700 ps
CPU time 15.6 seconds
Started Jan 21 03:36:34 PM PST 24
Finished Jan 21 03:36:55 PM PST 24
Peak memory 273680 kb
Host smart-cc6a64c1-2c6a-46df-ade2-eca90586eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056853138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3056853138
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.1191238322
Short name T1055
Test name
Test status
Simulation time 13665905500 ps
CPU time 2170.32 seconds
Started Jan 21 03:36:16 PM PST 24
Finished Jan 21 04:12:28 PM PST 24
Peak memory 264152 kb
Host smart-6fbf5338-6d63-4d5a-84c5-8c967377cd47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191238322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.1191238322
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.1064613727
Short name T6
Test name
Test status
Simulation time 742590700 ps
CPU time 1012.55 seconds
Started Jan 21 03:36:06 PM PST 24
Finished Jan 21 03:53:00 PM PST 24
Peak memory 272496 kb
Host smart-a0a8585f-a3b7-4966-a633-1b1d441ee5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064613727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1064613727
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2916276154
Short name T739
Test name
Test status
Simulation time 1015140800 ps
CPU time 24.77 seconds
Started Jan 21 05:05:11 PM PST 24
Finished Jan 21 05:05:36 PM PST 24
Peak memory 264296 kb
Host smart-5d5829a7-c72e-47ed-be34-b0d49748c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916276154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2916276154
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3606553086
Short name T929
Test name
Test status
Simulation time 10033286200 ps
CPU time 109.47 seconds
Started Jan 21 03:36:34 PM PST 24
Finished Jan 21 03:38:29 PM PST 24
Peak memory 272628 kb
Host smart-059714f1-d5ac-44c1-a897-34dbe66567c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606553086 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3606553086
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.2190693399
Short name T155
Test name
Test status
Simulation time 16371700 ps
CPU time 13.53 seconds
Started Jan 21 03:36:37 PM PST 24
Finished Jan 21 03:36:54 PM PST 24
Peak memory 263492 kb
Host smart-92b21b98-57e9-407b-87ad-8852ba75a11f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190693399 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2190693399
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2108914376
Short name T626
Test name
Test status
Simulation time 40121564300 ps
CPU time 775.72 seconds
Started Jan 21 03:36:08 PM PST 24
Finished Jan 21 03:49:05 PM PST 24
Peak memory 262788 kb
Host smart-0dd1711f-59b4-43bc-b8a1-5941df44aef8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108914376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.2108914376
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3981268704
Short name T423
Test name
Test status
Simulation time 3966415500 ps
CPU time 142.71 seconds
Started Jan 21 03:36:06 PM PST 24
Finished Jan 21 03:38:30 PM PST 24
Peak memory 261280 kb
Host smart-c41ee465-6980-4514-a79a-995b37fb2ee4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981268704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3981268704
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.714537782
Short name T661
Test name
Test status
Simulation time 1188702600 ps
CPU time 162.35 seconds
Started Jan 21 03:36:28 PM PST 24
Finished Jan 21 03:39:19 PM PST 24
Peak memory 291136 kb
Host smart-73f454d7-f827-469d-b8a5-2f80f0138ea1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714537782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.714537782
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1258584430
Short name T522
Test name
Test status
Simulation time 64022717300 ps
CPU time 267.81 seconds
Started Jan 21 03:36:27 PM PST 24
Finished Jan 21 03:41:04 PM PST 24
Peak memory 282944 kb
Host smart-acbf53c8-785d-4f86-9e26-d0289bca08b2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258584430 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1258584430
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1104346149
Short name T725
Test name
Test status
Simulation time 15799784900 ps
CPU time 99.79 seconds
Started Jan 21 03:36:30 PM PST 24
Finished Jan 21 03:38:16 PM PST 24
Peak memory 264340 kb
Host smart-23dde7c2-daa4-4e84-96fb-085370cb8a39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104346149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1104346149
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3232339173
Short name T947
Test name
Test status
Simulation time 304550459900 ps
CPU time 747.89 seconds
Started Jan 21 03:36:31 PM PST 24
Finished Jan 21 03:49:06 PM PST 24
Peak memory 264308 kb
Host smart-37c0ff28-c61d-4839-a72f-1e3931667552
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323
2339173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3232339173
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.554783420
Short name T709
Test name
Test status
Simulation time 4054548700 ps
CPU time 78.01 seconds
Started Jan 21 03:51:42 PM PST 24
Finished Jan 21 03:53:00 PM PST 24
Peak memory 258092 kb
Host smart-86fef76b-dd71-495e-a293-668acd148e00
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554783420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.554783420
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.4212494117
Short name T187
Test name
Test status
Simulation time 21381800 ps
CPU time 13.36 seconds
Started Jan 21 03:36:37 PM PST 24
Finished Jan 21 03:36:54 PM PST 24
Peak memory 264328 kb
Host smart-68a82e25-31f2-4c9e-94f7-c5a6e784d954
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212494117 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.4212494117
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3458954800
Short name T139
Test name
Test status
Simulation time 107644560700 ps
CPU time 395.47 seconds
Started Jan 21 03:36:10 PM PST 24
Finished Jan 21 03:42:47 PM PST 24
Peak memory 271732 kb
Host smart-2a560701-f413-48f5-b1d6-10659f2fd1d0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458954800 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3458954800
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3236567535
Short name T658
Test name
Test status
Simulation time 103774000 ps
CPU time 150.13 seconds
Started Jan 21 03:36:10 PM PST 24
Finished Jan 21 03:38:41 PM PST 24
Peak memory 264256 kb
Host smart-ca5cf8d2-3a0e-46f8-8fd6-7f5d46de524a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236567535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3236567535
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1940100968
Short name T334
Test name
Test status
Simulation time 27499700 ps
CPU time 14.17 seconds
Started Jan 21 03:36:26 PM PST 24
Finished Jan 21 03:36:50 PM PST 24
Peak memory 264304 kb
Host smart-6862f22f-06c6-42ab-8496-74db74cb80b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940100968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1940100968
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3555385621
Short name T34
Test name
Test status
Simulation time 134688300 ps
CPU time 826.55 seconds
Started Jan 21 03:36:14 PM PST 24
Finished Jan 21 03:50:01 PM PST 24
Peak memory 281648 kb
Host smart-271f39f0-bbf2-42b7-b5b5-5b4ead8e9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555385621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3555385621
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.529175252
Short name T674
Test name
Test status
Simulation time 180403100 ps
CPU time 36.53 seconds
Started Jan 21 03:36:29 PM PST 24
Finished Jan 21 03:37:13 PM PST 24
Peak memory 270840 kb
Host smart-99bbf18f-a4e6-4d13-bd98-b064bdd16600
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529175252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.529175252
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.248525053
Short name T680
Test name
Test status
Simulation time 880619800 ps
CPU time 97.54 seconds
Started Jan 21 03:36:17 PM PST 24
Finished Jan 21 03:37:55 PM PST 24
Peak memory 288784 kb
Host smart-080c2a30-90fa-4c27-adad-8578052e5ebf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248525053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_ro.248525053
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.1926403481
Short name T818
Test name
Test status
Simulation time 645923600 ps
CPU time 148.57 seconds
Started Jan 21 03:36:20 PM PST 24
Finished Jan 21 03:38:50 PM PST 24
Peak memory 280804 kb
Host smart-2e48739a-6651-4d2f-ad6a-a0755284cfbd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1926403481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1926403481
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.659614912
Short name T620
Test name
Test status
Simulation time 712618300 ps
CPU time 142.8 seconds
Started Jan 21 03:36:26 PM PST 24
Finished Jan 21 03:38:59 PM PST 24
Peak memory 292528 kb
Host smart-8f8ecd92-eb8a-45ee-8d70-6f7358313118
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659614912 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.659614912
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.305766331
Short name T785
Test name
Test status
Simulation time 3772824000 ps
CPU time 481.17 seconds
Started Jan 21 03:36:23 PM PST 24
Finished Jan 21 03:44:26 PM PST 24
Peak memory 313396 kb
Host smart-f41d4463-8fe7-4531-9d14-51924dfe2aab
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305766331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr
l_rw.305766331
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.2292092024
Short name T1046
Test name
Test status
Simulation time 29374600 ps
CPU time 31.94 seconds
Started Jan 21 03:36:26 PM PST 24
Finished Jan 21 03:37:08 PM PST 24
Peak memory 270968 kb
Host smart-bf020d87-d5fc-49a5-9de7-7daafda041a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292092024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.2292092024
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2657308310
Short name T63
Test name
Test status
Simulation time 209877300 ps
CPU time 32.75 seconds
Started Jan 21 03:36:28 PM PST 24
Finished Jan 21 03:37:09 PM PST 24
Peak memory 272636 kb
Host smart-5741efde-3dda-4e9e-bbe9-e2201f14d41d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657308310 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.2657308310
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.2536197119
Short name T557
Test name
Test status
Simulation time 23190030200 ps
CPU time 628.75 seconds
Started Jan 21 03:36:24 PM PST 24
Finished Jan 21 03:46:54 PM PST 24
Peak memory 310264 kb
Host smart-06e98cc2-e07f-492a-851b-983aae07b3e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536197119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.2536197119
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3244861250
Short name T834
Test name
Test status
Simulation time 4250992600 ps
CPU time 67.57 seconds
Started Jan 21 03:36:34 PM PST 24
Finished Jan 21 03:37:47 PM PST 24
Peak memory 261300 kb
Host smart-ddbbc3dd-3a35-45a7-b025-4080579fc62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244861250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3244861250
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1819733624
Short name T1023
Test name
Test status
Simulation time 36895600 ps
CPU time 76 seconds
Started Jan 21 03:36:14 PM PST 24
Finished Jan 21 03:37:31 PM PST 24
Peak memory 273052 kb
Host smart-adbceea5-c771-4eec-a607-269185ce779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819733624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1819733624
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.2876894927
Short name T489
Test name
Test status
Simulation time 3922815300 ps
CPU time 166.8 seconds
Started Jan 21 03:36:19 PM PST 24
Finished Jan 21 03:39:06 PM PST 24
Peak memory 264284 kb
Host smart-d74be389-200c-4bca-b22e-a4f47fc930cf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876894927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.2876894927
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.4199012817
Short name T422
Test name
Test status
Simulation time 36935300 ps
CPU time 13.41 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:02:59 PM PST 24
Peak memory 273516 kb
Host smart-615ade43-8f5f-4ea9-a71e-24a8f77cb6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199012817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.4199012817
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1332216808
Short name T190
Test name
Test status
Simulation time 46942800 ps
CPU time 15.62 seconds
Started Jan 21 03:51:52 PM PST 24
Finished Jan 21 03:52:08 PM PST 24
Peak memory 273488 kb
Host smart-7008472f-84f9-4e7c-bd45-24a21a1330a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332216808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1332216808
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3612031424
Short name T186
Test name
Test status
Simulation time 39906900 ps
CPU time 130.15 seconds
Started Jan 21 03:59:03 PM PST 24
Finished Jan 21 04:01:18 PM PST 24
Peak memory 258040 kb
Host smart-21e77c6c-3a0d-4ba9-8322-f2c20b369db4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612031424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3612031424
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3165939718
Short name T912
Test name
Test status
Simulation time 16033100 ps
CPU time 15.81 seconds
Started Jan 21 03:45:13 PM PST 24
Finished Jan 21 03:45:29 PM PST 24
Peak memory 283000 kb
Host smart-8997cdf4-4948-48ca-9642-1e990937173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165939718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3165939718
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1704525099
Short name T704
Test name
Test status
Simulation time 169267600 ps
CPU time 15.6 seconds
Started Jan 21 03:45:08 PM PST 24
Finished Jan 21 03:45:25 PM PST 24
Peak memory 273528 kb
Host smart-300b317d-8aa8-433f-803c-b41febd32ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704525099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1704525099
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.365807930
Short name T43
Test name
Test status
Simulation time 42673400 ps
CPU time 130.12 seconds
Started Jan 21 03:45:10 PM PST 24
Finished Jan 21 03:47:21 PM PST 24
Peak memory 258488 kb
Host smart-212c6484-0689-4f75-b5c7-6e6a82b8c77d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365807930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.365807930
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1424147020
Short name T541
Test name
Test status
Simulation time 15277900 ps
CPU time 15.66 seconds
Started Jan 21 03:45:09 PM PST 24
Finished Jan 21 03:45:26 PM PST 24
Peak memory 273604 kb
Host smart-cbdb8e80-1d1e-4954-9b0b-c985172ef84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424147020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1424147020
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1218784059
Short name T906
Test name
Test status
Simulation time 189811300 ps
CPU time 112.55 seconds
Started Jan 21 03:45:11 PM PST 24
Finished Jan 21 03:47:04 PM PST 24
Peak memory 258232 kb
Host smart-d1cfa6ef-f3b4-4435-b811-c21d60687c05
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218784059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1218784059
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2110298401
Short name T1029
Test name
Test status
Simulation time 15627900 ps
CPU time 13.59 seconds
Started Jan 21 03:45:14 PM PST 24
Finished Jan 21 03:45:28 PM PST 24
Peak memory 283004 kb
Host smart-c4b8df1e-d5fa-4088-a099-eeee1c4df853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110298401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2110298401
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.545920413
Short name T479
Test name
Test status
Simulation time 43757100 ps
CPU time 130.94 seconds
Started Jan 21 03:45:11 PM PST 24
Finished Jan 21 03:47:23 PM PST 24
Peak memory 258356 kb
Host smart-98dba98d-832b-4674-b473-54dcea4a6962
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545920413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot
p_reset.545920413
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.847349997
Short name T617
Test name
Test status
Simulation time 40561100 ps
CPU time 15.8 seconds
Started Jan 21 03:45:16 PM PST 24
Finished Jan 21 03:45:34 PM PST 24
Peak memory 273488 kb
Host smart-a21adefc-4751-4fbb-b07e-55ed42e8cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847349997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.847349997
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.4004234784
Short name T839
Test name
Test status
Simulation time 13224500 ps
CPU time 15.94 seconds
Started Jan 21 03:45:22 PM PST 24
Finished Jan 21 03:45:40 PM PST 24
Peak memory 273596 kb
Host smart-2c2b86ef-d1dd-42b2-92d0-95a56468e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004234784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.4004234784
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.3310858544
Short name T529
Test name
Test status
Simulation time 24592300 ps
CPU time 15.61 seconds
Started Jan 21 03:45:22 PM PST 24
Finished Jan 21 03:45:39 PM PST 24
Peak memory 273772 kb
Host smart-dd768597-454d-4664-b0db-c8e78fe308aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310858544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3310858544
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3872660036
Short name T672
Test name
Test status
Simulation time 43434600 ps
CPU time 15.74 seconds
Started Jan 21 03:45:21 PM PST 24
Finished Jan 21 03:45:39 PM PST 24
Peak memory 273508 kb
Host smart-f3d8ca2f-78ec-48c1-a1a0-175dffb44321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872660036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3872660036
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.2141269883
Short name T665
Test name
Test status
Simulation time 70261300 ps
CPU time 13.56 seconds
Started Jan 21 03:36:59 PM PST 24
Finished Jan 21 03:37:26 PM PST 24
Peak memory 264180 kb
Host smart-a2dfa803-2bf8-417d-9515-d0f9a00190b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141269883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2
141269883
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.201102182
Short name T443
Test name
Test status
Simulation time 47208000 ps
CPU time 15.59 seconds
Started Jan 21 03:57:09 PM PST 24
Finished Jan 21 03:57:26 PM PST 24
Peak memory 273480 kb
Host smart-3da54537-d186-459a-8f15-0fad9cc41577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201102182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.201102182
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.4086237669
Short name T227
Test name
Test status
Simulation time 15647809400 ps
CPU time 2243.81 seconds
Started Jan 21 03:36:51 PM PST 24
Finished Jan 21 04:14:15 PM PST 24
Peak memory 262564 kb
Host smart-b4acba6f-d09d-4e5b-931c-f4fc62bc407f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086237669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.4086237669
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.1536918449
Short name T823
Test name
Test status
Simulation time 2958021200 ps
CPU time 794.58 seconds
Started Jan 21 03:36:55 PM PST 24
Finished Jan 21 03:50:13 PM PST 24
Peak memory 264300 kb
Host smart-4b5dc0f7-19a2-4e7f-a89c-9f887997efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536918449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1536918449
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.368449065
Short name T49
Test name
Test status
Simulation time 2431776200 ps
CPU time 31.71 seconds
Started Jan 21 03:36:54 PM PST 24
Finished Jan 21 03:37:28 PM PST 24
Peak memory 264276 kb
Host smart-080746e7-8dc4-48b9-995f-df9f5c6d130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368449065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.368449065
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2179956496
Short name T981
Test name
Test status
Simulation time 10028617700 ps
CPU time 112.79 seconds
Started Jan 21 03:37:01 PM PST 24
Finished Jan 21 03:39:05 PM PST 24
Peak memory 276744 kb
Host smart-835d8669-2625-45f8-b07f-8d9df3aa34dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179956496 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2179956496
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3113009706
Short name T820
Test name
Test status
Simulation time 38197300 ps
CPU time 13.3 seconds
Started Jan 21 03:37:04 PM PST 24
Finished Jan 21 03:37:26 PM PST 24
Peak memory 264344 kb
Host smart-8c101439-9946-4805-9d2d-075f995ecc3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113009706 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3113009706
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1934124666
Short name T819
Test name
Test status
Simulation time 7035580700 ps
CPU time 103.11 seconds
Started Jan 21 03:36:40 PM PST 24
Finished Jan 21 03:38:25 PM PST 24
Peak memory 261260 kb
Host smart-b3cfa864-f948-4506-9eab-1c5a16be8388
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934124666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1934124666
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.257964603
Short name T586
Test name
Test status
Simulation time 4535702600 ps
CPU time 164 seconds
Started Jan 21 04:08:06 PM PST 24
Finished Jan 21 04:10:53 PM PST 24
Peak memory 291236 kb
Host smart-fb024a8b-d2f0-4973-b4b6-4a1cacc90ee9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257964603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.257964603
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1199606723
Short name T827
Test name
Test status
Simulation time 32389132300 ps
CPU time 221.84 seconds
Started Jan 21 03:36:51 PM PST 24
Finished Jan 21 03:40:34 PM PST 24
Peak memory 288980 kb
Host smart-1b0301e1-4a7f-458b-bfd4-7f58e488262d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199606723 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1199606723
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.2888734200
Short name T176
Test name
Test status
Simulation time 8028883100 ps
CPU time 100.99 seconds
Started Jan 21 03:36:52 PM PST 24
Finished Jan 21 03:38:34 PM PST 24
Peak memory 264320 kb
Host smart-e593694a-b85d-40ea-93a5-94548a48929c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888734200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.2888734200
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1459656719
Short name T776
Test name
Test status
Simulation time 50772543000 ps
CPU time 362.28 seconds
Started Jan 21 03:48:34 PM PST 24
Finished Jan 21 03:54:38 PM PST 24
Peak memory 264336 kb
Host smart-e2eaa98b-1a08-4b26-afdc-85b6e3ff2e63
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145
9656719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1459656719
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3329215066
Short name T744
Test name
Test status
Simulation time 6754777800 ps
CPU time 81.95 seconds
Started Jan 21 04:30:53 PM PST 24
Finished Jan 21 04:32:16 PM PST 24
Peak memory 258040 kb
Host smart-58fc0432-5c35-41a0-b2f8-3716c87c247d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329215066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3329215066
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3597961078
Short name T1024
Test name
Test status
Simulation time 22092200 ps
CPU time 13.8 seconds
Started Jan 21 03:37:04 PM PST 24
Finished Jan 21 03:37:27 PM PST 24
Peak memory 264312 kb
Host smart-46332fef-d683-4887-b6d2-d95169aab54a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597961078 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3597961078
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2461209864
Short name T106
Test name
Test status
Simulation time 10538030600 ps
CPU time 302.07 seconds
Started Jan 21 04:22:14 PM PST 24
Finished Jan 21 04:27:17 PM PST 24
Peak memory 272852 kb
Host smart-7c1994f7-0f83-454e-bb55-e61b3c4e465e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461209864 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2461209864
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.3181632130
Short name T78
Test name
Test status
Simulation time 41318000 ps
CPU time 131.93 seconds
Started Jan 21 03:36:44 PM PST 24
Finished Jan 21 03:38:57 PM PST 24
Peak memory 258200 kb
Host smart-5caf6a98-f16c-4e55-b266-4ffb6589d964
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181632130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.3181632130
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.568569839
Short name T580
Test name
Test status
Simulation time 6876648800 ps
CPU time 211.79 seconds
Started Jan 21 03:36:46 PM PST 24
Finished Jan 21 03:40:19 PM PST 24
Peak memory 264272 kb
Host smart-a0a34652-89de-4675-b339-60a709009e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568569839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.568569839
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.1938944357
Short name T428
Test name
Test status
Simulation time 77050500 ps
CPU time 13.53 seconds
Started Jan 21 04:01:16 PM PST 24
Finished Jan 21 04:01:31 PM PST 24
Peak memory 264132 kb
Host smart-8b31cf40-ed60-46bd-b0c6-35543583d676
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938944357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.1938944357
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.2936166058
Short name T142
Test name
Test status
Simulation time 81345100 ps
CPU time 273.46 seconds
Started Jan 21 03:36:35 PM PST 24
Finished Jan 21 03:41:13 PM PST 24
Peak memory 280160 kb
Host smart-d4420737-d7c1-4b4b-a47b-f1877f3ad2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936166058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2936166058
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2219802197
Short name T882
Test name
Test status
Simulation time 111598900 ps
CPU time 38.38 seconds
Started Jan 21 03:36:53 PM PST 24
Finished Jan 21 03:37:32 PM PST 24
Peak memory 276020 kb
Host smart-13e79535-5ab2-4fac-adb7-26f47f066f29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219802197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2219802197
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1207996989
Short name T987
Test name
Test status
Simulation time 2371684500 ps
CPU time 108.32 seconds
Started Jan 21 03:36:54 PM PST 24
Finished Jan 21 03:38:44 PM PST 24
Peak memory 280504 kb
Host smart-c39e9167-ea92-4386-8840-7ec53f328023
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207996989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.1207996989
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1605385616
Short name T803
Test name
Test status
Simulation time 3028545600 ps
CPU time 133.73 seconds
Started Jan 21 03:36:48 PM PST 24
Finished Jan 21 03:39:02 PM PST 24
Peak memory 281220 kb
Host smart-433d77e8-9f40-4dd7-a9b1-866f756c292b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1605385616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1605385616
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2125663646
Short name T573
Test name
Test status
Simulation time 2478000900 ps
CPU time 137.41 seconds
Started Jan 21 03:36:54 PM PST 24
Finished Jan 21 03:39:15 PM PST 24
Peak memory 292548 kb
Host smart-97e7889c-593d-4371-b097-e32ecccbdf98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125663646 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2125663646
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.180715216
Short name T664
Test name
Test status
Simulation time 13050448400 ps
CPU time 545.24 seconds
Started Jan 21 05:19:27 PM PST 24
Finished Jan 21 05:28:33 PM PST 24
Peak memory 313508 kb
Host smart-76ba533f-92d0-4b4c-890d-f94349eec939
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180715216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctr
l_rw.180715216
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.1637217393
Short name T197
Test name
Test status
Simulation time 3188302800 ps
CPU time 569.09 seconds
Started Jan 21 03:36:52 PM PST 24
Finished Jan 21 03:46:22 PM PST 24
Peak memory 313580 kb
Host smart-fc9ba01b-434b-404a-bff3-fe9f60823e32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637217393 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.1637217393
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.4119990631
Short name T970
Test name
Test status
Simulation time 28854000 ps
CPU time 34.7 seconds
Started Jan 21 04:50:12 PM PST 24
Finished Jan 21 04:50:49 PM PST 24
Peak memory 273996 kb
Host smart-b054c325-fdb5-44c1-832d-b1b0e25fd9da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119990631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.4119990631
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2064481487
Short name T389
Test name
Test status
Simulation time 59305600 ps
CPU time 28.92 seconds
Started Jan 21 03:51:42 PM PST 24
Finished Jan 21 03:52:11 PM PST 24
Peak memory 272580 kb
Host smart-a21ef7f5-ba7b-4345-89f1-f19c07011d55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064481487 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2064481487
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.350790504
Short name T1049
Test name
Test status
Simulation time 8297325500 ps
CPU time 468.01 seconds
Started Jan 21 03:36:52 PM PST 24
Finished Jan 21 03:44:41 PM PST 24
Peak memory 313496 kb
Host smart-410f7fbd-de7e-4509-a441-5743cc19e271
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350790504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_se
rr.350790504
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3949155037
Short name T755
Test name
Test status
Simulation time 657444800 ps
CPU time 69.5 seconds
Started Jan 21 06:09:38 PM PST 24
Finished Jan 21 06:10:48 PM PST 24
Peak memory 262684 kb
Host smart-4e451e38-f5c0-4684-8127-313b3511873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949155037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3949155037
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.1208906403
Short name T475
Test name
Test status
Simulation time 50873800 ps
CPU time 52.36 seconds
Started Jan 21 03:36:36 PM PST 24
Finished Jan 21 03:37:32 PM PST 24
Peak memory 268900 kb
Host smart-7c0cf74b-d161-49db-9370-78b7dbdd86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208906403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1208906403
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.4199616000
Short name T930
Test name
Test status
Simulation time 7218768400 ps
CPU time 205.38 seconds
Started Jan 21 05:12:10 PM PST 24
Finished Jan 21 05:15:37 PM PST 24
Peak memory 264320 kb
Host smart-b06107c8-fcaa-45f5-a679-16c78681a22d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199616000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.4199616000
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3152814864
Short name T952
Test name
Test status
Simulation time 14188500 ps
CPU time 13.7 seconds
Started Jan 21 03:45:20 PM PST 24
Finished Jan 21 03:45:36 PM PST 24
Peak memory 273488 kb
Host smart-5e30341c-21fd-4d9c-b302-77ab5f6a55b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152814864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3152814864
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3618010125
Short name T778
Test name
Test status
Simulation time 142328000 ps
CPU time 131.79 seconds
Started Jan 21 03:45:25 PM PST 24
Finished Jan 21 03:47:38 PM PST 24
Peak memory 262776 kb
Host smart-91a26521-a36e-46f8-9d2a-bd2ccbcfebf5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618010125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3618010125
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.1135245100
Short name T976
Test name
Test status
Simulation time 44090000 ps
CPU time 13.5 seconds
Started Jan 21 03:45:25 PM PST 24
Finished Jan 21 03:45:40 PM PST 24
Peak memory 273888 kb
Host smart-12ca6d84-bd3b-4c82-9387-b5a3989c42e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135245100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1135245100
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1864280639
Short name T575
Test name
Test status
Simulation time 23473700 ps
CPU time 15.99 seconds
Started Jan 21 03:45:22 PM PST 24
Finished Jan 21 03:45:39 PM PST 24
Peak memory 273424 kb
Host smart-f0b5d7c9-6cd3-44fe-a74e-d6a9a7face2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864280639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1864280639
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.73972642
Short name T640
Test name
Test status
Simulation time 35061400 ps
CPU time 16.26 seconds
Started Jan 21 03:45:40 PM PST 24
Finished Jan 21 03:45:59 PM PST 24
Peak memory 273424 kb
Host smart-74afccca-7cb5-42f3-8909-ae885d1a03a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73972642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.73972642
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.3147746000
Short name T751
Test name
Test status
Simulation time 43592900 ps
CPU time 15.63 seconds
Started Jan 21 03:45:36 PM PST 24
Finished Jan 21 03:45:53 PM PST 24
Peak memory 273772 kb
Host smart-419e6794-d305-4733-9016-26a6a56150dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147746000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3147746000
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3182000923
Short name T690
Test name
Test status
Simulation time 111441300 ps
CPU time 110.22 seconds
Started Jan 21 03:45:31 PM PST 24
Finished Jan 21 03:47:23 PM PST 24
Peak memory 258164 kb
Host smart-d3edd9cd-6e1f-4a6b-a99b-00869ebe2e41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182000923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3182000923
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.407522186
Short name T587
Test name
Test status
Simulation time 30614200 ps
CPU time 13.86 seconds
Started Jan 21 03:45:41 PM PST 24
Finished Jan 21 03:45:57 PM PST 24
Peak memory 273536 kb
Host smart-302a2963-5df8-4e70-8369-d0934d7fefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407522186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.407522186
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.764920066
Short name T1
Test name
Test status
Simulation time 40492900 ps
CPU time 133.79 seconds
Started Jan 21 03:45:39 PM PST 24
Finished Jan 21 03:47:56 PM PST 24
Peak memory 258076 kb
Host smart-8d63d383-ce13-433c-9f1f-d03f52e06a85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764920066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.764920066
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3262555486
Short name T793
Test name
Test status
Simulation time 16533000 ps
CPU time 13.29 seconds
Started Jan 21 03:45:36 PM PST 24
Finished Jan 21 03:45:50 PM PST 24
Peak memory 274220 kb
Host smart-eeee09ad-6d4b-49bc-bd3a-60f4e5f79e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262555486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3262555486
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2976851222
Short name T961
Test name
Test status
Simulation time 13844700 ps
CPU time 15.9 seconds
Started Jan 21 03:45:39 PM PST 24
Finished Jan 21 03:45:58 PM PST 24
Peak memory 273736 kb
Host smart-474ba1ec-d040-427b-87e2-b7ad0b3353f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976851222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2976851222
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1306547514
Short name T121
Test name
Test status
Simulation time 39251200 ps
CPU time 131.95 seconds
Started Jan 21 03:45:31 PM PST 24
Finished Jan 21 03:47:45 PM PST 24
Peak memory 262560 kb
Host smart-1e34e98b-dd48-4138-abc3-5fc8bbec902c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306547514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1306547514
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.1668089544
Short name T511
Test name
Test status
Simulation time 35944000 ps
CPU time 15.66 seconds
Started Jan 21 03:45:37 PM PST 24
Finished Jan 21 03:45:55 PM PST 24
Peak memory 273552 kb
Host smart-a2ed3e4f-36bc-4d72-bd17-2fab9b74bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668089544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1668089544
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.4240916782
Short name T105
Test name
Test status
Simulation time 179562200 ps
CPU time 13.4 seconds
Started Jan 21 03:45:34 PM PST 24
Finished Jan 21 03:45:49 PM PST 24
Peak memory 273636 kb
Host smart-5d0ef4d1-98b5-4f56-82bd-f3bcd7c46232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240916782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.4240916782
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.538527912
Short name T192
Test name
Test status
Simulation time 37480000 ps
CPU time 131.86 seconds
Started Jan 21 03:45:37 PM PST 24
Finished Jan 21 03:47:50 PM PST 24
Peak memory 258376 kb
Host smart-de1c4642-5025-4749-802d-d115376f7e5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538527912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.538527912
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3862506320
Short name T919
Test name
Test status
Simulation time 76866000 ps
CPU time 13.76 seconds
Started Jan 21 03:37:30 PM PST 24
Finished Jan 21 03:37:46 PM PST 24
Peak memory 264308 kb
Host smart-6acacd4b-7f53-4b3a-94ac-eac30e181e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862506320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
862506320
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2470974373
Short name T942
Test name
Test status
Simulation time 16207000 ps
CPU time 15.93 seconds
Started Jan 21 03:37:25 PM PST 24
Finished Jan 21 03:37:41 PM PST 24
Peak memory 273804 kb
Host smart-65d7a2e5-4bde-456e-ae7e-0f9ebe292e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470974373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2470974373
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.890240733
Short name T643
Test name
Test status
Simulation time 26638095500 ps
CPU time 2302.73 seconds
Started Jan 21 03:37:17 PM PST 24
Finished Jan 21 04:15:45 PM PST 24
Peak memory 262540 kb
Host smart-f8bfdc7c-9782-4c9b-9ae6-18cf630be4e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890240733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_erro
r_mp.890240733
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.949502703
Short name T584
Test name
Test status
Simulation time 1672683200 ps
CPU time 967.63 seconds
Started Jan 21 04:51:55 PM PST 24
Finished Jan 21 05:08:04 PM PST 24
Peak memory 264308 kb
Host smart-89cae6bd-3197-4c9f-be56-fb0b4cf4d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949502703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.949502703
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3031237186
Short name T843
Test name
Test status
Simulation time 295920100 ps
CPU time 26.07 seconds
Started Jan 21 03:37:17 PM PST 24
Finished Jan 21 03:37:48 PM PST 24
Peak memory 264172 kb
Host smart-cb559732-fcb2-4947-a58a-ee29da09e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031237186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3031237186
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2563456092
Short name T550
Test name
Test status
Simulation time 10012718600 ps
CPU time 105.34 seconds
Started Jan 21 03:37:30 PM PST 24
Finished Jan 21 03:39:18 PM PST 24
Peak memory 306816 kb
Host smart-b5430b93-d262-4f62-9eae-b19076cedd0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563456092 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2563456092
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3666338134
Short name T294
Test name
Test status
Simulation time 15824300 ps
CPU time 13.51 seconds
Started Jan 21 04:04:34 PM PST 24
Finished Jan 21 04:04:49 PM PST 24
Peak memory 263064 kb
Host smart-a7da29cb-e0e1-4144-a4b5-dbadc94059c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666338134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3666338134
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.3370100481
Short name T102
Test name
Test status
Simulation time 40122495600 ps
CPU time 736.55 seconds
Started Jan 21 03:37:04 PM PST 24
Finished Jan 21 03:49:29 PM PST 24
Peak memory 262372 kb
Host smart-d4c966a7-6dc7-4196-8625-9bab6d29ee1c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370100481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.3370100481
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.807217800
Short name T636
Test name
Test status
Simulation time 1864086400 ps
CPU time 50.48 seconds
Started Jan 21 03:36:59 PM PST 24
Finished Jan 21 03:38:02 PM PST 24
Peak memory 261360 kb
Host smart-555f63eb-0cf6-416e-bc2a-c240568a99ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807217800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw
_sec_otp.807217800
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2840688068
Short name T671
Test name
Test status
Simulation time 6888513400 ps
CPU time 167.59 seconds
Started Jan 21 03:37:15 PM PST 24
Finished Jan 21 03:40:09 PM PST 24
Peak memory 292128 kb
Host smart-006b6c58-70d6-4626-b4fe-63e3bf2d4701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840688068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2840688068
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3027981287
Short name T740
Test name
Test status
Simulation time 8552452100 ps
CPU time 225.66 seconds
Started Jan 21 03:37:25 PM PST 24
Finished Jan 21 03:41:11 PM PST 24
Peak memory 283204 kb
Host smart-dadd6099-791c-4e41-aa00-5d008284186e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027981287 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3027981287
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.674720624
Short name T406
Test name
Test status
Simulation time 4704734600 ps
CPU time 113.92 seconds
Started Jan 21 03:37:19 PM PST 24
Finished Jan 21 03:39:17 PM PST 24
Peak memory 264280 kb
Host smart-51dee95e-608d-4d50-a3aa-2542d3ae3df3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674720624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.674720624
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.4252091217
Short name T405
Test name
Test status
Simulation time 192136806900 ps
CPU time 541.64 seconds
Started Jan 21 03:37:22 PM PST 24
Finished Jan 21 03:46:25 PM PST 24
Peak memory 264120 kb
Host smart-ea07bc97-3e1f-454c-8e50-961531c13770
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425
2091217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.4252091217
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3867097107
Short name T809
Test name
Test status
Simulation time 1671719400 ps
CPU time 64.32 seconds
Started Jan 21 03:37:12 PM PST 24
Finished Jan 21 03:38:24 PM PST 24
Peak memory 258072 kb
Host smart-bee71be5-9a8f-4a93-8f98-2eeb2f2cf426
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867097107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3867097107
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1462669895
Short name T572
Test name
Test status
Simulation time 47539100 ps
CPU time 13.76 seconds
Started Jan 21 03:37:24 PM PST 24
Finished Jan 21 03:37:39 PM PST 24
Peak memory 264356 kb
Host smart-91bf830a-298a-43a1-a840-7bf239618975
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462669895 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.1462669895
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2671931150
Short name T112
Test name
Test status
Simulation time 18694146300 ps
CPU time 421.68 seconds
Started Jan 21 03:37:02 PM PST 24
Finished Jan 21 03:44:14 PM PST 24
Peak memory 272764 kb
Host smart-31deb3f5-dc0b-417a-b45c-9837980eaae4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671931150 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2671931150
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3077758143
Short name T203
Test name
Test status
Simulation time 722890800 ps
CPU time 297.07 seconds
Started Jan 21 03:37:02 PM PST 24
Finished Jan 21 03:42:10 PM PST 24
Peak memory 260660 kb
Host smart-e264fb58-5444-4799-88cc-cf71855bdab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077758143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3077758143
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.1026016405
Short name T425
Test name
Test status
Simulation time 51943800 ps
CPU time 14.43 seconds
Started Jan 21 03:37:24 PM PST 24
Finished Jan 21 03:37:39 PM PST 24
Peak memory 264324 kb
Host smart-67a726ac-8ceb-42c0-b763-28b022edbf3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026016405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.1026016405
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3356981599
Short name T131
Test name
Test status
Simulation time 1177481600 ps
CPU time 1154.25 seconds
Started Jan 21 03:37:03 PM PST 24
Finished Jan 21 03:56:27 PM PST 24
Peak memory 285412 kb
Host smart-3376346b-aa73-4664-ab4f-dd5d506cf4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356981599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3356981599
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.4144665141
Short name T607
Test name
Test status
Simulation time 131620800 ps
CPU time 38.14 seconds
Started Jan 21 03:37:22 PM PST 24
Finished Jan 21 03:38:02 PM PST 24
Peak memory 265456 kb
Host smart-4f1cb7d3-0323-4786-8ad7-384de2eb3540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144665141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.4144665141
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.2417185823
Short name T476
Test name
Test status
Simulation time 950664600 ps
CPU time 94.63 seconds
Started Jan 21 03:37:09 PM PST 24
Finished Jan 21 03:38:50 PM PST 24
Peak memory 280492 kb
Host smart-e5d1ee60-be7b-4340-a5d1-38e673963940
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417185823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.2417185823
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.1856880076
Short name T194
Test name
Test status
Simulation time 1316892500 ps
CPU time 132.48 seconds
Started Jan 21 03:37:18 PM PST 24
Finished Jan 21 03:39:35 PM PST 24
Peak memory 280756 kb
Host smart-c5198922-4418-4924-8afd-a5784f202822
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1856880076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1856880076
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2313765688
Short name T328
Test name
Test status
Simulation time 2332694400 ps
CPU time 104.59 seconds
Started Jan 21 03:37:10 PM PST 24
Finished Jan 21 03:39:02 PM PST 24
Peak memory 292440 kb
Host smart-1aa7d498-119d-4efe-a721-3353d298971d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313765688 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2313765688
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1853107822
Short name T464
Test name
Test status
Simulation time 6947524600 ps
CPU time 497.87 seconds
Started Jan 21 03:37:12 PM PST 24
Finished Jan 21 03:45:37 PM PST 24
Peak memory 312284 kb
Host smart-5af66b9a-3a17-4884-a9f9-83f535f9c098
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853107822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.1853107822
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.1877663622
Short name T734
Test name
Test status
Simulation time 34236795800 ps
CPU time 609.3 seconds
Started Jan 21 03:37:18 PM PST 24
Finished Jan 21 03:47:32 PM PST 24
Peak memory 330164 kb
Host smart-bc3392ba-576c-44b2-8aa8-0e18a1491807
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877663622 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.1877663622
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.955126105
Short name T493
Test name
Test status
Simulation time 36129300 ps
CPU time 31.92 seconds
Started Jan 21 03:37:23 PM PST 24
Finished Jan 21 03:37:56 PM PST 24
Peak memory 272676 kb
Host smart-0ee5d16a-91e4-430e-825b-26234496a7c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955126105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.955126105
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.1773846404
Short name T388
Test name
Test status
Simulation time 66802200 ps
CPU time 28.3 seconds
Started Jan 21 03:37:27 PM PST 24
Finished Jan 21 03:37:56 PM PST 24
Peak memory 273812 kb
Host smart-8d9d9026-c1c9-4c9f-8dc5-e1fa767dd067
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773846404 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.1773846404
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.828233013
Short name T486
Test name
Test status
Simulation time 7252039300 ps
CPU time 569.91 seconds
Started Jan 21 03:37:07 PM PST 24
Finished Jan 21 03:46:45 PM PST 24
Peak memory 311732 kb
Host smart-2c3e9e22-0f2f-4113-92f0-e80033ab85a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828233013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_se
rr.828233013
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3135893631
Short name T62
Test name
Test status
Simulation time 7690728700 ps
CPU time 66.71 seconds
Started Jan 21 04:00:24 PM PST 24
Finished Jan 21 04:01:32 PM PST 24
Peak memory 258092 kb
Host smart-442bbe75-6650-430f-a7a0-21b9ed5650af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135893631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3135893631
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2438583166
Short name T371
Test name
Test status
Simulation time 147548800 ps
CPU time 99.22 seconds
Started Jan 21 03:37:03 PM PST 24
Finished Jan 21 03:38:52 PM PST 24
Peak memory 273544 kb
Host smart-adfe64e8-7fbe-4f7e-9978-f51d905c9c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438583166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2438583166
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3483760348
Short name T841
Test name
Test status
Simulation time 1693036400 ps
CPU time 144.23 seconds
Started Jan 21 03:37:11 PM PST 24
Finished Jan 21 03:39:43 PM PST 24
Peak memory 264268 kb
Host smart-6978d314-2d38-4652-bb96-3535c05847b4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483760348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.3483760348
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.1727973009
Short name T711
Test name
Test status
Simulation time 154277300 ps
CPU time 13.79 seconds
Started Jan 21 03:57:48 PM PST 24
Finished Jan 21 03:58:03 PM PST 24
Peak memory 263824 kb
Host smart-d38594c8-2468-443e-8066-483c73dff91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727973009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1
727973009
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.2999239737
Short name T654
Test name
Test status
Simulation time 19614500 ps
CPU time 15.59 seconds
Started Jan 21 03:37:56 PM PST 24
Finished Jan 21 03:38:13 PM PST 24
Peak memory 273536 kb
Host smart-b5125e61-2cbd-45dd-b908-123fc3a527d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999239737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2999239737
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.781729087
Short name T1005
Test name
Test status
Simulation time 36867700 ps
CPU time 22.31 seconds
Started Jan 21 03:37:42 PM PST 24
Finished Jan 21 03:38:05 PM PST 24
Peak memory 272608 kb
Host smart-6123aef0-4bd5-4ea5-9ee9-33a0beac4790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781729087 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.781729087
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1559107977
Short name T962
Test name
Test status
Simulation time 6729261900 ps
CPU time 2169.64 seconds
Started Jan 21 03:37:38 PM PST 24
Finished Jan 21 04:13:49 PM PST 24
Peak memory 262796 kb
Host smart-8d36d350-2f40-44b0-9821-bd098818b203
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559107977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.1559107977
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3926603624
Short name T167
Test name
Test status
Simulation time 5771501100 ps
CPU time 802.63 seconds
Started Jan 21 03:37:31 PM PST 24
Finished Jan 21 03:50:55 PM PST 24
Peak memory 264276 kb
Host smart-904aaaa5-1a83-4b2f-b4a9-3fffd72fc869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926603624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3926603624
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.2835981281
Short name T605
Test name
Test status
Simulation time 263110400 ps
CPU time 27.37 seconds
Started Jan 21 04:39:27 PM PST 24
Finished Jan 21 04:39:55 PM PST 24
Peak memory 264492 kb
Host smart-663d2528-7952-47a9-9fbb-bed9a6b16c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835981281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.2835981281
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2900976416
Short name T719
Test name
Test status
Simulation time 10034321000 ps
CPU time 57.98 seconds
Started Jan 21 03:37:50 PM PST 24
Finished Jan 21 03:38:49 PM PST 24
Peak memory 291516 kb
Host smart-c37e9222-c3ce-430a-96f3-eab0fcfaab5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900976416 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2900976416
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1042901922
Short name T835
Test name
Test status
Simulation time 46448900 ps
CPU time 13.54 seconds
Started Jan 21 03:37:56 PM PST 24
Finished Jan 21 03:38:10 PM PST 24
Peak memory 264320 kb
Host smart-3011eca7-50f4-4a0a-95f1-e929b386a5bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042901922 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1042901922
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.3439959357
Short name T685
Test name
Test status
Simulation time 16875272000 ps
CPU time 152.25 seconds
Started Jan 21 03:37:34 PM PST 24
Finished Jan 21 03:40:08 PM PST 24
Peak memory 261148 kb
Host smart-37420d84-47f2-40a9-b89c-fc537df1eabe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439959357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.3439959357
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3933578632
Short name T895
Test name
Test status
Simulation time 2509576600 ps
CPU time 182.3 seconds
Started Jan 21 03:37:41 PM PST 24
Finished Jan 21 03:40:45 PM PST 24
Peak memory 292180 kb
Host smart-3a25f52f-239a-40c7-a118-3df4d5a26175
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933578632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3933578632
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2826465110
Short name T986
Test name
Test status
Simulation time 28310743200 ps
CPU time 213.02 seconds
Started Jan 21 03:37:40 PM PST 24
Finished Jan 21 03:41:14 PM PST 24
Peak memory 290992 kb
Host smart-21c8a1d1-12bf-4375-a9fa-00ec36cbff8a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826465110 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2826465110
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2440024559
Short name T177
Test name
Test status
Simulation time 12934395900 ps
CPU time 110.38 seconds
Started Jan 21 03:37:39 PM PST 24
Finished Jan 21 03:39:30 PM PST 24
Peak memory 264136 kb
Host smart-99429085-42b0-4176-b4af-20bf921373be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440024559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2440024559
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.157095394
Short name T749
Test name
Test status
Simulation time 90806550900 ps
CPU time 530.71 seconds
Started Jan 21 04:02:31 PM PST 24
Finished Jan 21 04:11:29 PM PST 24
Peak memory 264296 kb
Host smart-a14c2fe2-bf50-4b65-a25e-ef16230d6e53
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157
095394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.157095394
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.220730242
Short name T387
Test name
Test status
Simulation time 3773599600 ps
CPU time 95.87 seconds
Started Jan 21 03:37:35 PM PST 24
Finished Jan 21 03:39:12 PM PST 24
Peak memory 258856 kb
Host smart-b5232689-99bd-4e51-ae9b-d1b90da33fa0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220730242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.220730242
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.3796275236
Short name T943
Test name
Test status
Simulation time 15736100 ps
CPU time 13.53 seconds
Started Jan 21 03:37:56 PM PST 24
Finished Jan 21 03:38:10 PM PST 24
Peak memory 264348 kb
Host smart-482451c6-c937-4333-92df-049ea445f433
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796275236 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.3796275236
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.2128184319
Short name T107
Test name
Test status
Simulation time 32716515800 ps
CPU time 346.4 seconds
Started Jan 21 03:37:36 PM PST 24
Finished Jan 21 03:43:23 PM PST 24
Peak memory 272436 kb
Host smart-dd06ad0b-9ce5-4b29-9fb6-88d101287ff3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128184319 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.2128184319
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.2089292572
Short name T973
Test name
Test status
Simulation time 146881500 ps
CPU time 128.6 seconds
Started Jan 21 03:37:31 PM PST 24
Finished Jan 21 03:39:41 PM PST 24
Peak memory 258048 kb
Host smart-186f888f-7d3a-48d3-9462-e8ab1d5c27f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089292572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.2089292572
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1038819051
Short name T480
Test name
Test status
Simulation time 348266700 ps
CPU time 449.2 seconds
Started Jan 21 03:37:30 PM PST 24
Finished Jan 21 03:45:01 PM PST 24
Peak memory 260672 kb
Host smart-507202de-369a-4959-8936-39efed2e47fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038819051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1038819051
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.2186577217
Short name T592
Test name
Test status
Simulation time 18802800 ps
CPU time 13.59 seconds
Started Jan 21 03:37:42 PM PST 24
Finished Jan 21 03:37:56 PM PST 24
Peak memory 264348 kb
Host smart-9f4fcf29-80cc-4d2c-a4c6-6856f1db70a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186577217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.2186577217
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3099821563
Short name T113
Test name
Test status
Simulation time 1613453200 ps
CPU time 1423.55 seconds
Started Jan 21 03:37:30 PM PST 24
Finished Jan 21 04:01:16 PM PST 24
Peak memory 286900 kb
Host smart-d6aef746-1b7f-4afb-b479-7fff3412d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099821563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3099821563
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.79837816
Short name T595
Test name
Test status
Simulation time 1004337100 ps
CPU time 99.36 seconds
Started Jan 21 03:37:42 PM PST 24
Finished Jan 21 03:39:23 PM PST 24
Peak memory 280516 kb
Host smart-48efc7f0-2f44-446e-b6cb-546cecc25007
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79837816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.flash_ctrl_ro.79837816
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2501263875
Short name T646
Test name
Test status
Simulation time 800112300 ps
CPU time 149.07 seconds
Started Jan 21 03:37:44 PM PST 24
Finished Jan 21 03:40:14 PM PST 24
Peak memory 280680 kb
Host smart-ed3ebebc-eb2e-432c-a795-b6cb02ea31d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2501263875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2501263875
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1310388873
Short name T288
Test name
Test status
Simulation time 6011643600 ps
CPU time 148.08 seconds
Started Jan 21 03:37:41 PM PST 24
Finished Jan 21 03:40:10 PM PST 24
Peak memory 289020 kb
Host smart-46d86457-100f-4ae2-8fc0-e62ef15f8eaf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310388873 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1310388873
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.586401240
Short name T988
Test name
Test status
Simulation time 12565494800 ps
CPU time 471.15 seconds
Started Jan 21 03:37:44 PM PST 24
Finished Jan 21 03:45:36 PM PST 24
Peak memory 312496 kb
Host smart-036e6be9-fa27-44f6-950d-b589a51199f2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586401240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctr
l_rw.586401240
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.651477952
Short name T209
Test name
Test status
Simulation time 4932089900 ps
CPU time 766.21 seconds
Started Jan 21 03:37:44 PM PST 24
Finished Jan 21 03:50:31 PM PST 24
Peak memory 339456 kb
Host smart-87d47e6f-c86a-4cad-a454-5e3810e27b9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651477952 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_rw_derr.651477952
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.3155436358
Short name T588
Test name
Test status
Simulation time 67394600 ps
CPU time 29.25 seconds
Started Jan 21 03:37:41 PM PST 24
Finished Jan 21 03:38:11 PM PST 24
Peak memory 264440 kb
Host smart-d5b26f50-3744-40f8-90a7-f51513c48c99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155436358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.3155436358
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1482220004
Short name T621
Test name
Test status
Simulation time 29595300 ps
CPU time 31.74 seconds
Started Jan 21 03:37:40 PM PST 24
Finished Jan 21 03:38:13 PM PST 24
Peak memory 274104 kb
Host smart-a1755d6f-b34d-4a02-a18c-837650fdb68d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482220004 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1482220004
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.2666005373
Short name T869
Test name
Test status
Simulation time 5244119300 ps
CPU time 500.56 seconds
Started Jan 21 03:37:42 PM PST 24
Finished Jan 21 03:46:03 PM PST 24
Peak memory 311408 kb
Host smart-fb32ca98-e9c6-4f2b-a6df-bc6cb54540bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666005373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.2666005373
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.920619203
Short name T364
Test name
Test status
Simulation time 3441630300 ps
CPU time 66.16 seconds
Started Jan 21 03:37:46 PM PST 24
Finished Jan 21 03:38:53 PM PST 24
Peak memory 258108 kb
Host smart-0c4a70f5-00d4-43a9-821e-4d607e2ce93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920619203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.920619203
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2495979695
Short name T901
Test name
Test status
Simulation time 28354300 ps
CPU time 120.43 seconds
Started Jan 21 03:37:31 PM PST 24
Finished Jan 21 03:39:33 PM PST 24
Peak memory 274248 kb
Host smart-07441ecf-6f05-49c9-86bd-df2730fea97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495979695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2495979695
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.16468002
Short name T941
Test name
Test status
Simulation time 2180392100 ps
CPU time 152.37 seconds
Started Jan 21 03:37:44 PM PST 24
Finished Jan 21 03:40:17 PM PST 24
Peak memory 264368 kb
Host smart-229ff5a3-9474-4f75-8634-ab256b8d23c5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_wo.16468002
Directory /workspace/9.flash_ctrl_wo/latest
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