Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	337275	1		T1	2		T2	2		T3	1
all_values[1]	337275	1		T1	2		T2	2		T3	1
all_values[2]	337275	1		T1	2		T2	2		T3	1
all_values[3]	337275	1		T1	2		T2	2		T3	1
all_values[4]	337275	1		T1	2		T2	2		T3	1
all_values[5]	337275	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9504	1		T1	12		T2	12		T3	6
auto[1]	2014146	1		T42	14214		T43	15156		T33	9318

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1645600	1		T1	10		T2	11		T3	6
auto[1]	378050	1		T1	2		T2	1		T6	1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1167	1		T1	1		T2	2		T3	1
all_values[0]	auto[0]	auto[1]	419	1		T1	1		T23	1		T4	1
all_values[0]	auto[1]	auto[0]	274750	1		T42	2369		T43	2526		T33	1553
all_values[0]	auto[1]	auto[1]	60939	1		T162	4320		T46	2430		T163	4440
all_values[1]	auto[0]	auto[0]	1538	1		T1	2		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	60	1		T246	1		T322	2		T323	3
all_values[1]	auto[1]	auto[0]	270513	1		T42	2369		T43	2526		T33	1553
all_values[1]	auto[1]	auto[1]	65164	1		T46	6239		T47	3332		T48	3612
all_values[2]	auto[0]	auto[0]	1453	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	121	1		T50	1		T51	1		T52	1
all_values[2]	auto[1]	auto[0]	328673	1		T42	2325		T43	2526		T33	1217
all_values[2]	auto[1]	auto[1]	7028	1		T42	44		T33	336		T53	1051
all_values[3]	auto[0]	auto[0]	1442	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	139	1		T50	1		T51	1		T52	1
all_values[3]	auto[1]	auto[0]	188355	1		T42	758		T43	842		T33	776
all_values[3]	auto[1]	auto[1]	147339	1		T42	1611		T43	1684		T33	777
all_values[4]	auto[0]	auto[0]	1097	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	490	1		T1	1		T2	1		T6	1
all_values[4]	auto[1]	auto[0]	239543	1		T42	1214		T43	1684		T33	776
all_values[4]	auto[1]	auto[1]	96145	1		T42	1155		T43	842		T33	777
all_values[5]	auto[0]	auto[0]	1433	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	145	1		T4	1		T45	5		T34	1
all_values[5]	auto[1]	auto[0]	335636	1		T42	2369		T43	2526		T33	1553
all_values[5]	auto[1]	auto[1]	61	1		T244	1		T246	5		T322	1