Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T6 |
10 |
|
T18 |
1 |
|
T20 |
1 |
| others[1] |
1081 |
1 |
|
T6 |
11 |
|
T24 |
1 |
|
T43 |
1 |
| others[2] |
1091 |
1 |
|
T1 |
1 |
|
T6 |
8 |
|
T23 |
1 |
| others[3] |
1741 |
1 |
|
T2 |
1 |
|
T6 |
25 |
|
T19 |
1 |
| false |
552 |
1 |
|
T6 |
8 |
|
T21 |
1 |
|
T29 |
1 |
| true |
1381 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T38 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T52 |
9 |
| others[1] |
227 |
1 |
|
T20 |
1 |
|
T21 |
2 |
|
T24 |
1 |
| others[2] |
235 |
1 |
|
T34 |
1 |
|
T52 |
8 |
|
T109 |
9 |
| others[3] |
362 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T45 |
1 |
| false |
120 |
1 |
|
T45 |
2 |
|
T52 |
8 |
|
T109 |
7 |
| true |
5732 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T25 |
1 |
|
T52 |
12 |
|
T109 |
7 |
| others[1] |
196 |
1 |
|
T29 |
1 |
|
T25 |
2 |
|
T45 |
1 |
| others[2] |
221 |
1 |
|
T4 |
1 |
|
T25 |
1 |
|
T52 |
12 |
| others[3] |
343 |
1 |
|
T24 |
2 |
|
T25 |
1 |
|
T45 |
1 |
| false |
118 |
1 |
|
T21 |
1 |
|
T52 |
7 |
|
T109 |
6 |
| true |
5812 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T6 |
16 |
|
T21 |
1 |
|
T29 |
1 |
| others[1] |
1289 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
11 |
| others[2] |
1242 |
1 |
|
T6 |
11 |
|
T23 |
1 |
|
T144 |
1 |
| others[3] |
2149 |
1 |
|
T6 |
19 |
|
T4 |
1 |
|
T24 |
2 |
| false |
602 |
1 |
|
T6 |
5 |
|
T18 |
1 |
|
T23 |
1 |
| true |
414 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1330 |
1 |
|
T6 |
12 |
|
T29 |
1 |
|
T25 |
1 |
| others[1] |
1254 |
1 |
|
T6 |
10 |
|
T21 |
1 |
|
T24 |
1 |
| others[2] |
1241 |
1 |
|
T1 |
1 |
|
T6 |
17 |
|
T23 |
1 |
| others[3] |
2100 |
1 |
|
T2 |
1 |
|
T6 |
19 |
|
T19 |
1 |
| false |
592 |
1 |
|
T6 |
4 |
|
T18 |
1 |
|
T76 |
9 |
| true |
409 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T23 |
2 |
|
T25 |
3 |
|
T74 |
1 |
| others[1] |
100 |
1 |
|
T24 |
1 |
|
T25 |
3 |
|
T52 |
5 |
| others[2] |
98 |
1 |
|
T21 |
1 |
|
T24 |
1 |
|
T25 |
1 |
| others[3] |
181 |
1 |
|
T29 |
1 |
|
T45 |
1 |
|
T52 |
5 |
| false |
42 |
1 |
|
T21 |
1 |
|
T25 |
1 |
|
T52 |
1 |
| true |
6396 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| others[1] |
236 |
1 |
|
T1 |
1 |
|
T45 |
1 |
|
T52 |
12 |
| others[2] |
219 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T52 |
8 |
| others[3] |
368 |
1 |
|
T24 |
1 |
|
T44 |
1 |
|
T45 |
1 |
| false |
138 |
1 |
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
1 |
| true |
5722 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T1 |
1 |
|
T6 |
8 |
|
T19 |
1 |
| others[1] |
1084 |
1 |
|
T2 |
1 |
|
T6 |
13 |
|
T21 |
1 |
| others[2] |
1064 |
1 |
|
T6 |
14 |
|
T39 |
1 |
|
T25 |
2 |
| others[3] |
1840 |
1 |
|
T6 |
22 |
|
T18 |
1 |
|
T10 |
1 |
| false |
526 |
1 |
|
T6 |
5 |
|
T38 |
2 |
|
T45 |
2 |
| true |
1371 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T21 |
1 |
|
T74 |
1 |
|
T52 |
12 |
| others[1] |
206 |
1 |
|
T23 |
1 |
|
T44 |
1 |
|
T52 |
10 |
| others[2] |
249 |
1 |
|
T52 |
11 |
|
T109 |
9 |
|
T49 |
1 |
| others[3] |
386 |
1 |
|
T41 |
1 |
|
T25 |
2 |
|
T45 |
2 |
| false |
124 |
1 |
|
T20 |
1 |
|
T53 |
1 |
|
T52 |
6 |
| true |
5735 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T41 |
1 |
|
T25 |
1 |
|
T52 |
9 |
| others[1] |
209 |
1 |
|
T25 |
1 |
|
T45 |
1 |
|
T52 |
12 |
| others[2] |
219 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T39 |
1 |
| others[3] |
357 |
1 |
|
T24 |
1 |
|
T25 |
2 |
|
T52 |
19 |
| false |
121 |
1 |
|
T25 |
1 |
|
T52 |
2 |
|
T109 |
4 |
| true |
5797 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T1 |
1 |
|
T6 |
15 |
|
T18 |
1 |
| others[1] |
1209 |
1 |
|
T6 |
7 |
|
T23 |
2 |
|
T25 |
2 |
| others[2] |
1250 |
1 |
|
T6 |
16 |
|
T21 |
1 |
|
T25 |
1 |
| others[3] |
2162 |
1 |
|
T2 |
1 |
|
T6 |
19 |
|
T25 |
4 |
| false |
624 |
1 |
|
T6 |
5 |
|
T21 |
1 |
|
T29 |
1 |
| true |
423 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T6 |
12 |
|
T21 |
1 |
|
T29 |
1 |
| others[1] |
1226 |
1 |
|
T6 |
11 |
|
T19 |
1 |
|
T23 |
1 |
| others[2] |
1297 |
1 |
|
T1 |
1 |
|
T6 |
13 |
|
T18 |
1 |
| others[3] |
2088 |
1 |
|
T6 |
17 |
|
T23 |
1 |
|
T24 |
1 |
| false |
638 |
1 |
|
T2 |
1 |
|
T6 |
9 |
|
T25 |
1 |
| true |
402 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
81 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T45 |
1 |
| others[1] |
106 |
1 |
|
T1 |
1 |
|
T25 |
2 |
|
T52 |
4 |
| others[2] |
91 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[3] |
160 |
1 |
|
T21 |
1 |
|
T24 |
2 |
|
T25 |
3 |
| false |
55 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T52 |
3 |
| true |
6433 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T38 |
1 |
|
T25 |
2 |
|
T45 |
1 |
| others[1] |
213 |
1 |
|
T3 |
1 |
|
T21 |
1 |
|
T38 |
1 |
| others[2] |
260 |
1 |
|
T23 |
2 |
|
T38 |
1 |
|
T24 |
1 |
| others[3] |
410 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T38 |
3 |
| false |
93 |
1 |
|
T52 |
4 |
|
T109 |
4 |
|
T114 |
3 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T3 |
1 |
|
T6 |
10 |
|
T29 |
1 |
| others[1] |
1103 |
1 |
|
T6 |
13 |
|
T23 |
1 |
|
T24 |
1 |
| others[2] |
1126 |
1 |
|
T1 |
1 |
|
T6 |
9 |
|
T18 |
1 |
| others[3] |
1708 |
1 |
|
T2 |
1 |
|
T6 |
22 |
|
T21 |
2 |
| false |
547 |
1 |
|
T6 |
8 |
|
T42 |
1 |
|
T76 |
6 |
| true |
1382 |
1 |
|
T20 |
1 |
|
T10 |
1 |
|
T38 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T38 |
1 |
|
T45 |
1 |
|
T34 |
1 |
| others[1] |
222 |
1 |
|
T24 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| others[2] |
263 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| others[3] |
407 |
1 |
|
T23 |
1 |
|
T38 |
4 |
|
T41 |
1 |
| false |
107 |
1 |
|
T25 |
3 |
|
T52 |
2 |
|
T109 |
4 |
| true |
5694 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T23 |
1 |
|
T52 |
10 |
|
T109 |
6 |
| others[1] |
217 |
1 |
|
T41 |
1 |
|
T25 |
1 |
|
T52 |
10 |
| others[2] |
197 |
1 |
|
T21 |
1 |
|
T45 |
2 |
|
T52 |
12 |
| others[3] |
385 |
1 |
|
T1 |
1 |
|
T25 |
1 |
|
T52 |
17 |
| false |
97 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T52 |
7 |
| true |
5822 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T6 |
13 |
|
T18 |
1 |
|
T21 |
2 |
| others[1] |
1266 |
1 |
|
T6 |
15 |
|
T43 |
1 |
|
T25 |
1 |
| others[2] |
1177 |
1 |
|
T6 |
9 |
|
T23 |
1 |
|
T24 |
2 |
| others[3] |
2162 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
23 |
| false |
628 |
1 |
|
T6 |
2 |
|
T74 |
1 |
|
T191 |
1 |
| true |
412 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T6 |
7 |
|
T21 |
1 |
|
T23 |
1 |
| others[1] |
1281 |
1 |
|
T6 |
13 |
|
T19 |
1 |
|
T21 |
1 |
| others[2] |
1290 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
16 |
| others[3] |
2068 |
1 |
|
T6 |
17 |
|
T24 |
1 |
|
T25 |
1 |
| false |
616 |
1 |
|
T6 |
9 |
|
T25 |
2 |
|
T191 |
1 |
| true |
410 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T25 |
2 |
| others[1] |
101 |
1 |
|
T23 |
1 |
|
T24 |
1 |
|
T25 |
1 |
| others[2] |
85 |
1 |
|
T25 |
1 |
|
T52 |
6 |
|
T109 |
3 |
| others[3] |
162 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T25 |
4 |
| false |
57 |
1 |
|
T21 |
1 |
|
T109 |
2 |
|
T114 |
1 |
| true |
6414 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T3 |
1 |
|
T38 |
2 |
|
T25 |
1 |
| others[1] |
239 |
1 |
|
T21 |
1 |
|
T38 |
2 |
|
T4 |
1 |
| others[2] |
235 |
1 |
|
T23 |
1 |
|
T39 |
1 |
|
T52 |
9 |
| others[3] |
395 |
1 |
|
T38 |
2 |
|
T25 |
1 |
|
T52 |
21 |
| false |
122 |
1 |
|
T42 |
1 |
|
T25 |
1 |
|
T45 |
3 |
| true |
5708 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T6 |
11 |
|
T21 |
1 |
|
T25 |
1 |
| others[1] |
1127 |
1 |
|
T1 |
1 |
|
T6 |
12 |
|
T19 |
1 |
| others[2] |
1083 |
1 |
|
T6 |
12 |
|
T18 |
1 |
|
T20 |
1 |
| others[3] |
1748 |
1 |
|
T2 |
1 |
|
T6 |
20 |
|
T23 |
2 |
| false |
551 |
1 |
|
T6 |
7 |
|
T74 |
1 |
|
T76 |
5 |
| true |
1373 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T38 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T24 |
1 |
| others[1] |
253 |
1 |
|
T38 |
2 |
|
T4 |
1 |
|
T25 |
1 |
| others[2] |
217 |
1 |
|
T1 |
1 |
|
T38 |
1 |
|
T25 |
1 |
| others[3] |
389 |
1 |
|
T3 |
1 |
|
T38 |
3 |
|
T44 |
1 |
| false |
104 |
1 |
|
T52 |
4 |
|
T109 |
2 |
|
T114 |
1 |
| true |
5723 |
1 |
|
T2 |
1 |
|
T6 |
62 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T41 |
1 |
|
T74 |
1 |
|
T52 |
11 |
| others[1] |
236 |
1 |
|
T25 |
1 |
|
T45 |
1 |
|
T52 |
11 |
| others[2] |
229 |
1 |
|
T39 |
1 |
|
T25 |
1 |
|
T52 |
7 |
| others[3] |
333 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| false |
112 |
1 |
|
T52 |
4 |
|
T109 |
6 |
|
T200 |
1 |
| true |
5807 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T1 |
1 |
|
T6 |
10 |
|
T29 |
1 |
| others[1] |
1269 |
1 |
|
T6 |
17 |
|
T21 |
2 |
|
T23 |
1 |
| others[2] |
1301 |
1 |
|
T6 |
9 |
|
T23 |
1 |
|
T24 |
1 |
| others[3] |
2095 |
1 |
|
T6 |
12 |
|
T18 |
1 |
|
T43 |
1 |
| false |
640 |
1 |
|
T2 |
1 |
|
T6 |
14 |
|
T24 |
1 |
| true |
422 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T2 |
1 |
|
T6 |
8 |
|
T18 |
1 |
| others[1] |
1292 |
1 |
|
T1 |
1 |
|
T6 |
14 |
|
T25 |
3 |
| others[2] |
1276 |
1 |
|
T6 |
17 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
2109 |
1 |
|
T6 |
22 |
|
T23 |
1 |
|
T24 |
1 |
| false |
597 |
1 |
|
T6 |
1 |
|
T25 |
1 |
|
T76 |
7 |
| true |
406 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T21 |
1 |
|
T25 |
3 |
|
T52 |
4 |
| others[1] |
98 |
1 |
|
T25 |
1 |
|
T52 |
5 |
|
T109 |
1 |
| others[2] |
105 |
1 |
|
T23 |
2 |
|
T24 |
1 |
|
T25 |
3 |
| others[3] |
184 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| false |
56 |
1 |
|
T52 |
1 |
|
T109 |
2 |
|
T216 |
1 |
| true |
6388 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T29 |
1 |
|
T38 |
3 |
|
T25 |
1 |
| others[1] |
236 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T45 |
2 |
| others[2] |
240 |
1 |
|
T52 |
10 |
|
T109 |
14 |
|
T49 |
1 |
| others[3] |
386 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T38 |
2 |
| false |
116 |
1 |
|
T34 |
1 |
|
T52 |
3 |
|
T109 |
3 |
| true |
5731 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1145 |
1 |
|
T1 |
1 |
|
T6 |
10 |
|
T23 |
1 |
| others[1] |
1064 |
1 |
|
T6 |
12 |
|
T23 |
1 |
|
T25 |
1 |
| others[2] |
1046 |
1 |
|
T6 |
11 |
|
T10 |
1 |
|
T24 |
1 |
| others[3] |
1794 |
1 |
|
T6 |
20 |
|
T21 |
1 |
|
T29 |
1 |
| false |
553 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
9 |
| true |
1324 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T38 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T21 |
1 |
|
T38 |
2 |
|
T24 |
1 |
| others[1] |
223 |
1 |
|
T1 |
1 |
|
T38 |
1 |
|
T41 |
1 |
| others[2] |
216 |
1 |
|
T25 |
1 |
|
T52 |
7 |
|
T109 |
7 |
| others[3] |
379 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T23 |
1 |
| false |
139 |
1 |
|
T3 |
1 |
|
T38 |
1 |
|
T4 |
1 |
| true |
5744 |
1 |
|
T2 |
1 |
|
T6 |
62 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T25 |
2 |
|
T52 |
9 |
|
T109 |
6 |
| others[1] |
202 |
1 |
|
T23 |
1 |
|
T52 |
7 |
|
T109 |
15 |
| others[2] |
222 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[3] |
350 |
1 |
|
T1 |
1 |
|
T21 |
2 |
|
T23 |
1 |
| false |
117 |
1 |
|
T52 |
3 |
|
T109 |
6 |
|
T200 |
1 |
| true |
5827 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |