Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T6 |
15 |
|
T42 |
1 |
|
T25 |
2 |
| others[1] |
1213 |
1 |
|
T1 |
1 |
|
T6 |
15 |
|
T4 |
1 |
| others[2] |
1273 |
1 |
|
T2 |
1 |
|
T6 |
7 |
|
T21 |
1 |
| others[3] |
2090 |
1 |
|
T6 |
21 |
|
T21 |
1 |
|
T23 |
1 |
| false |
639 |
1 |
|
T6 |
4 |
|
T18 |
1 |
|
T25 |
1 |
| true |
421 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T6 |
7 |
|
T18 |
1 |
|
T29 |
1 |
| others[1] |
1212 |
1 |
|
T6 |
12 |
|
T21 |
1 |
|
T25 |
3 |
| others[2] |
1273 |
1 |
|
T1 |
1 |
|
T6 |
15 |
|
T25 |
4 |
| others[3] |
2092 |
1 |
|
T2 |
1 |
|
T6 |
20 |
|
T20 |
1 |
| false |
662 |
1 |
|
T6 |
8 |
|
T21 |
1 |
|
T76 |
9 |
| true |
405 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T25 |
3 |
|
T52 |
4 |
|
T109 |
3 |
| others[1] |
96 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T45 |
1 |
| others[2] |
101 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| others[3] |
171 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T74 |
1 |
| false |
63 |
1 |
|
T21 |
1 |
|
T52 |
3 |
|
T109 |
3 |
| true |
6398 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T53 |
1 |
|
T52 |
12 |
|
T109 |
10 |
| others[1] |
251 |
1 |
|
T24 |
1 |
|
T45 |
1 |
|
T52 |
8 |
| others[2] |
246 |
1 |
|
T23 |
1 |
|
T52 |
8 |
|
T109 |
10 |
| others[3] |
366 |
1 |
|
T3 |
1 |
|
T29 |
1 |
|
T25 |
2 |
| false |
112 |
1 |
|
T21 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| true |
5712 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T21 |
1 |
| others[1] |
1083 |
1 |
|
T6 |
13 |
|
T23 |
1 |
|
T38 |
2 |
| others[2] |
1043 |
1 |
|
T6 |
14 |
|
T38 |
1 |
|
T24 |
1 |
| others[3] |
1803 |
1 |
|
T1 |
1 |
|
T6 |
17 |
|
T29 |
1 |
| false |
521 |
1 |
|
T6 |
7 |
|
T18 |
1 |
|
T21 |
1 |
| true |
1381 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T38 |
2 |
| others[1] |
225 |
1 |
|
T21 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| others[2] |
223 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T38 |
1 |
| others[3] |
383 |
1 |
|
T38 |
2 |
|
T4 |
1 |
|
T39 |
1 |
| false |
121 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T25 |
1 |
| true |
5719 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T29 |
1 |
|
T52 |
9 |
|
T109 |
12 |
| others[1] |
218 |
1 |
|
T23 |
1 |
|
T41 |
1 |
|
T24 |
1 |
| others[2] |
252 |
1 |
|
T23 |
1 |
|
T4 |
1 |
|
T45 |
1 |
| others[3] |
383 |
1 |
|
T21 |
1 |
|
T25 |
1 |
|
T52 |
14 |
| false |
121 |
1 |
|
T52 |
2 |
|
T109 |
7 |
|
T345 |
1 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T6 |
8 |
|
T29 |
1 |
|
T23 |
1 |
| others[1] |
1260 |
1 |
|
T6 |
16 |
|
T21 |
1 |
|
T24 |
1 |
| others[2] |
1221 |
1 |
|
T6 |
14 |
|
T21 |
1 |
|
T23 |
1 |
| others[3] |
2119 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
18 |
| false |
654 |
1 |
|
T6 |
6 |
|
T24 |
1 |
|
T25 |
1 |
| true |
412 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T25 |
1 |
| others[1] |
1257 |
1 |
|
T6 |
12 |
|
T21 |
1 |
|
T23 |
2 |
| others[2] |
1214 |
1 |
|
T6 |
14 |
|
T18 |
1 |
|
T25 |
2 |
| others[3] |
2158 |
1 |
|
T6 |
23 |
|
T21 |
1 |
|
T29 |
1 |
| false |
638 |
1 |
|
T1 |
1 |
|
T6 |
2 |
|
T35 |
1 |
| true |
405 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T21 |
1 |
|
T39 |
1 |
|
T25 |
1 |
| others[1] |
102 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T52 |
3 |
| others[2] |
102 |
1 |
|
T21 |
1 |
|
T24 |
1 |
|
T25 |
3 |
| others[3] |
153 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T23 |
2 |
| false |
45 |
1 |
|
T52 |
5 |
|
T109 |
2 |
|
T116 |
4 |
| true |
6418 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T25 |
1 |
| others[1] |
256 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T42 |
1 |
| others[2] |
223 |
1 |
|
T38 |
2 |
|
T39 |
1 |
|
T25 |
1 |
| others[3] |
368 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T38 |
2 |
| false |
129 |
1 |
|
T38 |
1 |
|
T24 |
1 |
|
T52 |
6 |
| true |
5717 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
15 |
| others[1] |
1087 |
1 |
|
T3 |
1 |
|
T6 |
11 |
|
T29 |
1 |
| others[2] |
1096 |
1 |
|
T6 |
11 |
|
T20 |
1 |
|
T21 |
2 |
| others[3] |
1750 |
1 |
|
T6 |
19 |
|
T10 |
1 |
|
T23 |
1 |
| false |
524 |
1 |
|
T6 |
6 |
|
T25 |
2 |
|
T76 |
6 |
| true |
1406 |
1 |
|
T41 |
1 |
|
T45 |
3 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T4 |
1 |
| others[1] |
222 |
1 |
|
T45 |
1 |
|
T52 |
12 |
|
T109 |
11 |
| others[2] |
216 |
1 |
|
T38 |
2 |
|
T39 |
1 |
|
T52 |
8 |
| others[3] |
396 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T38 |
3 |
| false |
127 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T52 |
5 |
| true |
5727 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T25 |
1 |
|
T45 |
1 |
|
T52 |
7 |
| others[1] |
212 |
1 |
|
T23 |
1 |
|
T52 |
11 |
|
T109 |
9 |
| others[2] |
215 |
1 |
|
T39 |
1 |
|
T25 |
1 |
|
T52 |
5 |
| others[3] |
377 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T25 |
2 |
| false |
106 |
1 |
|
T24 |
1 |
|
T45 |
1 |
|
T52 |
5 |
| true |
5794 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T20 |
1 |
| others[1] |
1326 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
14 |
| others[2] |
1207 |
1 |
|
T6 |
11 |
|
T24 |
2 |
|
T25 |
1 |
| others[3] |
2102 |
1 |
|
T6 |
16 |
|
T21 |
1 |
|
T23 |
1 |
| false |
634 |
1 |
|
T6 |
6 |
|
T76 |
7 |
|
T52 |
10 |
| true |
416 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T6 |
18 |
|
T21 |
1 |
|
T43 |
1 |
| others[1] |
1221 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T23 |
1 |
| others[2] |
1262 |
1 |
|
T6 |
9 |
|
T21 |
1 |
|
T25 |
3 |
| others[3] |
2136 |
1 |
|
T1 |
1 |
|
T6 |
18 |
|
T18 |
1 |
| false |
657 |
1 |
|
T6 |
6 |
|
T23 |
1 |
|
T76 |
4 |
| true |
398 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T52 |
2 |
| others[1] |
107 |
1 |
|
T1 |
1 |
|
T25 |
3 |
|
T52 |
5 |
| others[2] |
99 |
1 |
|
T23 |
2 |
|
T52 |
5 |
|
T109 |
4 |
| others[3] |
189 |
1 |
|
T21 |
2 |
|
T24 |
1 |
|
T39 |
1 |
| false |
48 |
1 |
|
T29 |
1 |
|
T52 |
1 |
|
T109 |
1 |
| true |
6373 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T38 |
2 |
|
T24 |
2 |
|
T52 |
6 |
| others[1] |
239 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T38 |
2 |
| others[2] |
232 |
1 |
|
T25 |
1 |
|
T45 |
1 |
|
T52 |
7 |
| others[3] |
422 |
1 |
|
T3 |
1 |
|
T23 |
1 |
|
T38 |
2 |
| false |
142 |
1 |
|
T29 |
1 |
|
T39 |
1 |
|
T45 |
1 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T6 |
62 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T6 |
17 |
|
T23 |
1 |
|
T38 |
1 |
| others[1] |
1053 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T29 |
1 |
| others[2] |
1115 |
1 |
|
T6 |
12 |
|
T19 |
1 |
|
T21 |
1 |
| others[3] |
1825 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
15 |
| false |
562 |
1 |
|
T6 |
3 |
|
T25 |
1 |
|
T45 |
1 |
| true |
1301 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T38 |
1 |
|
T4 |
1 |
|
T41 |
1 |
| others[1] |
234 |
1 |
|
T20 |
1 |
|
T38 |
1 |
|
T42 |
1 |
| others[2] |
241 |
1 |
|
T38 |
1 |
|
T24 |
1 |
|
T44 |
1 |
| others[3] |
351 |
1 |
|
T1 |
1 |
|
T21 |
2 |
|
T38 |
3 |
| false |
122 |
1 |
|
T24 |
1 |
|
T45 |
1 |
|
T52 |
7 |
| true |
5753 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T52 |
6 |
| others[1] |
242 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[2] |
241 |
1 |
|
T23 |
1 |
|
T41 |
1 |
|
T52 |
8 |
| others[3] |
345 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T45 |
3 |
| false |
119 |
1 |
|
T52 |
8 |
|
T109 |
4 |
|
T114 |
8 |
| true |
5752 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T6 |
8 |
|
T24 |
1 |
|
T25 |
1 |
| others[1] |
1238 |
1 |
|
T1 |
1 |
|
T6 |
14 |
|
T76 |
12 |
| others[2] |
1258 |
1 |
|
T2 |
1 |
|
T6 |
4 |
|
T18 |
1 |
| others[3] |
2136 |
1 |
|
T6 |
23 |
|
T19 |
1 |
|
T21 |
2 |
| false |
638 |
1 |
|
T6 |
13 |
|
T23 |
1 |
|
T25 |
2 |
| true |
419 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T6 |
11 |
|
T25 |
2 |
|
T144 |
1 |
| others[1] |
1255 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T29 |
1 |
| others[2] |
1268 |
1 |
|
T1 |
1 |
|
T6 |
14 |
|
T19 |
1 |
| others[3] |
2075 |
1 |
|
T6 |
18 |
|
T18 |
1 |
|
T21 |
1 |
| false |
703 |
1 |
|
T6 |
9 |
|
T21 |
1 |
|
T23 |
2 |
| true |
402 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T24 |
1 |
|
T25 |
3 |
|
T52 |
3 |
| others[1] |
115 |
1 |
|
T25 |
1 |
|
T52 |
7 |
|
T109 |
7 |
| others[2] |
96 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| others[3] |
152 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| false |
51 |
1 |
|
T29 |
1 |
|
T52 |
1 |
|
T109 |
4 |
| true |
6416 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T38 |
1 |
| others[1] |
252 |
1 |
|
T38 |
3 |
|
T41 |
1 |
|
T25 |
2 |
| others[2] |
214 |
1 |
|
T44 |
1 |
|
T45 |
1 |
|
T52 |
4 |
| others[3] |
413 |
1 |
|
T21 |
1 |
|
T38 |
1 |
|
T45 |
1 |
| false |
116 |
1 |
|
T38 |
1 |
|
T52 |
6 |
|
T109 |
1 |
| true |
5689 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T6 |
9 |
|
T21 |
1 |
|
T23 |
1 |
| others[1] |
1074 |
1 |
|
T6 |
16 |
|
T29 |
1 |
|
T23 |
1 |
| others[2] |
1102 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[3] |
1824 |
1 |
|
T6 |
20 |
|
T18 |
1 |
|
T21 |
1 |
| false |
524 |
1 |
|
T6 |
8 |
|
T20 |
1 |
|
T38 |
2 |
| true |
1369 |
1 |
|
T19 |
1 |
|
T11 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T23 |
1 |
|
T52 |
8 |
|
T109 |
11 |
| others[1] |
225 |
1 |
|
T21 |
1 |
|
T45 |
1 |
|
T52 |
11 |
| others[2] |
244 |
1 |
|
T3 |
1 |
|
T39 |
1 |
|
T25 |
1 |
| others[3] |
360 |
1 |
|
T24 |
1 |
|
T34 |
1 |
|
T74 |
1 |
| false |
127 |
1 |
|
T41 |
1 |
|
T52 |
3 |
|
T109 |
10 |
| true |
5739 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T23 |
1 |
|
T45 |
2 |
|
T74 |
1 |
| others[1] |
194 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T4 |
1 |
| others[2] |
195 |
1 |
|
T41 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[3] |
340 |
1 |
|
T25 |
3 |
|
T52 |
12 |
|
T109 |
15 |
| false |
111 |
1 |
|
T24 |
1 |
|
T52 |
6 |
|
T109 |
5 |
| true |
5848 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
13 |
| others[1] |
1288 |
1 |
|
T6 |
11 |
|
T21 |
2 |
|
T29 |
1 |
| others[2] |
1222 |
1 |
|
T6 |
10 |
|
T23 |
1 |
|
T25 |
2 |
| others[3] |
2039 |
1 |
|
T6 |
22 |
|
T19 |
1 |
|
T42 |
1 |
| false |
661 |
1 |
|
T6 |
6 |
|
T23 |
1 |
|
T4 |
1 |
| true |
437 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T346 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
2 |
1 |
|
T347 |
1 |
|
T348 |
1 |
|
- |
- |
| others[2] |
3 |
1 |
|
T112 |
1 |
|
T349 |
1 |
|
T350 |
1 |
| others[3] |
7 |
1 |
|
T351 |
1 |
|
T352 |
1 |
|
T353 |
1 |
| false |
3 |
1 |
|
T334 |
1 |
|
T354 |
1 |
|
T355 |
1 |
| true |
28 |
1 |
|
T50 |
1 |
|
T266 |
1 |
|
T303 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T356 |
1 |
|
T357 |
1 |
|
- |
- |
| others[1] |
1 |
1 |
|
T349 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
5 |
1 |
|
T352 |
1 |
|
T350 |
1 |
|
T358 |
1 |
| others[3] |
1 |
1 |
|
T359 |
1 |
|
- |
- |
|
- |
- |
| false |
12 |
1 |
|
T112 |
1 |
|
T360 |
1 |
|
T351 |
1 |
| true |
23 |
1 |
|
T50 |
1 |
|
T266 |
1 |
|
T303 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |