Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10017 |
1 |
|
T6 |
8 |
|
T24 |
1 |
|
T25 |
1 |
| others[1] |
481 |
1 |
|
T6 |
4 |
|
T21 |
1 |
|
T38 |
1 |
| others[2] |
506 |
1 |
|
T3 |
1 |
|
T6 |
4 |
|
T29 |
1 |
| others[3] |
789 |
1 |
|
T2 |
1 |
|
T6 |
8 |
|
T38 |
2 |
| false |
280 |
1 |
|
T1 |
1 |
|
T6 |
4 |
|
T21 |
1 |
| true |
2161 |
1 |
|
T6 |
34 |
|
T18 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9849 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T73 |
128 |
| others[1] |
264 |
1 |
|
T29 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| others[2] |
231 |
1 |
|
T20 |
1 |
|
T52 |
9 |
|
T109 |
11 |
| others[3] |
416 |
1 |
|
T21 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| false |
136 |
1 |
|
T25 |
1 |
|
T52 |
8 |
|
T109 |
4 |
| true |
3338 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9827 |
1 |
|
T29 |
1 |
|
T35 |
1 |
|
T73 |
128 |
| others[1] |
255 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T45 |
1 |
| others[2] |
253 |
1 |
|
T18 |
1 |
|
T24 |
1 |
|
T191 |
1 |
| others[3] |
459 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T25 |
2 |
| false |
121 |
1 |
|
T21 |
1 |
|
T4 |
1 |
|
T45 |
1 |
| true |
3319 |
1 |
|
T3 |
1 |
|
T6 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10372 |
1 |
|
T6 |
14 |
|
T23 |
1 |
|
T42 |
1 |
| others[1] |
777 |
1 |
|
T6 |
9 |
|
T23 |
1 |
|
T25 |
1 |
| others[2] |
837 |
1 |
|
T1 |
1 |
|
T6 |
12 |
|
T43 |
1 |
| others[3] |
1309 |
1 |
|
T6 |
16 |
|
T18 |
1 |
|
T29 |
1 |
| false |
449 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T25 |
1 |
| true |
490 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10348 |
1 |
|
T6 |
11 |
|
T35 |
1 |
|
T73 |
128 |
| others[1] |
837 |
1 |
|
T1 |
1 |
|
T6 |
13 |
|
T18 |
1 |
| others[2] |
809 |
1 |
|
T2 |
1 |
|
T6 |
13 |
|
T42 |
1 |
| others[3] |
1338 |
1 |
|
T6 |
20 |
|
T19 |
1 |
|
T21 |
1 |
| false |
417 |
1 |
|
T6 |
5 |
|
T23 |
1 |
|
T43 |
1 |
| true |
485 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2470 |
1 |
|
T6 |
12 |
|
T29 |
1 |
|
T25 |
2 |
| others[1] |
2389 |
1 |
|
T6 |
12 |
|
T23 |
1 |
|
T4 |
1 |
| others[2] |
2480 |
1 |
|
T6 |
13 |
|
T21 |
1 |
|
T23 |
1 |
| others[3] |
4062 |
1 |
|
T6 |
18 |
|
T18 |
1 |
|
T21 |
1 |
| false |
1298 |
1 |
|
T2 |
1 |
|
T6 |
7 |
|
T24 |
1 |
| true |
1535 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9817 |
1 |
|
T29 |
1 |
|
T25 |
1 |
|
T73 |
128 |
| others[1] |
287 |
1 |
|
T41 |
1 |
|
T24 |
1 |
|
T44 |
1 |
| others[2] |
288 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T21 |
1 |
| others[3] |
463 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T4 |
1 |
| false |
145 |
1 |
|
T39 |
1 |
|
T25 |
3 |
|
T52 |
6 |
| true |
3234 |
1 |
|
T3 |
1 |
|
T6 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10064 |
1 |
|
T6 |
8 |
|
T18 |
1 |
|
T21 |
1 |
| others[1] |
474 |
1 |
|
T6 |
7 |
|
T20 |
1 |
|
T21 |
1 |
| others[2] |
489 |
1 |
|
T6 |
8 |
|
T29 |
1 |
|
T25 |
2 |
| others[3] |
806 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
11 |
| false |
253 |
1 |
|
T6 |
4 |
|
T23 |
1 |
|
T42 |
1 |
| true |
2148 |
1 |
|
T1 |
1 |
|
T6 |
24 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9814 |
1 |
|
T73 |
128 |
|
T34 |
1 |
|
T144 |
1 |
| others[1] |
286 |
1 |
|
T21 |
1 |
|
T42 |
1 |
|
T43 |
1 |
| others[2] |
261 |
1 |
|
T45 |
1 |
|
T52 |
5 |
|
T109 |
10 |
| others[3] |
457 |
1 |
|
T1 |
1 |
|
T41 |
1 |
|
T25 |
2 |
| false |
135 |
1 |
|
T25 |
1 |
|
T74 |
1 |
|
T52 |
3 |
| true |
3281 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9813 |
1 |
|
T25 |
2 |
|
T45 |
1 |
|
T73 |
128 |
| others[1] |
264 |
1 |
|
T24 |
1 |
|
T74 |
1 |
|
T191 |
1 |
| others[2] |
228 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[3] |
424 |
1 |
|
T43 |
1 |
|
T25 |
1 |
|
T52 |
19 |
| false |
151 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T4 |
1 |
| true |
3354 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10388 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T24 |
2 |
| others[1] |
796 |
1 |
|
T6 |
13 |
|
T21 |
1 |
|
T43 |
1 |
| others[2] |
840 |
1 |
|
T1 |
1 |
|
T6 |
10 |
|
T21 |
1 |
| others[3] |
1329 |
1 |
|
T6 |
19 |
|
T23 |
1 |
|
T25 |
1 |
| false |
399 |
1 |
|
T2 |
1 |
|
T6 |
5 |
|
T29 |
1 |
| true |
482 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10398 |
1 |
|
T2 |
1 |
|
T6 |
17 |
|
T18 |
1 |
| others[1] |
798 |
1 |
|
T6 |
11 |
|
T25 |
1 |
|
T52 |
17 |
| others[2] |
791 |
1 |
|
T6 |
9 |
|
T25 |
1 |
|
T52 |
18 |
| others[3] |
1309 |
1 |
|
T1 |
1 |
|
T6 |
18 |
|
T20 |
1 |
| false |
453 |
1 |
|
T6 |
7 |
|
T19 |
1 |
|
T23 |
1 |
| true |
485 |
1 |
|
T3 |
1 |
|
T21 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2494 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T23 |
1 |
| others[1] |
2557 |
1 |
|
T6 |
17 |
|
T29 |
1 |
|
T25 |
2 |
| others[2] |
2420 |
1 |
|
T6 |
10 |
|
T18 |
1 |
|
T24 |
2 |
| others[3] |
4065 |
1 |
|
T6 |
21 |
|
T21 |
2 |
|
T23 |
1 |
| false |
1222 |
1 |
|
T6 |
4 |
|
T25 |
1 |
|
T45 |
1 |
| true |
1476 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9815 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T38 |
3 |
| others[1] |
279 |
1 |
|
T38 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[2] |
281 |
1 |
|
T38 |
1 |
|
T24 |
1 |
|
T35 |
1 |
| others[3] |
440 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T38 |
1 |
| false |
156 |
1 |
|
T41 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| true |
3263 |
1 |
|
T3 |
1 |
|
T6 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10080 |
1 |
|
T6 |
4 |
|
T19 |
1 |
|
T25 |
2 |
| others[1] |
439 |
1 |
|
T6 |
11 |
|
T20 |
1 |
|
T21 |
2 |
| others[2] |
443 |
1 |
|
T3 |
1 |
|
T6 |
3 |
|
T18 |
1 |
| others[3] |
816 |
1 |
|
T1 |
1 |
|
T6 |
8 |
|
T39 |
1 |
| false |
237 |
1 |
|
T6 |
5 |
|
T23 |
1 |
|
T52 |
5 |
| true |
2219 |
1 |
|
T2 |
1 |
|
T6 |
31 |
|
T38 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9822 |
1 |
|
T24 |
1 |
|
T44 |
1 |
|
T25 |
1 |
| others[1] |
267 |
1 |
|
T1 |
1 |
|
T38 |
1 |
|
T45 |
2 |
| others[2] |
254 |
1 |
|
T29 |
1 |
|
T38 |
1 |
|
T4 |
1 |
| others[3] |
451 |
1 |
|
T21 |
1 |
|
T38 |
3 |
|
T43 |
1 |
| false |
134 |
1 |
|
T38 |
1 |
|
T45 |
1 |
|
T52 |
7 |
| true |
3306 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9835 |
1 |
|
T18 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| others[1] |
245 |
1 |
|
T29 |
1 |
|
T4 |
1 |
|
T45 |
1 |
| others[2] |
218 |
1 |
|
T74 |
1 |
|
T52 |
4 |
|
T109 |
7 |
| others[3] |
409 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T21 |
1 |
| false |
139 |
1 |
|
T23 |
1 |
|
T41 |
1 |
|
T25 |
3 |
| true |
3388 |
1 |
|
T3 |
1 |
|
T6 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10342 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
10 |
| others[1] |
789 |
1 |
|
T6 |
12 |
|
T19 |
1 |
|
T21 |
1 |
| others[2] |
778 |
1 |
|
T6 |
9 |
|
T25 |
1 |
|
T33 |
1 |
| others[3] |
1371 |
1 |
|
T6 |
21 |
|
T18 |
1 |
|
T25 |
2 |
| false |
460 |
1 |
|
T6 |
10 |
|
T74 |
1 |
|
T52 |
10 |
| true |
494 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10343 |
1 |
|
T2 |
1 |
|
T6 |
7 |
|
T24 |
1 |
| others[1] |
782 |
1 |
|
T6 |
15 |
|
T23 |
1 |
|
T25 |
1 |
| others[2] |
807 |
1 |
|
T6 |
11 |
|
T21 |
1 |
|
T24 |
1 |
| others[3] |
1355 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T21 |
1 |
| false |
445 |
1 |
|
T6 |
8 |
|
T18 |
1 |
|
T144 |
1 |
| true |
502 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2445 |
1 |
|
T6 |
7 |
|
T23 |
1 |
|
T24 |
2 |
| others[1] |
2433 |
1 |
|
T6 |
11 |
|
T21 |
1 |
|
T39 |
1 |
| others[2] |
2477 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
14 |
| others[3] |
4119 |
1 |
|
T6 |
22 |
|
T18 |
1 |
|
T21 |
1 |
| false |
1272 |
1 |
|
T6 |
8 |
|
T25 |
1 |
|
T45 |
1 |
| true |
1488 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9827 |
1 |
|
T39 |
1 |
|
T25 |
1 |
|
T73 |
128 |
| others[1] |
251 |
1 |
|
T45 |
1 |
|
T52 |
9 |
|
T109 |
12 |
| others[2] |
275 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
460 |
1 |
|
T3 |
1 |
|
T29 |
1 |
|
T23 |
1 |
| false |
150 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T42 |
1 |
| true |
3271 |
1 |
|
T6 |
62 |
|
T18 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9988 |
1 |
|
T6 |
4 |
|
T21 |
1 |
|
T38 |
1 |
| others[1] |
440 |
1 |
|
T6 |
8 |
|
T21 |
1 |
|
T29 |
1 |
| others[2] |
448 |
1 |
|
T6 |
5 |
|
T10 |
1 |
|
T23 |
1 |
| others[3] |
805 |
1 |
|
T1 |
1 |
|
T6 |
10 |
|
T23 |
1 |
| false |
250 |
1 |
|
T3 |
1 |
|
T6 |
4 |
|
T42 |
1 |
| true |
2303 |
1 |
|
T2 |
1 |
|
T6 |
31 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9809 |
1 |
|
T38 |
1 |
|
T4 |
1 |
|
T41 |
1 |
| others[1] |
241 |
1 |
|
T3 |
1 |
|
T21 |
1 |
|
T38 |
1 |
| others[2] |
269 |
1 |
|
T38 |
1 |
|
T25 |
1 |
|
T74 |
1 |
| others[3] |
468 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| false |
131 |
1 |
|
T38 |
1 |
|
T52 |
6 |
|
T109 |
4 |
| true |
3316 |
1 |
|
T1 |
1 |
|
T6 |
62 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9815 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T45 |
1 |
| others[1] |
274 |
1 |
|
T21 |
1 |
|
T39 |
1 |
|
T25 |
1 |
| others[2] |
266 |
1 |
|
T18 |
1 |
|
T45 |
2 |
|
T74 |
1 |
| others[3] |
408 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| false |
137 |
1 |
|
T25 |
1 |
|
T45 |
1 |
|
T52 |
6 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10368 |
1 |
|
T6 |
16 |
|
T4 |
1 |
|
T43 |
1 |
| others[1] |
809 |
1 |
|
T6 |
15 |
|
T23 |
1 |
|
T35 |
1 |
| others[2] |
785 |
1 |
|
T6 |
9 |
|
T18 |
1 |
|
T25 |
2 |
| others[3] |
1387 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
20 |
| false |
403 |
1 |
|
T6 |
2 |
|
T33 |
1 |
|
T52 |
14 |
| true |
482 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |