Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226036	1		T1	155		T2	454		T3	4
auto[FlashEraseBank]	220513	1		T1	45		T2	463		T3	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	248505	1		T1	93		T2	917		T3	10
auto[FlashOpProgram]	178127	1		T1	75		T3	2		T23	4
auto[FlashOpErase]	15917	1		T1	32		T20	31		T11	1
auto[FlashOpInvalid]	4000	1		T76	200		T124	200		T115	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	248505	1		T1	93		T2	917		T3	10
op[FlashOpProgram]	178127	1		T1	75		T3	2		T23	4
op[FlashOpErase]	15917	1		T1	32		T20	31		T11	1
read_erase_read	733	1		T1	11		T20	17		T50	3
read_prog_read	1242	1		T1	10		T3	2		T4	8

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	304988	1		T1	196		T2	907		T6	62
auto[FlashPartInfo]	138199	1		T1	3		T3	12		T20	42
auto[FlashPartInfo1]	764	1		T1	1		T2	4		T4	6
auto[FlashPartInfo2]	2598	1		T2	6		T20	1		T4	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183590	1		T1	90		T2	907		T6	62
auto[FlashPartData]	auto[FlashOpProgram]	113792	1		T1	74		T23	4		T4	1453
auto[FlashPartData]	auto[FlashOpErase]	3684	1		T1	32		T20	14		T11	1
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T76	192		T124	194		T115	196
auto[FlashPartInfo]	auto[FlashOpRead]	62703	1		T1	2		T3	10		T20	25
auto[FlashPartInfo]	auto[FlashOpProgram]	63278	1		T1	1		T3	2		T4	271
auto[FlashPartInfo]	auto[FlashOpErase]	12150	1		T20	17		T73	188		T50	9
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T76	4		T124	6		T115	2
auto[FlashPartInfo1]	auto[FlashOpRead]	650	1		T1	1		T2	4		T4	6
auto[FlashPartInfo1]	auto[FlashOpProgram]	101	1		T76	1		T115	1		T125	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T76	1		T115	1		T125	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T76	2		T115	2		T125	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1562	1		T2	6		T20	1		T4	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	956	1		T4	5		T39	6		T76	1
auto[FlashPartInfo2]	auto[FlashOpErase]	78	1		T76	1		T109	1		T362	15
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T76	2		-	-		-	-