Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.95	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	8	24	75.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	8	24	75.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30817	1		T1	24		T73	388		T74	28
auto[1]	14	1		T54	1		T158	2		T310	1
auto[2]	55	1		T308	24		T146	4		T147	4
auto[3]	270	1		T44	1		T55	2		T311	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7806	1		T1	6		T44	1		T73	97
evic_idx[1]	7799	1		T1	6		T73	97		T74	7
evic_idx[2]	7785	1		T1	6		T73	97		T74	7
evic_idx[3]	7766	1		T1	6		T73	97		T74	7

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30182	1		T73	388		T74	4		T76	400
evic_op[2]	429	1		T44	1		T109	4		T110	8

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	8	24	75.00	8

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7500	1		T73	97		T74	1		T76	100
evic_idx[0]	evic_op[1]	auto[3]	54	1		T312	18		T259	3		T263	5
evic_idx[0]	evic_op[2]	auto[0]	78	1		T109	1		T110	2		T112	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T158	1		T310	1		T264	1
evic_idx[0]	evic_op[2]	auto[2]	10	1		T308	8		T313	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	24	1		T44	1		T185	1		T186	1
evic_idx[1]	evic_op[1]	auto[0]	7493	1		T73	97		T74	1		T76	100
evic_idx[1]	evic_op[1]	auto[3]	60	1		T312	19		T259	1		T263	5
evic_idx[1]	evic_op[2]	auto[0]	80	1		T109	1		T110	2		T112	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T158	1		T252	1		T264	1
evic_idx[1]	evic_op[2]	auto[2]	16	1		T308	7		T314	1		T315	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T316	1		T186	1		T317	1
evic_idx[2]	evic_op[1]	auto[0]	7492	1		T73	97		T74	1		T76	100
evic_idx[2]	evic_op[1]	auto[3]	52	1		T312	13		T259	1		T263	4
evic_idx[2]	evic_op[2]	auto[0]	81	1		T109	1		T110	2		T112	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T54	1		T264	1		T318	1
evic_idx[2]	evic_op[2]	auto[2]	8	1		T308	4		T315	1		T313	2
evic_idx[2]	evic_op[2]	auto[3]	13	1		T55	1		T311	1		T317	1
evic_idx[3]	evic_op[1]	auto[0]	7488	1		T73	97		T74	1		T76	100
evic_idx[3]	evic_op[1]	auto[3]	43	1		T312	7		T259	4		T263	2
evic_idx[3]	evic_op[2]	auto[0]	76	1		T109	1		T110	2		T112	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T319	1		T264	2		T320	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T308	5		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	13	1		T55	1		T317	1		T260	1