Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
instr_type_cp	3	0	3	100.00	100	1	1	0
key_cp	2	0	2	100.00	100	1	1	2

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_instr_cross	6	0	6	100.00	100	1	1	0

Summary for Variable instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for instr_type_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	4749	1		T15	5		T6	216		T36	72
instr_types[0]	6243	1		T6	255		T36	312		T37	300
instr_types[1]	4348808	1		T15	15		T2	16097		T3	5

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Summary for Variable key_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4357391	1		T15	20		T2	16097		T3	5
auto[1]	2409	1		T6	208		T36	246		T37	234

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Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for key_instr_cross

Bins

key_cp	instr_type_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	others	4249	1		T15	5		T6	141		T36	48
auto[0]	instr_types[0]	5296	1		T6	218		T36	142		T37	250
auto[0]	instr_types[1]	4347846	1		T15	15		T2	16097		T3	5
auto[1]	others	500	1		T6	75		T36	24		T37	69
auto[1]	instr_types[0]	947	1		T6	37		T36	170		T37	50
auto[1]	instr_types[1]	962	1		T6	96		T36	52		T37	115