Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	55081	1		T46	6239		T47	1691		T48	1806
prog_lvl[2]	4034	1		T47	807		T48	902		T363	1
prog_lvl[3]	5	1		T47	1		T48	1		T364	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	9905	1		T184	29		T201	12		T365	81
rd_lvl[2]	27633	1		T42	10		T191	3521		T53	53
rd_lvl[3]	20747	1		T42	17		T191	2207		T182	55
rd_lvl[4]	12808	1		T42	22		T184	21		T201	253
rd_lvl[5]	11846	1		T42	9		T184	1032		T201	2
rd_lvl[6]	12225	1		T42	398		T43	1331		T184	773
rd_lvl[7]	10498	1		T43	353		T201	870		T366	1007
rd_lvl[8]	5638	1		T144	1509		T366	565		T367	1
rd_lvl[9]	3465	1		T144	375		T367	35		T254	6
rd_lvl[10]	3212	1		T42	369		T201	80		T368	545
rd_lvl[11]	3102	1		T42	742		T107	416		T369	335
rd_lvl[12]	5024	1		T42	1		T107	258		T370	525
rd_lvl[13]	8569	1		T182	324		T302	529		T265	508
rd_lvl[14]	6561	1		T42	43		T53	696		T182	684
rd_lvl[15]	3843	1		T33	440		T53	544		T134	519