Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	337275	1		T1	2		T2	2		T3	1
all_pins[1]	337275	1		T1	2		T2	2		T3	1
all_pins[2]	337275	1		T1	2		T2	2		T3	1
all_pins[3]	337275	1		T1	2		T2	2		T3	1
all_pins[4]	337275	1		T1	2		T2	2		T3	1
all_pins[5]	337275	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1645504	1		T1	12		T2	12		T3	6
values[0x1]	378146	1		T42	2810		T43	2526		T33	2227
transitions[0x0=>0x1]	362632	1		T42	2413		T43	2526		T33	1553
transitions[0x1=>0x0]	362642	1		T42	2413		T43	2526		T33	1553

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	276336	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	60939	1		T162	4320		T46	2430		T163	4440
all_pins[0]	transitions[0x0=>0x1]	60922	1		T162	4320		T46	2430		T163	4440
all_pins[0]	transitions[0x1=>0x0]	65147	1		T46	6239		T47	3332		T48	3612
all_pins[1]	values[0x0]	272111	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	65164	1		T46	6239		T47	3332		T48	3612
all_pins[1]	transitions[0x0=>0x1]	65143	1		T46	6239		T47	3332		T48	3612
all_pins[1]	transitions[0x1=>0x0]	8306	1		T42	44		T33	673		T53	1070
all_pins[2]	values[0x0]	328948	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	8327	1		T42	44		T33	673		T53	1070
all_pins[2]	transitions[0x0=>0x1]	7011	1		T42	44		T33	336		T53	1051
all_pins[2]	transitions[0x1=>0x0]	146023	1		T42	1611		T43	1684		T33	440
all_pins[3]	values[0x0]	189936	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	147339	1		T42	1611		T43	1684		T33	777
all_pins[3]	transitions[0x0=>0x1]	133216	1		T42	1214		T43	1684		T33	440
all_pins[3]	transitions[0x1=>0x0]	82193	1		T42	758		T43	842		T33	440
all_pins[4]	values[0x0]	240959	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	96316	1		T42	1155		T43	842		T33	777
all_pins[4]	transitions[0x0=>0x1]	96299	1		T42	1155		T43	842		T33	777
all_pins[4]	transitions[0x1=>0x0]	44	1		T246	3		T322	1		T323	3
all_pins[5]	values[0x0]	337214	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	61	1		T244	1		T246	5		T322	1
all_pins[5]	transitions[0x0=>0x1]	41	1		T246	4		T323	2		T287	1
all_pins[5]	transitions[0x1=>0x0]	60929	1		T162	4320		T46	2430		T163	4440