Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	257	1		T244	4		T245	4		T246	7
all_values[1]	257	1		T244	4		T245	4		T246	7
all_values[2]	257	1		T244	4		T245	4		T246	7
all_values[3]	257	1		T244	4		T245	4		T246	7
all_values[4]	257	1		T244	4		T245	4		T246	7
all_values[5]	257	1		T244	4		T245	4		T246	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	845	1		T244	10		T245	15		T246	18
auto[1]	697	1		T244	14		T245	9		T246	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	615	1		T244	8		T245	11		T246	6
auto[1]	927	1		T244	16		T245	13		T246	36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	929	1		T244	15		T245	16		T246	18
auto[1]	613	1		T244	9		T245	8		T246	24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	60	1		T245	1		T283	2		T284	2
all_values[0]	auto[0]	auto[0]	auto[1]	29	1		T244	2		T246	2		T287	1
all_values[0]	auto[0]	auto[1]	auto[0]	36	1		T245	1		T322	2		T323	1
all_values[0]	auto[0]	auto[1]	auto[1]	23	1		T323	2		T284	1		T287	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T244	1		T245	1		T246	4
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T244	1		T245	1		T246	1
all_values[1]	auto[0]	auto[0]	auto[0]	72	1		T244	1		T245	4		T283	1
all_values[1]	auto[0]	auto[0]	auto[1]	21	1		T322	1		T283	1		T285	1
all_values[1]	auto[0]	auto[1]	auto[0]	32	1		T322	1		T323	2		T283	1
all_values[1]	auto[0]	auto[1]	auto[1]	27	1		T244	1		T246	2		T322	1
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T246	1		T322	1		T323	3
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T244	2		T246	4		T322	3
all_values[2]	auto[0]	auto[0]	auto[0]	61	1		T244	2		T245	1		T246	1
all_values[2]	auto[0]	auto[0]	auto[1]	24	1		T245	1		T322	1		T323	2
all_values[2]	auto[0]	auto[1]	auto[0]	49	1		T244	1		T246	1		T285	3
all_values[2]	auto[0]	auto[1]	auto[1]	26	1		T246	2		T322	1		T219	1
all_values[2]	auto[1]	auto[0]	auto[1]	53	1		T245	2		T246	1		T322	1
all_values[2]	auto[1]	auto[1]	auto[1]	44	1		T244	1		T246	2		T322	2
all_values[3]	auto[0]	auto[0]	auto[0]	57	1		T244	1		T246	3		T283	1
all_values[3]	auto[0]	auto[0]	auto[1]	31	1		T245	2		T322	1		T323	2
all_values[3]	auto[0]	auto[1]	auto[0]	38	1		T244	2		T283	1		T284	3
all_values[3]	auto[0]	auto[1]	auto[1]	29	1		T245	1		T246	1		T323	1
all_values[3]	auto[1]	auto[0]	auto[1]	50	1		T246	2		T322	4		T323	1
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T244	1		T245	1		T246	1
all_values[4]	auto[0]	auto[0]	auto[0]	66	1		T246	1		T322	1		T323	1
all_values[4]	auto[0]	auto[0]	auto[1]	22	1		T244	1		T245	1		T246	1
all_values[4]	auto[0]	auto[1]	auto[0]	39	1		T244	1		T322	3		T323	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T246	1		T323	1		T283	1
all_values[4]	auto[1]	auto[0]	auto[1]	51	1		T246	1		T322	2		T323	1
all_values[4]	auto[1]	auto[1]	auto[1]	50	1		T244	2		T245	3		T246	3
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T245	2		T323	1		T283	1
all_values[5]	auto[0]	auto[0]	auto[1]	24	1		T244	1		T323	1		T284	2
all_values[5]	auto[0]	auto[1]	auto[0]	51	1		T245	2		T322	3		T283	1
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T244	2		T246	3		T323	1
all_values[5]	auto[1]	auto[0]	auto[1]	49	1		T244	1		T246	1		T322	1
all_values[5]	auto[1]	auto[1]	auto[1]	50	1		T246	3		T322	3		T323	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal