Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287930	1		T2	7968		T3	1		T4	1
all_values[1]	287930	1		T2	7968		T3	1		T4	1
all_values[2]	287930	1		T2	7968		T3	1		T4	1
all_values[3]	287930	1		T2	7968		T3	1		T4	1
all_values[4]	287930	1		T2	7968		T3	1		T4	1
all_values[5]	287930	1		T2	7968		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7695	1		T3	6		T4	6		T5	6
auto[1]	1719885	1		T2	47808		T5	19044		T6	24150

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1398916	1		T2	38818		T3	6		T4	6
auto[1]	328664	1		T2	8990		T5	3236		T6	5030

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	946	1		T3	1		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	329	1		T7	1		T21	1		T24	1
all_values[0]	auto[1]	auto[0]	227905	1		T2	5706		T5	3174		T6	1
all_values[0]	auto[1]	auto[1]	58750	1		T2	2262		T6	4024		T116	2512
all_values[1]	auto[0]	auto[0]	1258	1		T3	1		T4	1		T5	1
all_values[1]	auto[0]	auto[1]	23	1		T208	1		T209	4		T210	1
all_values[1]	auto[1]	auto[0]	225728	1		T2	2263		T5	3174		T6	4025
all_values[1]	auto[1]	auto[1]	60921	1		T2	5705		T116	3200		T117	2464
all_values[2]	auto[0]	auto[0]	1205	1		T3	1		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	93	1		T21	1		T24	1		T45	1
all_values[2]	auto[1]	auto[0]	281554	1		T2	7968		T5	3174		T6	4025
all_values[2]	auto[1]	auto[1]	5078	1		T19	2		T208	1		T209	4
all_values[3]	auto[0]	auto[0]	1187	1		T3	1		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	97	1		T21	1		T24	1		T45	1
all_values[3]	auto[1]	auto[0]	168130	1		T2	7968		T5	1070		T6	4025
all_values[3]	auto[1]	auto[1]	118516	1		T5	2104		T8	858		T41	1580
all_values[4]	auto[0]	auto[0]	866	1		T3	1		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	411	1		T7	1		T21	1		T24	1
all_values[4]	auto[1]	auto[0]	202321	1		T2	6945		T5	2042		T6	3019
all_values[4]	auto[1]	auto[1]	84332	1		T2	1023		T5	1132		T6	1006
all_values[5]	auto[0]	auto[0]	1204	1		T3	1		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	76	1		T112	1		T295	3		T250	1
all_values[5]	auto[1]	auto[0]	286612	1		T2	7968		T5	3174		T6	4025
all_values[5]	auto[1]	auto[1]	38	1		T208	2		T210	5		T296	3