Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7309 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
2 |
| others[1] |
923 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
5 |
| others[2] |
929 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T40 |
1 |
| others[3] |
1581 |
1 |
|
T7 |
5 |
|
T41 |
1 |
|
T23 |
1 |
| false |
460 |
1 |
|
T7 |
3 |
|
T45 |
12 |
|
T46 |
2 |
| true |
1265 |
1 |
|
T5 |
1 |
|
T13 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T45 |
9 |
|
T58 |
12 |
|
T111 |
1 |
| others[1] |
207 |
1 |
|
T33 |
1 |
|
T45 |
11 |
|
T58 |
7 |
| others[2] |
203 |
1 |
|
T45 |
7 |
|
T58 |
5 |
|
T116 |
1 |
| others[3] |
329 |
1 |
|
T40 |
1 |
|
T45 |
14 |
|
T58 |
15 |
| false |
96 |
1 |
|
T45 |
6 |
|
T58 |
6 |
|
T112 |
1 |
| true |
11417 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
191 |
1 |
|
T45 |
9 |
|
T58 |
12 |
|
T117 |
1 |
| others[1] |
219 |
1 |
|
T45 |
13 |
|
T58 |
12 |
|
T52 |
1 |
| others[2] |
189 |
1 |
|
T45 |
12 |
|
T58 |
10 |
|
T285 |
1 |
| others[3] |
300 |
1 |
|
T45 |
12 |
|
T58 |
8 |
|
T34 |
1 |
| false |
97 |
1 |
|
T45 |
7 |
|
T58 |
2 |
|
T30 |
4 |
| true |
11471 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7485 |
1 |
|
T7 |
2 |
|
T8 |
1 |
|
T50 |
2 |
| others[1] |
1074 |
1 |
|
T7 |
3 |
|
T45 |
25 |
|
T58 |
15 |
| others[2] |
1155 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| others[3] |
1838 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
11 |
| false |
572 |
1 |
|
T7 |
3 |
|
T23 |
1 |
|
T45 |
11 |
| true |
343 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7510 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| others[1] |
1095 |
1 |
|
T7 |
2 |
|
T19 |
1 |
|
T45 |
26 |
| others[2] |
1100 |
1 |
|
T7 |
5 |
|
T41 |
1 |
|
T23 |
1 |
| others[3] |
1860 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
590 |
1 |
|
T7 |
2 |
|
T45 |
6 |
|
T46 |
1 |
| true |
312 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
81 |
1 |
|
T45 |
2 |
|
T58 |
4 |
|
T30 |
7 |
| others[1] |
78 |
1 |
|
T45 |
5 |
|
T58 |
3 |
|
T285 |
1 |
| others[2] |
104 |
1 |
|
T45 |
3 |
|
T58 |
5 |
|
T111 |
1 |
| others[3] |
161 |
1 |
|
T45 |
8 |
|
T58 |
4 |
|
T285 |
1 |
| false |
44 |
1 |
|
T45 |
2 |
|
T58 |
3 |
|
T142 |
2 |
| true |
11999 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
176 |
1 |
|
T45 |
8 |
|
T58 |
15 |
|
T111 |
1 |
| others[1] |
203 |
1 |
|
T45 |
10 |
|
T58 |
10 |
|
T30 |
10 |
| others[2] |
192 |
1 |
|
T45 |
15 |
|
T58 |
8 |
|
T30 |
11 |
| others[3] |
356 |
1 |
|
T4 |
1 |
|
T45 |
13 |
|
T58 |
13 |
| false |
128 |
1 |
|
T45 |
5 |
|
T58 |
8 |
|
T38 |
1 |
| true |
11412 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7319 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T7 |
5 |
| others[1] |
890 |
1 |
|
T7 |
5 |
|
T45 |
19 |
|
T25 |
1 |
| others[2] |
942 |
1 |
|
T7 |
5 |
|
T14 |
1 |
|
T45 |
24 |
| others[3] |
1514 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
485 |
1 |
|
T45 |
6 |
|
T46 |
2 |
|
T58 |
10 |
| true |
1317 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
180 |
1 |
|
T4 |
1 |
|
T45 |
6 |
|
T58 |
9 |
| others[1] |
217 |
1 |
|
T45 |
13 |
|
T139 |
1 |
|
T58 |
12 |
| others[2] |
220 |
1 |
|
T45 |
9 |
|
T58 |
15 |
|
T115 |
1 |
| others[3] |
325 |
1 |
|
T33 |
1 |
|
T45 |
16 |
|
T58 |
19 |
| false |
92 |
1 |
|
T5 |
1 |
|
T45 |
3 |
|
T58 |
4 |
| true |
11433 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
183 |
1 |
|
T45 |
5 |
|
T58 |
14 |
|
T30 |
11 |
| others[1] |
198 |
1 |
|
T45 |
6 |
|
T58 |
10 |
|
T30 |
9 |
| others[2] |
175 |
1 |
|
T40 |
1 |
|
T45 |
8 |
|
T58 |
10 |
| others[3] |
312 |
1 |
|
T45 |
12 |
|
T139 |
1 |
|
T58 |
15 |
| false |
101 |
1 |
|
T45 |
4 |
|
T58 |
5 |
|
T52 |
1 |
| true |
11498 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7494 |
1 |
|
T7 |
6 |
|
T50 |
2 |
|
T45 |
11 |
| others[1] |
1137 |
1 |
|
T7 |
8 |
|
T23 |
1 |
|
T45 |
30 |
| others[2] |
1048 |
1 |
|
T7 |
3 |
|
T8 |
1 |
|
T41 |
1 |
| others[3] |
1837 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T45 |
29 |
| false |
602 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| true |
349 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1102 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
6 |
| others[1] |
1128 |
1 |
|
T7 |
8 |
|
T23 |
1 |
|
T45 |
21 |
| others[2] |
1121 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T41 |
1 |
| others[3] |
1821 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T8 |
1 |
| false |
561 |
1 |
|
T7 |
1 |
|
T45 |
10 |
|
T46 |
1 |
| true |
324 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T45 |
8 |
|
T58 |
3 |
|
T30 |
8 |
| others[1] |
88 |
1 |
|
T45 |
6 |
|
T58 |
2 |
|
T285 |
1 |
| others[2] |
87 |
1 |
|
T45 |
2 |
|
T58 |
6 |
|
T111 |
1 |
| others[3] |
151 |
1 |
|
T45 |
3 |
|
T58 |
6 |
|
T30 |
6 |
| false |
48 |
1 |
|
T45 |
2 |
|
T58 |
2 |
|
T285 |
1 |
| true |
5585 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
185 |
1 |
|
T45 |
4 |
|
T58 |
8 |
|
T34 |
1 |
| others[1] |
180 |
1 |
|
T45 |
11 |
|
T58 |
13 |
|
T115 |
1 |
| others[2] |
200 |
1 |
|
T33 |
1 |
|
T45 |
6 |
|
T58 |
9 |
| others[3] |
357 |
1 |
|
T45 |
6 |
|
T58 |
16 |
|
T30 |
13 |
| false |
101 |
1 |
|
T45 |
5 |
|
T58 |
9 |
|
T30 |
5 |
| true |
5034 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
915 |
1 |
|
T2 |
1 |
|
T7 |
7 |
|
T14 |
1 |
| others[1] |
902 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T13 |
1 |
| others[2] |
887 |
1 |
|
T7 |
3 |
|
T45 |
18 |
|
T25 |
1 |
| others[3] |
1564 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
6 |
| false |
486 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T14 |
1 |
| true |
1303 |
1 |
|
T42 |
1 |
|
T40 |
1 |
|
T96 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T45 |
13 |
|
T58 |
12 |
|
T111 |
1 |
| others[1] |
186 |
1 |
|
T45 |
14 |
|
T58 |
10 |
|
T116 |
1 |
| others[2] |
173 |
1 |
|
T45 |
5 |
|
T58 |
8 |
|
T30 |
12 |
| others[3] |
335 |
1 |
|
T45 |
22 |
|
T58 |
18 |
|
T115 |
1 |
| false |
100 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T30 |
7 |
| true |
5058 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T45 |
5 |
|
T58 |
11 |
|
T38 |
1 |
| others[1] |
163 |
1 |
|
T45 |
8 |
|
T58 |
7 |
|
T111 |
1 |
| others[2] |
211 |
1 |
|
T45 |
12 |
|
T58 |
12 |
|
T30 |
10 |
| others[3] |
317 |
1 |
|
T45 |
21 |
|
T139 |
1 |
|
T58 |
13 |
| false |
104 |
1 |
|
T45 |
7 |
|
T58 |
1 |
|
T30 |
5 |
| true |
5066 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1118 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T45 |
21 |
| others[1] |
1067 |
1 |
|
T1 |
1 |
|
T7 |
8 |
|
T8 |
1 |
| others[2] |
1120 |
1 |
|
T7 |
2 |
|
T45 |
21 |
|
T25 |
1 |
| others[3] |
1857 |
1 |
|
T7 |
4 |
|
T42 |
1 |
|
T19 |
1 |
| false |
557 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| true |
338 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1134 |
1 |
|
T7 |
7 |
|
T23 |
1 |
|
T45 |
25 |
| others[1] |
1077 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[2] |
1096 |
1 |
|
T7 |
3 |
|
T8 |
1 |
|
T45 |
13 |
| others[3] |
1847 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T19 |
1 |
| false |
579 |
1 |
|
T7 |
5 |
|
T41 |
1 |
|
T45 |
9 |
| true |
324 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
82 |
1 |
|
T45 |
1 |
|
T58 |
4 |
|
T285 |
1 |
| others[1] |
91 |
1 |
|
T45 |
4 |
|
T139 |
1 |
|
T58 |
4 |
| others[2] |
89 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T30 |
6 |
| others[3] |
151 |
1 |
|
T45 |
2 |
|
T58 |
10 |
|
T111 |
1 |
| false |
63 |
1 |
|
T45 |
6 |
|
T58 |
1 |
|
T30 |
4 |
| true |
5581 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
173 |
1 |
|
T40 |
1 |
|
T45 |
9 |
|
T58 |
7 |
| others[1] |
220 |
1 |
|
T45 |
13 |
|
T58 |
20 |
|
T112 |
1 |
| others[2] |
192 |
1 |
|
T45 |
8 |
|
T58 |
10 |
|
T30 |
8 |
| others[3] |
327 |
1 |
|
T33 |
1 |
|
T45 |
22 |
|
T139 |
1 |
| false |
115 |
1 |
|
T45 |
6 |
|
T58 |
3 |
|
T111 |
1 |
| true |
5030 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
971 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T13 |
1 |
| others[1] |
892 |
1 |
|
T7 |
2 |
|
T40 |
1 |
|
T14 |
1 |
| others[2] |
900 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T43 |
1 |
| others[3] |
1577 |
1 |
|
T7 |
6 |
|
T14 |
1 |
|
T41 |
1 |
| false |
448 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T45 |
14 |
| true |
1269 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T5 |
1 |
|
T40 |
1 |
|
T45 |
6 |
| others[1] |
205 |
1 |
|
T45 |
12 |
|
T58 |
10 |
|
T111 |
1 |
| others[2] |
173 |
1 |
|
T45 |
6 |
|
T58 |
12 |
|
T115 |
1 |
| others[3] |
309 |
1 |
|
T4 |
1 |
|
T45 |
15 |
|
T139 |
1 |
| false |
85 |
1 |
|
T45 |
6 |
|
T58 |
5 |
|
T257 |
1 |
| true |
5066 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T45 |
6 |
|
T58 |
14 |
|
T30 |
11 |
| others[1] |
188 |
1 |
|
T45 |
7 |
|
T58 |
9 |
|
T34 |
1 |
| others[2] |
196 |
1 |
|
T45 |
9 |
|
T58 |
8 |
|
T285 |
1 |
| others[3] |
296 |
1 |
|
T45 |
16 |
|
T58 |
15 |
|
T115 |
1 |
| false |
102 |
1 |
|
T45 |
5 |
|
T58 |
1 |
|
T30 |
8 |
| true |
5085 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1109 |
1 |
|
T1 |
1 |
|
T7 |
4 |
|
T41 |
1 |
| others[1] |
1043 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
4 |
| others[2] |
1119 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T45 |
13 |
| others[3] |
1836 |
1 |
|
T7 |
6 |
|
T19 |
1 |
|
T23 |
1 |
| false |
610 |
1 |
|
T7 |
2 |
|
T45 |
12 |
|
T46 |
2 |
| true |
340 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1133 |
1 |
|
T7 |
6 |
|
T45 |
22 |
|
T46 |
3 |
| others[1] |
1142 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T45 |
19 |
| others[2] |
1104 |
1 |
|
T1 |
1 |
|
T7 |
6 |
|
T41 |
1 |
| others[3] |
1809 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T8 |
1 |
| false |
551 |
1 |
|
T7 |
3 |
|
T45 |
9 |
|
T46 |
2 |
| true |
318 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
64 |
1 |
|
T45 |
1 |
|
T58 |
3 |
|
T285 |
1 |
| others[1] |
75 |
1 |
|
T45 |
2 |
|
T58 |
1 |
|
T30 |
1 |
| others[2] |
87 |
1 |
|
T45 |
6 |
|
T58 |
2 |
|
T111 |
1 |
| others[3] |
154 |
1 |
|
T45 |
8 |
|
T58 |
8 |
|
T285 |
1 |
| false |
48 |
1 |
|
T45 |
1 |
|
T58 |
2 |
|
T38 |
1 |
| true |
5629 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T45 |
17 |
|
T58 |
10 |
|
T30 |
14 |
| others[1] |
211 |
1 |
|
T4 |
1 |
|
T45 |
13 |
|
T58 |
12 |
| others[2] |
197 |
1 |
|
T5 |
1 |
|
T45 |
12 |
|
T58 |
11 |
| others[3] |
299 |
1 |
|
T45 |
11 |
|
T139 |
1 |
|
T58 |
14 |
| false |
104 |
1 |
|
T45 |
5 |
|
T58 |
4 |
|
T30 |
3 |
| true |
5020 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
930 |
1 |
|
T7 |
3 |
|
T33 |
1 |
|
T41 |
1 |
| others[1] |
931 |
1 |
|
T7 |
6 |
|
T45 |
12 |
|
T58 |
31 |
| others[2] |
898 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
5 |
| others[3] |
1512 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
497 |
1 |
|
T7 |
1 |
|
T19 |
1 |
|
T45 |
16 |
| true |
1289 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T40 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
173 |
1 |
|
T5 |
1 |
|
T45 |
8 |
|
T58 |
8 |
| others[1] |
192 |
1 |
|
T45 |
13 |
|
T58 |
7 |
|
T34 |
1 |
| others[2] |
205 |
1 |
|
T45 |
10 |
|
T58 |
17 |
|
T111 |
1 |
| others[3] |
348 |
1 |
|
T40 |
1 |
|
T45 |
10 |
|
T58 |
17 |
| false |
90 |
1 |
|
T45 |
3 |
|
T58 |
5 |
|
T30 |
7 |
| true |
5049 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
188 |
1 |
|
T45 |
10 |
|
T58 |
7 |
|
T117 |
1 |
| others[1] |
193 |
1 |
|
T40 |
1 |
|
T45 |
11 |
|
T58 |
4 |
| others[2] |
167 |
1 |
|
T45 |
3 |
|
T58 |
13 |
|
T52 |
1 |
| others[3] |
314 |
1 |
|
T45 |
12 |
|
T58 |
16 |
|
T111 |
1 |
| false |
99 |
1 |
|
T45 |
5 |
|
T58 |
7 |
|
T285 |
1 |
| true |
5096 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |