Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1076 |
1 |
|
T7 |
3 |
|
T45 |
18 |
|
T139 |
1 |
| others[1] |
1114 |
1 |
|
T7 |
3 |
|
T19 |
1 |
|
T45 |
14 |
| others[2] |
1125 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
6 |
| others[3] |
1883 |
1 |
|
T6 |
1 |
|
T7 |
8 |
|
T45 |
27 |
| false |
527 |
1 |
|
T7 |
1 |
|
T45 |
12 |
|
T46 |
1 |
| true |
332 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1177 |
1 |
|
T7 |
3 |
|
T45 |
16 |
|
T25 |
1 |
| others[1] |
1070 |
1 |
|
T7 |
4 |
|
T14 |
1 |
|
T23 |
1 |
| others[2] |
1117 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T41 |
1 |
| others[3] |
1804 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
5 |
| false |
572 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T45 |
9 |
| true |
317 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T45 |
3 |
|
T58 |
2 |
|
T30 |
3 |
| others[1] |
90 |
1 |
|
T45 |
5 |
|
T58 |
6 |
|
T257 |
1 |
| others[2] |
80 |
1 |
|
T45 |
3 |
|
T58 |
1 |
|
T285 |
1 |
| others[3] |
129 |
1 |
|
T45 |
7 |
|
T58 |
5 |
|
T111 |
1 |
| false |
47 |
1 |
|
T45 |
3 |
|
T58 |
2 |
|
T52 |
1 |
| true |
5616 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T45 |
9 |
|
T58 |
5 |
|
T116 |
1 |
| others[1] |
196 |
1 |
|
T40 |
1 |
|
T45 |
10 |
|
T58 |
13 |
| others[2] |
199 |
1 |
|
T45 |
10 |
|
T58 |
9 |
|
T117 |
1 |
| others[3] |
344 |
1 |
|
T4 |
1 |
|
T33 |
1 |
|
T45 |
12 |
| false |
103 |
1 |
|
T45 |
7 |
|
T58 |
4 |
|
T285 |
1 |
| true |
5019 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
881 |
1 |
|
T7 |
2 |
|
T8 |
1 |
|
T45 |
17 |
| others[1] |
939 |
1 |
|
T1 |
1 |
|
T13 |
1 |
|
T7 |
6 |
| others[2] |
916 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
8 |
| others[3] |
1542 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T45 |
34 |
| false |
516 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T45 |
15 |
| true |
1263 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
186 |
1 |
|
T45 |
13 |
|
T58 |
3 |
|
T30 |
12 |
| others[1] |
179 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T45 |
10 |
| others[2] |
198 |
1 |
|
T45 |
9 |
|
T58 |
9 |
|
T30 |
8 |
| others[3] |
321 |
1 |
|
T45 |
13 |
|
T58 |
17 |
|
T38 |
1 |
| false |
117 |
1 |
|
T45 |
2 |
|
T58 |
5 |
|
T285 |
2 |
| true |
5056 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T45 |
10 |
|
T58 |
11 |
|
T38 |
1 |
| others[1] |
197 |
1 |
|
T45 |
13 |
|
T139 |
1 |
|
T58 |
9 |
| others[2] |
171 |
1 |
|
T45 |
14 |
|
T58 |
8 |
|
T111 |
1 |
| others[3] |
310 |
1 |
|
T45 |
11 |
|
T58 |
15 |
|
T30 |
17 |
| false |
108 |
1 |
|
T45 |
7 |
|
T58 |
5 |
|
T285 |
1 |
| true |
5066 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1120 |
1 |
|
T7 |
6 |
|
T8 |
1 |
|
T19 |
1 |
| others[1] |
1119 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T45 |
21 |
| others[2] |
1078 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
3 |
| others[3] |
1832 |
1 |
|
T7 |
4 |
|
T23 |
1 |
|
T45 |
35 |
| false |
569 |
1 |
|
T7 |
3 |
|
T45 |
11 |
|
T46 |
1 |
| true |
339 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1116 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
7 |
| others[1] |
1119 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T45 |
17 |
| others[2] |
1138 |
1 |
|
T7 |
2 |
|
T41 |
1 |
|
T19 |
1 |
| others[3] |
1830 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T45 |
32 |
| false |
539 |
1 |
|
T7 |
2 |
|
T45 |
8 |
|
T46 |
3 |
| true |
315 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T45 |
8 |
|
T58 |
4 |
|
T285 |
1 |
| others[1] |
76 |
1 |
|
T45 |
5 |
|
T58 |
1 |
|
T30 |
6 |
| others[2] |
91 |
1 |
|
T45 |
2 |
|
T58 |
5 |
|
T285 |
1 |
| others[3] |
146 |
1 |
|
T45 |
7 |
|
T58 |
4 |
|
T111 |
1 |
| false |
64 |
1 |
|
T45 |
4 |
|
T139 |
1 |
|
T58 |
7 |
| true |
5593 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
180 |
1 |
|
T45 |
11 |
|
T58 |
9 |
|
T112 |
1 |
| others[1] |
197 |
1 |
|
T40 |
1 |
|
T45 |
7 |
|
T58 |
10 |
| others[2] |
188 |
1 |
|
T45 |
9 |
|
T58 |
10 |
|
T30 |
9 |
| others[3] |
329 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T33 |
1 |
| false |
106 |
1 |
|
T45 |
8 |
|
T58 |
6 |
|
T52 |
1 |
| true |
5057 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
897 |
1 |
|
T7 |
3 |
|
T23 |
1 |
|
T45 |
12 |
| others[1] |
904 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T45 |
21 |
| others[2] |
938 |
1 |
|
T2 |
1 |
|
T7 |
7 |
|
T8 |
1 |
| others[3] |
1585 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T13 |
1 |
| false |
446 |
1 |
|
T7 |
1 |
|
T40 |
1 |
|
T45 |
13 |
| true |
1287 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T33 |
1 |
|
T45 |
6 |
|
T58 |
12 |
| others[1] |
178 |
1 |
|
T45 |
9 |
|
T58 |
9 |
|
T30 |
8 |
| others[2] |
205 |
1 |
|
T45 |
7 |
|
T58 |
12 |
|
T257 |
1 |
| others[3] |
339 |
1 |
|
T45 |
15 |
|
T139 |
1 |
|
T58 |
15 |
| false |
93 |
1 |
|
T45 |
6 |
|
T58 |
3 |
|
T115 |
1 |
| true |
5041 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T45 |
6 |
|
T58 |
9 |
|
T112 |
1 |
| others[1] |
200 |
1 |
|
T45 |
9 |
|
T58 |
12 |
|
T30 |
8 |
| others[2] |
196 |
1 |
|
T45 |
10 |
|
T139 |
1 |
|
T58 |
9 |
| others[3] |
297 |
1 |
|
T40 |
1 |
|
T45 |
12 |
|
T58 |
11 |
| false |
105 |
1 |
|
T45 |
5 |
|
T58 |
8 |
|
T285 |
1 |
| true |
5053 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1118 |
1 |
|
T7 |
6 |
|
T41 |
1 |
|
T45 |
18 |
| others[1] |
1089 |
1 |
|
T7 |
6 |
|
T45 |
19 |
|
T46 |
3 |
| others[2] |
1087 |
1 |
|
T7 |
3 |
|
T8 |
1 |
|
T19 |
1 |
| others[3] |
1856 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
| false |
570 |
1 |
|
T7 |
1 |
|
T45 |
11 |
|
T25 |
1 |
| true |
337 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1168 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T19 |
1 |
| others[1] |
1099 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| others[2] |
1117 |
1 |
|
T7 |
5 |
|
T45 |
17 |
|
T46 |
4 |
| others[3] |
1785 |
1 |
|
T3 |
1 |
|
T7 |
5 |
|
T23 |
1 |
| false |
573 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T45 |
15 |
| true |
315 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T45 |
5 |
|
T58 |
3 |
|
T285 |
1 |
| others[1] |
97 |
1 |
|
T45 |
8 |
|
T58 |
5 |
|
T285 |
1 |
| others[2] |
97 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T30 |
4 |
| others[3] |
144 |
1 |
|
T45 |
7 |
|
T58 |
10 |
|
T111 |
1 |
| false |
48 |
1 |
|
T45 |
2 |
|
T58 |
1 |
|
T115 |
1 |
| true |
5585 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T45 |
14 |
|
T58 |
15 |
|
T111 |
1 |
| others[1] |
198 |
1 |
|
T45 |
15 |
|
T58 |
5 |
|
T112 |
1 |
| others[2] |
199 |
1 |
|
T45 |
11 |
|
T58 |
6 |
|
T52 |
1 |
| others[3] |
333 |
1 |
|
T33 |
1 |
|
T40 |
1 |
|
T45 |
11 |
| false |
100 |
1 |
|
T45 |
2 |
|
T58 |
8 |
|
T257 |
1 |
| true |
5012 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
955 |
1 |
|
T4 |
1 |
|
T7 |
5 |
|
T41 |
1 |
| others[1] |
931 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T45 |
25 |
| others[2] |
888 |
1 |
|
T13 |
1 |
|
T7 |
4 |
|
T14 |
2 |
| others[3] |
1553 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
6 |
| false |
484 |
1 |
|
T7 |
3 |
|
T8 |
1 |
|
T45 |
8 |
| true |
1246 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
163 |
1 |
|
T45 |
9 |
|
T58 |
8 |
|
T315 |
1 |
| others[1] |
177 |
1 |
|
T45 |
7 |
|
T58 |
10 |
|
T116 |
1 |
| others[2] |
194 |
1 |
|
T40 |
1 |
|
T45 |
7 |
|
T58 |
10 |
| others[3] |
323 |
1 |
|
T45 |
18 |
|
T58 |
17 |
|
T285 |
1 |
| false |
102 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T30 |
4 |
| true |
5098 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T45 |
10 |
|
T58 |
8 |
|
T111 |
1 |
| others[1] |
198 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T30 |
11 |
| others[2] |
165 |
1 |
|
T45 |
10 |
|
T58 |
8 |
|
T52 |
1 |
| others[3] |
331 |
1 |
|
T45 |
25 |
|
T58 |
22 |
|
T285 |
1 |
| false |
106 |
1 |
|
T45 |
7 |
|
T58 |
6 |
|
T30 |
12 |
| true |
5061 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T7 |
1 |
|
T45 |
20 |
|
T25 |
1 |
| others[1] |
1138 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
4 |
| others[2] |
1066 |
1 |
|
T7 |
6 |
|
T45 |
19 |
|
T46 |
1 |
| others[3] |
1863 |
1 |
|
T7 |
6 |
|
T41 |
1 |
|
T23 |
1 |
| false |
587 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| true |
343 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1075 |
1 |
|
T3 |
1 |
|
T7 |
4 |
|
T45 |
17 |
| others[1] |
1113 |
1 |
|
T7 |
2 |
|
T45 |
18 |
|
T46 |
1 |
| others[2] |
1126 |
1 |
|
T7 |
7 |
|
T41 |
1 |
|
T45 |
24 |
| others[3] |
1849 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
| false |
576 |
1 |
|
T7 |
1 |
|
T45 |
13 |
|
T46 |
3 |
| true |
318 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T45 |
7 |
|
T58 |
4 |
|
T30 |
3 |
| others[1] |
87 |
1 |
|
T45 |
2 |
|
T58 |
1 |
|
T111 |
1 |
| others[2] |
89 |
1 |
|
T40 |
1 |
|
T45 |
7 |
|
T58 |
5 |
| others[3] |
151 |
1 |
|
T45 |
5 |
|
T58 |
6 |
|
T285 |
1 |
| false |
44 |
1 |
|
T45 |
2 |
|
T58 |
1 |
|
T142 |
3 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T45 |
10 |
|
T58 |
13 |
|
T30 |
12 |
| others[1] |
181 |
1 |
|
T33 |
1 |
|
T45 |
10 |
|
T58 |
9 |
| others[2] |
183 |
1 |
|
T45 |
11 |
|
T58 |
12 |
|
T257 |
1 |
| others[3] |
280 |
1 |
|
T45 |
16 |
|
T58 |
17 |
|
T115 |
1 |
| false |
103 |
1 |
|
T45 |
3 |
|
T139 |
1 |
|
T285 |
1 |
| true |
5108 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
945 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T33 |
1 |
| others[1] |
939 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
7 |
| others[2] |
907 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T7 |
4 |
| others[3] |
1552 |
1 |
|
T7 |
5 |
|
T40 |
1 |
|
T41 |
1 |
| false |
476 |
1 |
|
T45 |
10 |
|
T58 |
12 |
|
T250 |
1 |
| true |
1238 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
187 |
1 |
|
T5 |
1 |
|
T45 |
8 |
|
T58 |
9 |
| others[1] |
178 |
1 |
|
T45 |
9 |
|
T58 |
14 |
|
T285 |
1 |
| others[2] |
184 |
1 |
|
T4 |
1 |
|
T45 |
10 |
|
T58 |
8 |
| others[3] |
326 |
1 |
|
T45 |
10 |
|
T139 |
1 |
|
T58 |
13 |
| false |
96 |
1 |
|
T45 |
6 |
|
T58 |
3 |
|
T111 |
1 |
| true |
5086 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
159 |
1 |
|
T45 |
10 |
|
T58 |
15 |
|
T285 |
1 |
| others[1] |
213 |
1 |
|
T45 |
4 |
|
T58 |
7 |
|
T30 |
6 |
| others[2] |
198 |
1 |
|
T45 |
12 |
|
T58 |
11 |
|
T115 |
1 |
| others[3] |
341 |
1 |
|
T45 |
13 |
|
T58 |
19 |
|
T34 |
1 |
| false |
85 |
1 |
|
T45 |
8 |
|
T58 |
6 |
|
T38 |
1 |
| true |
5061 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T7 |
5 |
|
T45 |
18 |
|
T58 |
18 |
| others[1] |
1078 |
1 |
|
T7 |
7 |
|
T19 |
1 |
|
T45 |
17 |
| others[2] |
1139 |
1 |
|
T7 |
1 |
|
T45 |
22 |
|
T46 |
3 |
| others[3] |
1837 |
1 |
|
T6 |
1 |
|
T7 |
7 |
|
T8 |
1 |
| false |
621 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| true |
339 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1098 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T14 |
1 |
| others[1] |
1117 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T8 |
1 |
| others[2] |
1142 |
1 |
|
T7 |
4 |
|
T45 |
17 |
|
T46 |
3 |
| others[3] |
1834 |
1 |
|
T1 |
1 |
|
T7 |
6 |
|
T19 |
1 |
| false |
544 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T45 |
7 |
| true |
322 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T45 |
4 |
|
T58 |
2 |
|
T285 |
1 |
| others[1] |
89 |
1 |
|
T45 |
5 |
|
T58 |
6 |
|
T115 |
1 |
| others[2] |
95 |
1 |
|
T45 |
3 |
|
T58 |
6 |
|
T111 |
1 |
| others[3] |
149 |
1 |
|
T45 |
3 |
|
T58 |
11 |
|
T285 |
1 |
| false |
38 |
1 |
|
T45 |
6 |
|
T58 |
2 |
|
T30 |
2 |
| true |
5592 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |