Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T45 |
12 |
|
T58 |
12 |
|
T111 |
1 |
| others[1] |
194 |
1 |
|
T45 |
10 |
|
T58 |
11 |
|
T285 |
1 |
| others[2] |
188 |
1 |
|
T5 |
1 |
|
T45 |
7 |
|
T58 |
7 |
| others[3] |
354 |
1 |
|
T45 |
12 |
|
T58 |
19 |
|
T116 |
1 |
| false |
86 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T30 |
4 |
| true |
5024 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
932 |
1 |
|
T7 |
4 |
|
T23 |
1 |
|
T45 |
18 |
| others[1] |
882 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
| others[2] |
908 |
1 |
|
T7 |
4 |
|
T45 |
19 |
|
T46 |
3 |
| others[3] |
1567 |
1 |
|
T7 |
10 |
|
T43 |
1 |
|
T40 |
1 |
| false |
487 |
1 |
|
T7 |
1 |
|
T33 |
1 |
|
T45 |
12 |
| true |
1281 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T45 |
7 |
|
T58 |
12 |
|
T285 |
1 |
| others[1] |
206 |
1 |
|
T45 |
8 |
|
T58 |
10 |
|
T30 |
8 |
| others[2] |
179 |
1 |
|
T40 |
1 |
|
T45 |
13 |
|
T58 |
8 |
| others[3] |
301 |
1 |
|
T45 |
16 |
|
T58 |
14 |
|
T30 |
14 |
| false |
94 |
1 |
|
T45 |
6 |
|
T139 |
1 |
|
T58 |
4 |
| true |
5075 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
172 |
1 |
|
T45 |
7 |
|
T58 |
5 |
|
T285 |
1 |
| others[1] |
183 |
1 |
|
T40 |
1 |
|
T45 |
10 |
|
T58 |
8 |
| others[2] |
187 |
1 |
|
T45 |
4 |
|
T58 |
13 |
|
T34 |
1 |
| others[3] |
308 |
1 |
|
T45 |
16 |
|
T58 |
19 |
|
T115 |
1 |
| false |
99 |
1 |
|
T45 |
7 |
|
T58 |
3 |
|
T30 |
5 |
| true |
5108 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1130 |
1 |
|
T1 |
1 |
|
T7 |
6 |
|
T45 |
12 |
| others[1] |
1084 |
1 |
|
T7 |
4 |
|
T45 |
23 |
|
T25 |
1 |
| others[2] |
1102 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| others[3] |
1819 |
1 |
|
T2 |
1 |
|
T7 |
5 |
|
T8 |
1 |
| false |
569 |
1 |
|
T7 |
4 |
|
T45 |
11 |
|
T46 |
1 |
| true |
353 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1124 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T45 |
24 |
| others[1] |
1126 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T41 |
1 |
| others[2] |
1092 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T45 |
17 |
| others[3] |
1795 |
1 |
|
T2 |
1 |
|
T7 |
7 |
|
T45 |
30 |
| false |
605 |
1 |
|
T7 |
3 |
|
T19 |
1 |
|
T45 |
4 |
| true |
315 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
81 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T30 |
5 |
| others[1] |
90 |
1 |
|
T45 |
3 |
|
T58 |
7 |
|
T30 |
6 |
| others[2] |
95 |
1 |
|
T45 |
2 |
|
T58 |
2 |
|
T112 |
1 |
| others[3] |
151 |
1 |
|
T45 |
5 |
|
T58 |
4 |
|
T111 |
1 |
| false |
67 |
1 |
|
T45 |
3 |
|
T58 |
1 |
|
T285 |
2 |
| true |
5573 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T5 |
1 |
|
T45 |
12 |
|
T139 |
1 |
| others[1] |
191 |
1 |
|
T45 |
7 |
|
T58 |
8 |
|
T34 |
1 |
| others[2] |
198 |
1 |
|
T45 |
10 |
|
T58 |
10 |
|
T285 |
2 |
| others[3] |
306 |
1 |
|
T4 |
1 |
|
T45 |
14 |
|
T58 |
13 |
| false |
111 |
1 |
|
T45 |
7 |
|
T58 |
5 |
|
T30 |
7 |
| true |
5040 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
938 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
7 |
| others[1] |
913 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
3 |
| others[2] |
964 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
| others[3] |
1485 |
1 |
|
T7 |
4 |
|
T43 |
1 |
|
T14 |
1 |
| false |
479 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T45 |
10 |
| true |
1278 |
1 |
|
T42 |
1 |
|
T33 |
1 |
|
T97 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
188 |
1 |
|
T45 |
11 |
|
T58 |
5 |
|
T117 |
1 |
| others[1] |
180 |
1 |
|
T5 |
1 |
|
T45 |
4 |
|
T58 |
8 |
| others[2] |
185 |
1 |
|
T45 |
8 |
|
T58 |
9 |
|
T285 |
1 |
| others[3] |
352 |
1 |
|
T33 |
1 |
|
T45 |
16 |
|
T58 |
16 |
| false |
109 |
1 |
|
T45 |
6 |
|
T58 |
3 |
|
T115 |
1 |
| true |
5043 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
162 |
1 |
|
T45 |
8 |
|
T58 |
8 |
|
T30 |
5 |
| others[1] |
172 |
1 |
|
T45 |
12 |
|
T139 |
1 |
|
T58 |
9 |
| others[2] |
198 |
1 |
|
T45 |
11 |
|
T58 |
12 |
|
T112 |
1 |
| others[3] |
334 |
1 |
|
T45 |
18 |
|
T58 |
12 |
|
T115 |
1 |
| false |
93 |
1 |
|
T45 |
2 |
|
T58 |
4 |
|
T315 |
1 |
| true |
5098 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1128 |
1 |
|
T7 |
5 |
|
T23 |
1 |
|
T45 |
17 |
| others[1] |
1098 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| others[2] |
1082 |
1 |
|
T7 |
3 |
|
T45 |
19 |
|
T25 |
1 |
| others[3] |
1859 |
1 |
|
T6 |
1 |
|
T7 |
6 |
|
T42 |
1 |
| false |
545 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T45 |
8 |
| true |
345 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1140 |
1 |
|
T7 |
4 |
|
T45 |
27 |
|
T46 |
2 |
| others[1] |
1113 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
4 |
| others[2] |
1097 |
1 |
|
T7 |
5 |
|
T19 |
1 |
|
T45 |
20 |
| others[3] |
1775 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T23 |
1 |
| false |
615 |
1 |
|
T7 |
4 |
|
T42 |
1 |
|
T8 |
1 |
| true |
317 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
80 |
1 |
|
T45 |
1 |
|
T58 |
3 |
|
T116 |
1 |
| others[1] |
83 |
1 |
|
T45 |
7 |
|
T58 |
4 |
|
T30 |
2 |
| others[2] |
86 |
1 |
|
T45 |
7 |
|
T139 |
1 |
|
T58 |
3 |
| others[3] |
131 |
1 |
|
T45 |
4 |
|
T58 |
4 |
|
T112 |
1 |
| false |
47 |
1 |
|
T45 |
2 |
|
T58 |
2 |
|
T111 |
1 |
| true |
5630 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T5 |
1 |
|
T45 |
6 |
|
T58 |
10 |
| others[1] |
191 |
1 |
|
T45 |
11 |
|
T58 |
4 |
|
T30 |
10 |
| others[2] |
208 |
1 |
|
T45 |
10 |
|
T58 |
11 |
|
T52 |
1 |
| others[3] |
334 |
1 |
|
T45 |
22 |
|
T58 |
16 |
|
T285 |
1 |
| false |
115 |
1 |
|
T45 |
8 |
|
T58 |
3 |
|
T257 |
1 |
| true |
5008 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
938 |
1 |
|
T4 |
1 |
|
T7 |
5 |
|
T42 |
1 |
| others[1] |
860 |
1 |
|
T1 |
1 |
|
T7 |
4 |
|
T45 |
21 |
| others[2] |
939 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
5 |
| others[3] |
1528 |
1 |
|
T7 |
5 |
|
T41 |
1 |
|
T45 |
25 |
| false |
470 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T19 |
1 |
| true |
1322 |
1 |
|
T3 |
1 |
|
T13 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T45 |
9 |
|
T58 |
8 |
|
T111 |
1 |
| others[1] |
201 |
1 |
|
T5 |
1 |
|
T45 |
9 |
|
T58 |
15 |
| others[2] |
172 |
1 |
|
T45 |
10 |
|
T58 |
12 |
|
T30 |
11 |
| others[3] |
337 |
1 |
|
T4 |
1 |
|
T33 |
1 |
|
T45 |
12 |
| false |
114 |
1 |
|
T40 |
1 |
|
T45 |
11 |
|
T58 |
5 |
| true |
5028 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T111 |
1 |
| others[1] |
196 |
1 |
|
T45 |
13 |
|
T58 |
5 |
|
T116 |
1 |
| others[2] |
203 |
1 |
|
T45 |
7 |
|
T58 |
10 |
|
T30 |
8 |
| others[3] |
299 |
1 |
|
T40 |
1 |
|
T45 |
17 |
|
T58 |
10 |
| false |
102 |
1 |
|
T45 |
4 |
|
T139 |
1 |
|
T58 |
8 |
| true |
5053 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1064 |
1 |
|
T7 |
3 |
|
T45 |
12 |
|
T46 |
1 |
| others[1] |
1132 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T8 |
1 |
| others[2] |
1119 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
2 |
| others[3] |
1867 |
1 |
|
T7 |
11 |
|
T45 |
36 |
|
T46 |
1 |
| false |
537 |
1 |
|
T23 |
1 |
|
T45 |
11 |
|
T46 |
2 |
| true |
338 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1164 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T45 |
20 |
| others[1] |
1123 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T41 |
1 |
| others[2] |
1080 |
1 |
|
T6 |
1 |
|
T7 |
7 |
|
T19 |
1 |
| others[3] |
1833 |
1 |
|
T7 |
6 |
|
T8 |
1 |
|
T23 |
1 |
| false |
547 |
1 |
|
T7 |
1 |
|
T45 |
11 |
|
T46 |
1 |
| true |
310 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
78 |
1 |
|
T45 |
7 |
|
T58 |
2 |
|
T38 |
1 |
| others[1] |
79 |
1 |
|
T45 |
1 |
|
T58 |
5 |
|
T115 |
1 |
| others[2] |
78 |
1 |
|
T45 |
4 |
|
T30 |
6 |
|
T146 |
1 |
| others[3] |
161 |
1 |
|
T45 |
10 |
|
T58 |
4 |
|
T285 |
1 |
| false |
53 |
1 |
|
T40 |
1 |
|
T45 |
2 |
|
T58 |
4 |
| true |
5608 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T5 |
1 |
|
T45 |
12 |
|
T58 |
4 |
| others[1] |
190 |
1 |
|
T45 |
4 |
|
T58 |
9 |
|
T52 |
1 |
| others[2] |
183 |
1 |
|
T4 |
1 |
|
T45 |
4 |
|
T139 |
1 |
| others[3] |
328 |
1 |
|
T45 |
13 |
|
T58 |
24 |
|
T285 |
1 |
| false |
111 |
1 |
|
T45 |
3 |
|
T58 |
4 |
|
T315 |
1 |
| true |
5051 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
900 |
1 |
|
T5 |
1 |
|
T7 |
3 |
|
T8 |
1 |
| others[1] |
898 |
1 |
|
T7 |
3 |
|
T33 |
1 |
|
T23 |
1 |
| others[2] |
882 |
1 |
|
T7 |
5 |
|
T19 |
1 |
|
T45 |
13 |
| others[3] |
1612 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
499 |
1 |
|
T7 |
3 |
|
T45 |
16 |
|
T58 |
14 |
| true |
1266 |
1 |
|
T4 |
1 |
|
T13 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T4 |
1 |
|
T45 |
9 |
|
T58 |
10 |
| others[1] |
186 |
1 |
|
T45 |
9 |
|
T58 |
3 |
|
T111 |
1 |
| others[2] |
178 |
1 |
|
T45 |
13 |
|
T58 |
7 |
|
T30 |
7 |
| others[3] |
331 |
1 |
|
T45 |
15 |
|
T139 |
1 |
|
T58 |
20 |
| false |
97 |
1 |
|
T45 |
2 |
|
T58 |
4 |
|
T30 |
13 |
| true |
5055 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T45 |
12 |
|
T58 |
9 |
|
T115 |
1 |
| others[1] |
193 |
1 |
|
T40 |
1 |
|
T45 |
10 |
|
T58 |
11 |
| others[2] |
191 |
1 |
|
T45 |
8 |
|
T58 |
9 |
|
T30 |
7 |
| others[3] |
301 |
1 |
|
T45 |
15 |
|
T58 |
24 |
|
T111 |
1 |
| false |
88 |
1 |
|
T45 |
1 |
|
T58 |
3 |
|
T30 |
8 |
| true |
5075 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T14 |
2 |
| others[1] |
1100 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T8 |
1 |
| others[2] |
1069 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T41 |
1 |
| others[3] |
1854 |
1 |
|
T7 |
6 |
|
T45 |
30 |
|
T58 |
21 |
| false |
590 |
1 |
|
T7 |
1 |
|
T45 |
9 |
|
T46 |
2 |
| true |
349 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1121 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T45 |
20 |
| others[1] |
1088 |
1 |
|
T7 |
7 |
|
T45 |
17 |
|
T46 |
2 |
| others[2] |
1151 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T41 |
1 |
| others[3] |
1810 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
7 |
| false |
577 |
1 |
|
T7 |
2 |
|
T42 |
1 |
|
T45 |
15 |
| true |
310 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T45 |
5 |
|
T58 |
4 |
|
T285 |
1 |
| others[1] |
85 |
1 |
|
T45 |
2 |
|
T58 |
3 |
|
T30 |
6 |
| others[2] |
85 |
1 |
|
T45 |
2 |
|
T58 |
3 |
|
T30 |
6 |
| others[3] |
171 |
1 |
|
T45 |
9 |
|
T58 |
7 |
|
T285 |
1 |
| false |
36 |
1 |
|
T45 |
1 |
|
T58 |
2 |
|
T111 |
1 |
| true |
5594 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
174 |
1 |
|
T45 |
8 |
|
T58 |
12 |
|
T111 |
1 |
| others[1] |
190 |
1 |
|
T45 |
9 |
|
T58 |
12 |
|
T30 |
10 |
| others[2] |
211 |
1 |
|
T5 |
1 |
|
T40 |
1 |
|
T45 |
8 |
| others[3] |
323 |
1 |
|
T45 |
23 |
|
T58 |
16 |
|
T30 |
7 |
| false |
109 |
1 |
|
T45 |
8 |
|
T58 |
5 |
|
T285 |
1 |
| true |
5050 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
899 |
1 |
|
T7 |
5 |
|
T19 |
1 |
|
T45 |
17 |
| others[1] |
855 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T45 |
23 |
| others[2] |
950 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T23 |
1 |
| others[3] |
1555 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T13 |
1 |
| false |
487 |
1 |
|
T4 |
1 |
|
T7 |
3 |
|
T45 |
9 |
| true |
1311 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T40 |
1 |
|
T45 |
15 |
|
T58 |
11 |
| others[1] |
176 |
1 |
|
T33 |
1 |
|
T45 |
8 |
|
T58 |
10 |
| others[2] |
181 |
1 |
|
T4 |
1 |
|
T45 |
12 |
|
T58 |
8 |
| others[3] |
334 |
1 |
|
T5 |
1 |
|
T45 |
10 |
|
T58 |
21 |
| false |
100 |
1 |
|
T45 |
5 |
|
T139 |
1 |
|
T58 |
3 |
| true |
5064 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |