Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
191 |
1 |
|
T45 |
10 |
|
T139 |
1 |
|
T58 |
11 |
| others[1] |
178 |
1 |
|
T45 |
11 |
|
T58 |
5 |
|
T30 |
12 |
| others[2] |
201 |
1 |
|
T45 |
16 |
|
T58 |
13 |
|
T30 |
14 |
| others[3] |
314 |
1 |
|
T45 |
15 |
|
T58 |
16 |
|
T117 |
1 |
| false |
95 |
1 |
|
T45 |
3 |
|
T58 |
7 |
|
T30 |
6 |
| true |
5078 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1111 |
1 |
|
T7 |
4 |
|
T45 |
19 |
|
T46 |
4 |
| others[1] |
1088 |
1 |
|
T7 |
3 |
|
T45 |
20 |
|
T46 |
1 |
| others[2] |
1089 |
1 |
|
T7 |
3 |
|
T45 |
19 |
|
T25 |
1 |
| others[3] |
1886 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
8 |
| false |
540 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T8 |
1 |
| true |
343 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1126 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T14 |
1 |
| others[1] |
1154 |
1 |
|
T7 |
7 |
|
T8 |
1 |
|
T45 |
19 |
| others[2] |
1109 |
1 |
|
T7 |
2 |
|
T19 |
1 |
|
T45 |
20 |
| others[3] |
1795 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
6 |
| false |
555 |
1 |
|
T7 |
1 |
|
T23 |
1 |
|
T45 |
8 |
| true |
318 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T45 |
3 |
|
T58 |
1 |
|
T111 |
1 |
| others[1] |
76 |
1 |
|
T45 |
3 |
|
T58 |
5 |
|
T112 |
1 |
| others[2] |
86 |
1 |
|
T45 |
1 |
|
T139 |
1 |
|
T58 |
5 |
| others[3] |
156 |
1 |
|
T45 |
5 |
|
T58 |
4 |
|
T285 |
1 |
| false |
51 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T30 |
2 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T45 |
9 |
|
T139 |
1 |
|
T58 |
9 |
| others[1] |
189 |
1 |
|
T5 |
1 |
|
T40 |
1 |
|
T45 |
8 |
| others[2] |
197 |
1 |
|
T45 |
10 |
|
T58 |
10 |
|
T30 |
9 |
| others[3] |
350 |
1 |
|
T45 |
16 |
|
T58 |
20 |
|
T285 |
2 |
| false |
101 |
1 |
|
T45 |
4 |
|
T58 |
4 |
|
T30 |
3 |
| true |
5022 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
937 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
4 |
| others[1] |
915 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T19 |
1 |
| others[2] |
939 |
1 |
|
T7 |
3 |
|
T43 |
1 |
|
T45 |
23 |
| others[3] |
1582 |
1 |
|
T7 |
7 |
|
T41 |
1 |
|
T45 |
32 |
| false |
442 |
1 |
|
T4 |
1 |
|
T7 |
3 |
|
T23 |
1 |
| true |
1242 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T4 |
1 |
|
T45 |
6 |
|
T58 |
11 |
| others[1] |
186 |
1 |
|
T33 |
1 |
|
T45 |
12 |
|
T58 |
7 |
| others[2] |
231 |
1 |
|
T45 |
13 |
|
T139 |
1 |
|
T58 |
15 |
| others[3] |
313 |
1 |
|
T5 |
1 |
|
T45 |
15 |
|
T58 |
12 |
| false |
99 |
1 |
|
T45 |
5 |
|
T58 |
3 |
|
T30 |
6 |
| true |
5025 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T45 |
8 |
|
T58 |
7 |
|
T52 |
1 |
| others[1] |
195 |
1 |
|
T45 |
8 |
|
T58 |
8 |
|
T115 |
1 |
| others[2] |
182 |
1 |
|
T45 |
9 |
|
T58 |
9 |
|
T257 |
1 |
| others[3] |
313 |
1 |
|
T45 |
15 |
|
T58 |
19 |
|
T34 |
1 |
| false |
103 |
1 |
|
T45 |
7 |
|
T58 |
9 |
|
T30 |
10 |
| true |
5074 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1084 |
1 |
|
T3 |
1 |
|
T7 |
6 |
|
T45 |
8 |
| others[1] |
1128 |
1 |
|
T7 |
4 |
|
T8 |
1 |
|
T41 |
1 |
| others[2] |
1091 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T45 |
21 |
| others[3] |
1847 |
1 |
|
T1 |
1 |
|
T7 |
7 |
|
T42 |
1 |
| false |
559 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T45 |
9 |
| true |
348 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1096 |
1 |
|
T7 |
5 |
|
T45 |
17 |
|
T46 |
4 |
| others[1] |
1042 |
1 |
|
T7 |
4 |
|
T19 |
1 |
|
T45 |
21 |
| others[2] |
1112 |
1 |
|
T1 |
1 |
|
T7 |
6 |
|
T45 |
19 |
| others[3] |
1888 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T41 |
1 |
| false |
609 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T8 |
1 |
| true |
310 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T58 |
4 |
|
T285 |
1 |
|
T30 |
10 |
| others[1] |
89 |
1 |
|
T45 |
5 |
|
T58 |
1 |
|
T111 |
1 |
| others[2] |
90 |
1 |
|
T45 |
2 |
|
T58 |
5 |
|
T257 |
1 |
| others[3] |
141 |
1 |
|
T45 |
8 |
|
T58 |
14 |
|
T285 |
1 |
| false |
48 |
1 |
|
T45 |
2 |
|
T58 |
1 |
|
T30 |
4 |
| true |
5592 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T33 |
1 |
|
T45 |
9 |
|
T58 |
16 |
| others[1] |
195 |
1 |
|
T5 |
1 |
|
T45 |
11 |
|
T58 |
8 |
| others[2] |
199 |
1 |
|
T45 |
9 |
|
T58 |
9 |
|
T30 |
12 |
| others[3] |
310 |
1 |
|
T4 |
1 |
|
T45 |
27 |
|
T58 |
17 |
| false |
118 |
1 |
|
T40 |
1 |
|
T45 |
6 |
|
T58 |
9 |
| true |
5033 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
904 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T45 |
13 |
| others[1] |
970 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T13 |
1 |
| others[2] |
926 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T7 |
3 |
| others[3] |
1527 |
1 |
|
T5 |
1 |
|
T7 |
6 |
|
T42 |
1 |
| false |
480 |
1 |
|
T7 |
2 |
|
T45 |
3 |
|
T46 |
2 |
| true |
1250 |
1 |
|
T40 |
1 |
|
T14 |
2 |
|
T96 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T45 |
10 |
|
T139 |
1 |
|
T58 |
9 |
| others[1] |
193 |
1 |
|
T45 |
7 |
|
T58 |
8 |
|
T34 |
1 |
| others[2] |
170 |
1 |
|
T45 |
8 |
|
T58 |
9 |
|
T112 |
1 |
| others[3] |
317 |
1 |
|
T45 |
13 |
|
T58 |
19 |
|
T111 |
1 |
| false |
120 |
1 |
|
T45 |
10 |
|
T58 |
6 |
|
T30 |
5 |
| true |
5059 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T45 |
15 |
|
T58 |
12 |
|
T285 |
1 |
| others[1] |
171 |
1 |
|
T45 |
6 |
|
T58 |
9 |
|
T116 |
1 |
| others[2] |
180 |
1 |
|
T45 |
8 |
|
T58 |
9 |
|
T38 |
1 |
| others[3] |
287 |
1 |
|
T45 |
17 |
|
T58 |
12 |
|
T30 |
17 |
| false |
99 |
1 |
|
T45 |
5 |
|
T58 |
4 |
|
T30 |
2 |
| true |
5108 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T7 |
5 |
|
T45 |
25 |
|
T46 |
1 |
| others[1] |
1091 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T41 |
1 |
| others[2] |
1115 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T45 |
14 |
| others[3] |
1852 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| false |
593 |
1 |
|
T7 |
4 |
|
T19 |
1 |
|
T45 |
11 |
| true |
340 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1125 |
1 |
|
T7 |
2 |
|
T45 |
24 |
|
T46 |
7 |
| others[1] |
1107 |
1 |
|
T7 |
5 |
|
T45 |
15 |
|
T46 |
3 |
| others[2] |
1075 |
1 |
|
T1 |
1 |
|
T7 |
3 |
|
T45 |
19 |
| others[3] |
1871 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
10 |
| false |
562 |
1 |
|
T7 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| true |
317 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T45 |
4 |
|
T58 |
1 |
|
T285 |
2 |
| others[1] |
82 |
1 |
|
T45 |
5 |
|
T58 |
1 |
|
T30 |
4 |
| others[2] |
114 |
1 |
|
T45 |
4 |
|
T58 |
9 |
|
T111 |
1 |
| others[3] |
152 |
1 |
|
T45 |
14 |
|
T58 |
3 |
|
T52 |
1 |
| false |
46 |
1 |
|
T45 |
1 |
|
T257 |
1 |
|
T30 |
2 |
| true |
5569 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
171 |
1 |
|
T45 |
6 |
|
T58 |
9 |
|
T285 |
1 |
| others[1] |
234 |
1 |
|
T40 |
1 |
|
T45 |
9 |
|
T139 |
1 |
| others[2] |
210 |
1 |
|
T45 |
5 |
|
T58 |
9 |
|
T30 |
12 |
| others[3] |
348 |
1 |
|
T45 |
17 |
|
T58 |
17 |
|
T111 |
1 |
| false |
109 |
1 |
|
T45 |
4 |
|
T58 |
8 |
|
T30 |
10 |
| true |
4985 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
973 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T23 |
1 |
| others[1] |
903 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T19 |
1 |
| others[2] |
914 |
1 |
|
T7 |
5 |
|
T42 |
1 |
|
T45 |
13 |
| others[3] |
1549 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
6 |
| false |
467 |
1 |
|
T7 |
2 |
|
T45 |
15 |
|
T46 |
2 |
| true |
1251 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T45 |
11 |
|
T139 |
1 |
|
T58 |
11 |
| others[1] |
180 |
1 |
|
T45 |
9 |
|
T58 |
9 |
|
T111 |
1 |
| others[2] |
184 |
1 |
|
T5 |
1 |
|
T45 |
13 |
|
T58 |
6 |
| others[3] |
319 |
1 |
|
T45 |
16 |
|
T58 |
24 |
|
T285 |
1 |
| false |
100 |
1 |
|
T45 |
3 |
|
T58 |
2 |
|
T38 |
1 |
| true |
5076 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
177 |
1 |
|
T45 |
18 |
|
T58 |
15 |
|
T257 |
1 |
| others[1] |
185 |
1 |
|
T45 |
12 |
|
T58 |
7 |
|
T38 |
1 |
| others[2] |
185 |
1 |
|
T45 |
8 |
|
T58 |
12 |
|
T30 |
11 |
| others[3] |
320 |
1 |
|
T45 |
16 |
|
T139 |
1 |
|
T58 |
12 |
| false |
112 |
1 |
|
T45 |
6 |
|
T58 |
6 |
|
T30 |
4 |
| true |
5078 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T1 |
1 |
|
T7 |
5 |
|
T19 |
1 |
| others[1] |
1114 |
1 |
|
T2 |
1 |
|
T7 |
7 |
|
T45 |
20 |
| others[2] |
1100 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T45 |
18 |
| others[3] |
1852 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T45 |
34 |
| false |
576 |
1 |
|
T7 |
4 |
|
T8 |
1 |
|
T45 |
9 |
| true |
344 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1132 |
1 |
|
T7 |
6 |
|
T8 |
1 |
|
T45 |
15 |
| others[1] |
1104 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T41 |
1 |
| others[2] |
1102 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
1817 |
1 |
|
T7 |
10 |
|
T19 |
1 |
|
T45 |
33 |
| false |
575 |
1 |
|
T7 |
1 |
|
T45 |
10 |
|
T46 |
5 |
| true |
327 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T45 |
6 |
|
T58 |
3 |
|
T285 |
1 |
| others[1] |
90 |
1 |
|
T40 |
1 |
|
T45 |
3 |
|
T58 |
2 |
| others[2] |
94 |
1 |
|
T45 |
4 |
|
T58 |
3 |
|
T111 |
1 |
| others[3] |
146 |
1 |
|
T45 |
8 |
|
T58 |
5 |
|
T112 |
1 |
| false |
52 |
1 |
|
T45 |
2 |
|
T58 |
2 |
|
T30 |
4 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T45 |
9 |
|
T58 |
12 |
|
T38 |
1 |
| others[1] |
184 |
1 |
|
T4 |
1 |
|
T45 |
9 |
|
T58 |
7 |
| others[2] |
176 |
1 |
|
T45 |
15 |
|
T139 |
1 |
|
T58 |
10 |
| others[3] |
310 |
1 |
|
T45 |
16 |
|
T58 |
16 |
|
T111 |
1 |
| false |
111 |
1 |
|
T45 |
4 |
|
T58 |
4 |
|
T30 |
9 |
| true |
5070 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
943 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T23 |
1 |
| others[1] |
984 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
| others[2] |
874 |
1 |
|
T7 |
3 |
|
T43 |
1 |
|
T45 |
19 |
| others[3] |
1503 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
481 |
1 |
|
T7 |
2 |
|
T45 |
11 |
|
T139 |
1 |
| true |
1272 |
1 |
|
T42 |
1 |
|
T33 |
1 |
|
T40 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
176 |
1 |
|
T45 |
9 |
|
T58 |
17 |
|
T115 |
1 |
| others[1] |
192 |
1 |
|
T45 |
16 |
|
T139 |
1 |
|
T58 |
12 |
| others[2] |
196 |
1 |
|
T5 |
1 |
|
T45 |
11 |
|
T58 |
13 |
| others[3] |
333 |
1 |
|
T4 |
1 |
|
T45 |
15 |
|
T58 |
14 |
| false |
106 |
1 |
|
T45 |
2 |
|
T58 |
4 |
|
T30 |
5 |
| true |
5054 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T45 |
7 |
|
T58 |
6 |
|
T38 |
1 |
| others[1] |
176 |
1 |
|
T45 |
13 |
|
T58 |
11 |
|
T30 |
9 |
| others[2] |
174 |
1 |
|
T45 |
12 |
|
T58 |
3 |
|
T116 |
1 |
| others[3] |
324 |
1 |
|
T40 |
1 |
|
T45 |
22 |
|
T58 |
22 |
| false |
121 |
1 |
|
T45 |
5 |
|
T58 |
9 |
|
T30 |
11 |
| true |
5066 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1112 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| others[1] |
1114 |
1 |
|
T7 |
4 |
|
T23 |
1 |
|
T45 |
23 |
| others[2] |
1071 |
1 |
|
T7 |
5 |
|
T19 |
1 |
|
T45 |
14 |
| others[3] |
1830 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
9 |
| false |
591 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T45 |
13 |
| true |
339 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T316 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
8 |
1 |
|
T287 |
1 |
|
T317 |
1 |
|
T318 |
1 |
| others[2] |
2 |
1 |
|
T319 |
1 |
|
T310 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T312 |
1 |
|
T320 |
1 |
|
T321 |
1 |
| false |
11 |
1 |
|
T21 |
1 |
|
T289 |
1 |
|
T307 |
1 |
| true |
16 |
1 |
|
T24 |
1 |
|
T110 |
1 |
|
T156 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |