Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9377 |
1 |
|
T1 |
1 |
|
T7 |
4 |
|
T50 |
2 |
| others[1] |
644 |
1 |
|
T6 |
1 |
|
T7 |
7 |
|
T8 |
1 |
| others[2] |
708 |
1 |
|
T7 |
7 |
|
T45 |
23 |
|
T46 |
2 |
| others[3] |
1081 |
1 |
|
T7 |
2 |
|
T41 |
1 |
|
T19 |
1 |
| false |
302 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T45 |
7 |
| true |
428 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2138 |
1 |
|
T7 |
7 |
|
T50 |
1 |
|
T45 |
10 |
| others[1] |
2236 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
| others[2] |
2158 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T41 |
1 |
| others[3] |
3613 |
1 |
|
T7 |
3 |
|
T50 |
1 |
|
T19 |
1 |
| false |
1087 |
1 |
|
T7 |
3 |
|
T45 |
6 |
|
T58 |
5 |
| true |
1308 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8865 |
1 |
|
T5 |
1 |
|
T50 |
2 |
|
T45 |
9 |
| others[1] |
230 |
1 |
|
T6 |
1 |
|
T45 |
8 |
|
T25 |
1 |
| others[2] |
214 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T45 |
8 |
| others[3] |
366 |
1 |
|
T41 |
1 |
|
T45 |
7 |
|
T58 |
15 |
| false |
113 |
1 |
|
T45 |
6 |
|
T58 |
6 |
|
T112 |
1 |
| true |
2752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9056 |
1 |
|
T13 |
1 |
|
T42 |
1 |
|
T43 |
1 |
| others[1] |
407 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T45 |
8 |
| others[2] |
406 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T45 |
14 |
| others[3] |
634 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T19 |
1 |
| false |
186 |
1 |
|
T7 |
1 |
|
T45 |
3 |
|
T46 |
1 |
| true |
1851 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8836 |
1 |
|
T50 |
2 |
|
T45 |
10 |
|
T58 |
8 |
| others[1] |
181 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T315 |
1 |
| others[2] |
210 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T8 |
1 |
| others[3] |
368 |
1 |
|
T40 |
1 |
|
T45 |
12 |
|
T58 |
16 |
| false |
124 |
1 |
|
T45 |
3 |
|
T58 |
4 |
|
T116 |
1 |
| true |
2821 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8824 |
1 |
|
T2 |
1 |
|
T50 |
2 |
|
T45 |
10 |
| others[1] |
221 |
1 |
|
T8 |
1 |
|
T45 |
11 |
|
T58 |
13 |
| others[2] |
235 |
1 |
|
T41 |
1 |
|
T19 |
1 |
|
T45 |
16 |
| others[3] |
368 |
1 |
|
T6 |
1 |
|
T45 |
17 |
|
T58 |
24 |
| false |
118 |
1 |
|
T45 |
4 |
|
T58 |
10 |
|
T322 |
1 |
| true |
2774 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9307 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T8 |
1 |
| others[1] |
672 |
1 |
|
T2 |
1 |
|
T7 |
7 |
|
T42 |
1 |
| others[2] |
663 |
1 |
|
T1 |
1 |
|
T7 |
4 |
|
T14 |
1 |
| others[3] |
1118 |
1 |
|
T7 |
6 |
|
T14 |
1 |
|
T19 |
1 |
| false |
369 |
1 |
|
T7 |
1 |
|
T45 |
16 |
|
T58 |
11 |
| true |
411 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9313 |
1 |
|
T7 |
3 |
|
T50 |
2 |
|
T45 |
16 |
| others[1] |
621 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[2] |
688 |
1 |
|
T7 |
2 |
|
T45 |
28 |
|
T46 |
3 |
| others[3] |
1108 |
1 |
|
T2 |
1 |
|
T7 |
12 |
|
T19 |
1 |
| false |
360 |
1 |
|
T7 |
3 |
|
T45 |
10 |
|
T46 |
1 |
| true |
421 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2206 |
1 |
|
T7 |
3 |
|
T50 |
1 |
|
T45 |
11 |
| others[1] |
2165 |
1 |
|
T2 |
1 |
|
T7 |
5 |
|
T40 |
1 |
| others[2] |
2132 |
1 |
|
T7 |
4 |
|
T41 |
1 |
|
T19 |
1 |
| others[3] |
3581 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
5 |
| false |
1110 |
1 |
|
T7 |
4 |
|
T8 |
1 |
|
T45 |
8 |
| true |
1317 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8873 |
1 |
|
T41 |
1 |
|
T50 |
2 |
|
T45 |
7 |
| others[1] |
243 |
1 |
|
T8 |
1 |
|
T45 |
14 |
|
T58 |
6 |
| others[2] |
234 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T45 |
9 |
| others[3] |
365 |
1 |
|
T23 |
1 |
|
T45 |
15 |
|
T139 |
1 |
| false |
114 |
1 |
|
T4 |
1 |
|
T45 |
3 |
|
T25 |
1 |
| true |
2682 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9025 |
1 |
|
T7 |
5 |
|
T33 |
1 |
|
T50 |
2 |
| others[1] |
411 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T45 |
12 |
| others[2] |
387 |
1 |
|
T7 |
4 |
|
T43 |
1 |
|
T45 |
11 |
| others[3] |
660 |
1 |
|
T7 |
2 |
|
T45 |
13 |
|
T46 |
3 |
| false |
192 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T13 |
1 |
| true |
1836 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8849 |
1 |
|
T33 |
1 |
|
T50 |
2 |
|
T45 |
15 |
| others[1] |
222 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T45 |
8 |
| others[2] |
220 |
1 |
|
T45 |
9 |
|
T58 |
10 |
|
T210 |
1 |
| others[3] |
364 |
1 |
|
T45 |
6 |
|
T58 |
15 |
|
T22 |
1 |
| false |
117 |
1 |
|
T45 |
7 |
|
T58 |
7 |
|
T113 |
1 |
| true |
2739 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8839 |
1 |
|
T50 |
2 |
|
T45 |
2 |
|
T58 |
17 |
| others[1] |
194 |
1 |
|
T45 |
8 |
|
T58 |
12 |
|
T44 |
1 |
| others[2] |
219 |
1 |
|
T45 |
13 |
|
T58 |
12 |
|
T112 |
1 |
| others[3] |
358 |
1 |
|
T1 |
1 |
|
T40 |
1 |
|
T8 |
1 |
| false |
119 |
1 |
|
T2 |
1 |
|
T45 |
3 |
|
T58 |
2 |
| true |
2782 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9290 |
1 |
|
T1 |
1 |
|
T41 |
1 |
|
T50 |
2 |
| others[1] |
664 |
1 |
|
T6 |
1 |
|
T7 |
10 |
|
T45 |
20 |
| others[2] |
684 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T19 |
1 |
| others[3] |
1139 |
1 |
|
T7 |
6 |
|
T8 |
1 |
|
T45 |
38 |
| false |
344 |
1 |
|
T7 |
1 |
|
T45 |
6 |
|
T46 |
2 |
| true |
390 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9259 |
1 |
|
T7 |
1 |
|
T50 |
2 |
|
T45 |
18 |
| others[1] |
703 |
1 |
|
T2 |
1 |
|
T7 |
5 |
|
T41 |
1 |
| others[2] |
681 |
1 |
|
T7 |
2 |
|
T8 |
1 |
|
T45 |
24 |
| others[3] |
1089 |
1 |
|
T6 |
1 |
|
T7 |
11 |
|
T23 |
1 |
| false |
363 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T19 |
1 |
| true |
416 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2132 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
7 |
| others[1] |
2190 |
1 |
|
T7 |
4 |
|
T45 |
8 |
|
T58 |
9 |
| others[2] |
2197 |
1 |
|
T7 |
3 |
|
T45 |
11 |
|
T58 |
15 |
| others[3] |
3551 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T41 |
1 |
| false |
1156 |
1 |
|
T7 |
1 |
|
T45 |
6 |
|
T139 |
1 |
| true |
1285 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8870 |
1 |
|
T50 |
2 |
|
T45 |
8 |
|
T58 |
12 |
| others[1] |
239 |
1 |
|
T45 |
9 |
|
T58 |
11 |
|
T22 |
2 |
| others[2] |
217 |
1 |
|
T2 |
1 |
|
T45 |
6 |
|
T58 |
11 |
| others[3] |
378 |
1 |
|
T45 |
21 |
|
T58 |
17 |
|
T22 |
1 |
| false |
130 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T45 |
5 |
| true |
2677 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9038 |
1 |
|
T13 |
1 |
|
T41 |
1 |
|
T50 |
2 |
| others[1] |
415 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T45 |
4 |
| others[2] |
403 |
1 |
|
T5 |
1 |
|
T7 |
5 |
|
T45 |
10 |
| others[3] |
628 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T33 |
1 |
| false |
201 |
1 |
|
T45 |
11 |
|
T46 |
4 |
|
T58 |
4 |
| true |
1826 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8818 |
1 |
|
T50 |
2 |
|
T19 |
1 |
|
T45 |
10 |
| others[1] |
210 |
1 |
|
T8 |
1 |
|
T23 |
1 |
|
T45 |
10 |
| others[2] |
201 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T45 |
7 |
| others[3] |
391 |
1 |
|
T1 |
1 |
|
T40 |
1 |
|
T45 |
15 |
| false |
126 |
1 |
|
T2 |
1 |
|
T45 |
6 |
|
T25 |
1 |
| true |
2765 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8854 |
1 |
|
T1 |
1 |
|
T40 |
1 |
|
T41 |
1 |
| others[1] |
203 |
1 |
|
T45 |
7 |
|
T58 |
13 |
|
T22 |
1 |
| others[2] |
200 |
1 |
|
T45 |
3 |
|
T139 |
1 |
|
T58 |
8 |
| others[3] |
329 |
1 |
|
T45 |
16 |
|
T58 |
7 |
|
T44 |
1 |
| false |
109 |
1 |
|
T8 |
1 |
|
T45 |
6 |
|
T58 |
5 |
| true |
2816 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9273 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
4 |
| others[1] |
697 |
1 |
|
T7 |
5 |
|
T19 |
1 |
|
T45 |
19 |
| others[2] |
658 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T45 |
19 |
| others[3] |
1123 |
1 |
|
T6 |
1 |
|
T7 |
7 |
|
T8 |
1 |
| false |
346 |
1 |
|
T7 |
2 |
|
T14 |
1 |
|
T45 |
12 |
| true |
414 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9267 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
5 |
| others[1] |
691 |
1 |
|
T7 |
5 |
|
T23 |
1 |
|
T45 |
24 |
| others[2] |
666 |
1 |
|
T2 |
1 |
|
T7 |
4 |
|
T45 |
18 |
| others[3] |
1113 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T8 |
1 |
| false |
360 |
1 |
|
T7 |
2 |
|
T45 |
5 |
|
T46 |
2 |
| true |
414 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2162 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[1] |
2174 |
1 |
|
T7 |
7 |
|
T50 |
1 |
|
T45 |
4 |
| others[2] |
2216 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T40 |
1 |
| others[3] |
3582 |
1 |
|
T7 |
8 |
|
T8 |
1 |
|
T41 |
1 |
| false |
1101 |
1 |
|
T7 |
2 |
|
T45 |
10 |
|
T25 |
1 |
| true |
1276 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8852 |
1 |
|
T50 |
2 |
|
T45 |
7 |
|
T58 |
12 |
| others[1] |
239 |
1 |
|
T45 |
10 |
|
T58 |
17 |
|
T112 |
1 |
| others[2] |
221 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T45 |
9 |
| others[3] |
377 |
1 |
|
T33 |
1 |
|
T41 |
1 |
|
T45 |
17 |
| false |
112 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T45 |
3 |
| true |
2710 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9004 |
1 |
|
T50 |
2 |
|
T45 |
11 |
|
T139 |
1 |
| others[1] |
382 |
1 |
|
T7 |
2 |
|
T45 |
8 |
|
T25 |
1 |
| others[2] |
395 |
1 |
|
T3 |
1 |
|
T7 |
2 |
|
T40 |
1 |
| others[3] |
654 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
| false |
238 |
1 |
|
T7 |
3 |
|
T23 |
1 |
|
T45 |
8 |
| true |
1838 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8840 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T50 |
2 |
| others[1] |
225 |
1 |
|
T41 |
1 |
|
T45 |
9 |
|
T58 |
11 |
| others[2] |
227 |
1 |
|
T45 |
8 |
|
T58 |
17 |
|
T22 |
3 |
| others[3] |
390 |
1 |
|
T23 |
1 |
|
T45 |
21 |
|
T58 |
15 |
| false |
117 |
1 |
|
T4 |
1 |
|
T45 |
5 |
|
T58 |
2 |
| true |
2712 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8868 |
1 |
|
T41 |
1 |
|
T50 |
2 |
|
T45 |
11 |
| others[1] |
194 |
1 |
|
T40 |
1 |
|
T19 |
1 |
|
T45 |
6 |
| others[2] |
201 |
1 |
|
T1 |
1 |
|
T45 |
7 |
|
T58 |
11 |
| others[3] |
370 |
1 |
|
T6 |
1 |
|
T23 |
1 |
|
T45 |
17 |
| false |
112 |
1 |
|
T45 |
3 |
|
T58 |
6 |
|
T22 |
1 |
| true |
2766 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9293 |
1 |
|
T7 |
8 |
|
T41 |
1 |
|
T50 |
2 |
| others[1] |
655 |
1 |
|
T7 |
4 |
|
T45 |
23 |
|
T46 |
3 |
| others[2] |
670 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T8 |
1 |
| others[3] |
1124 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T19 |
1 |
| false |
359 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T45 |
9 |
| true |
410 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9308 |
1 |
|
T2 |
1 |
|
T7 |
3 |
|
T50 |
2 |
| others[1] |
690 |
1 |
|
T6 |
1 |
|
T7 |
10 |
|
T45 |
19 |
| others[2] |
629 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T19 |
1 |
| others[3] |
1106 |
1 |
|
T7 |
6 |
|
T8 |
1 |
|
T23 |
1 |
| false |
345 |
1 |
|
T7 |
1 |
|
T41 |
1 |
|
T45 |
7 |
| true |
433 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2187 |
1 |
|
T2 |
1 |
|
T7 |
6 |
|
T8 |
1 |
| others[1] |
2172 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
6 |
| others[2] |
2170 |
1 |
|
T45 |
11 |
|
T58 |
12 |
|
T22 |
1 |
| others[3] |
3615 |
1 |
|
T7 |
7 |
|
T50 |
1 |
|
T23 |
1 |
| false |
1101 |
1 |
|
T7 |
2 |
|
T40 |
1 |
|
T41 |
1 |
| true |
1266 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8837 |
1 |
|
T40 |
1 |
|
T50 |
2 |
|
T45 |
7 |
| others[1] |
239 |
1 |
|
T1 |
1 |
|
T45 |
9 |
|
T25 |
1 |
| others[2] |
209 |
1 |
|
T33 |
1 |
|
T19 |
1 |
|
T45 |
12 |
| others[3] |
344 |
1 |
|
T6 |
1 |
|
T41 |
1 |
|
T23 |
1 |
| false |
120 |
1 |
|
T4 |
1 |
|
T45 |
6 |
|
T58 |
9 |
| true |
2762 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |