Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9017 |
1 |
|
T7 |
2 |
|
T50 |
2 |
|
T45 |
16 |
| others[1] |
399 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T45 |
15 |
| others[2] |
361 |
1 |
|
T5 |
1 |
|
T7 |
3 |
|
T33 |
1 |
| others[3] |
682 |
1 |
|
T7 |
3 |
|
T19 |
1 |
|
T45 |
15 |
| false |
190 |
1 |
|
T13 |
1 |
|
T45 |
3 |
|
T58 |
7 |
| true |
1862 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8831 |
1 |
|
T50 |
2 |
|
T45 |
4 |
|
T139 |
1 |
| others[1] |
194 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| others[2] |
202 |
1 |
|
T45 |
8 |
|
T58 |
10 |
|
T44 |
1 |
| others[3] |
381 |
1 |
|
T1 |
1 |
|
T41 |
1 |
|
T45 |
17 |
| false |
111 |
1 |
|
T45 |
7 |
|
T58 |
6 |
|
T257 |
1 |
| true |
2792 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8820 |
1 |
|
T50 |
2 |
|
T45 |
8 |
|
T58 |
9 |
| others[1] |
193 |
1 |
|
T45 |
7 |
|
T58 |
10 |
|
T22 |
2 |
| others[2] |
240 |
1 |
|
T41 |
1 |
|
T45 |
14 |
|
T58 |
16 |
| others[3] |
385 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T45 |
17 |
| false |
115 |
1 |
|
T45 |
9 |
|
T58 |
6 |
|
T253 |
1 |
| true |
2758 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9279 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T50 |
2 |
| others[1] |
651 |
1 |
|
T1 |
1 |
|
T7 |
7 |
|
T19 |
1 |
| others[2] |
703 |
1 |
|
T7 |
4 |
|
T8 |
1 |
|
T23 |
1 |
| others[3] |
1119 |
1 |
|
T2 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| false |
360 |
1 |
|
T7 |
3 |
|
T45 |
17 |
|
T58 |
13 |
| true |
399 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9296 |
1 |
|
T7 |
3 |
|
T50 |
2 |
|
T45 |
19 |
| others[1] |
688 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
4 |
| others[2] |
702 |
1 |
|
T7 |
5 |
|
T42 |
1 |
|
T23 |
1 |
| others[3] |
1108 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
6 |
| false |
311 |
1 |
|
T7 |
3 |
|
T19 |
1 |
|
T45 |
10 |
| true |
406 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2158 |
1 |
|
T7 |
3 |
|
T50 |
1 |
|
T45 |
9 |
| others[1] |
2160 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T8 |
1 |
| others[2] |
2130 |
1 |
|
T7 |
2 |
|
T50 |
1 |
|
T19 |
1 |
| others[3] |
3655 |
1 |
|
T2 |
1 |
|
T7 |
8 |
|
T41 |
1 |
| false |
1154 |
1 |
|
T1 |
1 |
|
T7 |
4 |
|
T45 |
9 |
| true |
1254 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8831 |
1 |
|
T1 |
1 |
|
T50 |
2 |
|
T45 |
10 |
| others[1] |
225 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T45 |
9 |
| others[2] |
200 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T45 |
9 |
| others[3] |
417 |
1 |
|
T33 |
1 |
|
T45 |
25 |
|
T58 |
21 |
| false |
110 |
1 |
|
T45 |
3 |
|
T58 |
5 |
|
T250 |
1 |
| true |
2728 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9023 |
1 |
|
T4 |
1 |
|
T7 |
3 |
|
T50 |
2 |
| others[1] |
352 |
1 |
|
T7 |
2 |
|
T45 |
9 |
|
T46 |
4 |
| others[2] |
406 |
1 |
|
T7 |
4 |
|
T41 |
1 |
|
T45 |
5 |
| others[3] |
690 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T42 |
1 |
| false |
193 |
1 |
|
T13 |
1 |
|
T45 |
8 |
|
T58 |
4 |
| true |
1847 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8862 |
1 |
|
T2 |
1 |
|
T40 |
1 |
|
T8 |
1 |
| others[1] |
209 |
1 |
|
T45 |
9 |
|
T58 |
13 |
|
T22 |
1 |
| others[2] |
227 |
1 |
|
T45 |
15 |
|
T58 |
9 |
|
T22 |
2 |
| others[3] |
353 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T33 |
1 |
| false |
134 |
1 |
|
T4 |
1 |
|
T45 |
5 |
|
T58 |
8 |
| true |
2726 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8837 |
1 |
|
T50 |
2 |
|
T45 |
9 |
|
T58 |
11 |
| others[1] |
205 |
1 |
|
T8 |
1 |
|
T45 |
4 |
|
T58 |
10 |
| others[2] |
212 |
1 |
|
T40 |
1 |
|
T45 |
8 |
|
T58 |
10 |
| others[3] |
355 |
1 |
|
T6 |
1 |
|
T45 |
23 |
|
T25 |
1 |
| false |
109 |
1 |
|
T23 |
1 |
|
T45 |
3 |
|
T58 |
4 |
| true |
2793 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9261 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T41 |
1 |
| others[1] |
685 |
1 |
|
T7 |
5 |
|
T8 |
1 |
|
T19 |
1 |
| others[2] |
658 |
1 |
|
T7 |
5 |
|
T23 |
1 |
|
T45 |
17 |
| others[3] |
1118 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
9 |
| false |
367 |
1 |
|
T7 |
1 |
|
T45 |
13 |
|
T46 |
2 |
| true |
422 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9309 |
1 |
|
T7 |
4 |
|
T50 |
2 |
|
T45 |
19 |
| others[1] |
645 |
1 |
|
T7 |
2 |
|
T45 |
20 |
|
T46 |
4 |
| others[2] |
695 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T41 |
1 |
| others[3] |
1124 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
11 |
| false |
321 |
1 |
|
T7 |
2 |
|
T45 |
11 |
|
T58 |
9 |
| true |
417 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2167 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T40 |
1 |
| others[1] |
2179 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
7 |
| others[2] |
2192 |
1 |
|
T7 |
4 |
|
T45 |
10 |
|
T25 |
1 |
| others[3] |
3627 |
1 |
|
T7 |
6 |
|
T50 |
1 |
|
T23 |
1 |
| false |
1045 |
1 |
|
T7 |
2 |
|
T41 |
1 |
|
T45 |
5 |
| true |
1301 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8844 |
1 |
|
T40 |
1 |
|
T8 |
1 |
|
T41 |
1 |
| others[1] |
226 |
1 |
|
T33 |
1 |
|
T19 |
1 |
|
T45 |
4 |
| others[2] |
225 |
1 |
|
T45 |
13 |
|
T139 |
1 |
|
T58 |
6 |
| others[3] |
374 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T45 |
16 |
| false |
137 |
1 |
|
T45 |
7 |
|
T25 |
1 |
|
T58 |
3 |
| true |
2705 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9064 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[1] |
384 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T43 |
1 |
| others[2] |
392 |
1 |
|
T7 |
2 |
|
T45 |
12 |
|
T46 |
1 |
| others[3] |
645 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
3 |
| false |
190 |
1 |
|
T7 |
1 |
|
T33 |
1 |
|
T45 |
5 |
| true |
1836 |
1 |
|
T13 |
1 |
|
T7 |
14 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8855 |
1 |
|
T50 |
2 |
|
T45 |
10 |
|
T139 |
1 |
| others[1] |
231 |
1 |
|
T45 |
7 |
|
T58 |
13 |
|
T22 |
1 |
| others[2] |
202 |
1 |
|
T8 |
1 |
|
T45 |
6 |
|
T58 |
10 |
| others[3] |
369 |
1 |
|
T4 |
1 |
|
T41 |
1 |
|
T45 |
15 |
| false |
116 |
1 |
|
T19 |
1 |
|
T45 |
4 |
|
T58 |
1 |
| true |
2738 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8851 |
1 |
|
T50 |
2 |
|
T45 |
4 |
|
T58 |
13 |
| others[1] |
211 |
1 |
|
T45 |
6 |
|
T58 |
9 |
|
T111 |
1 |
| others[2] |
216 |
1 |
|
T40 |
1 |
|
T45 |
10 |
|
T58 |
9 |
| others[3] |
367 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T45 |
17 |
| false |
102 |
1 |
|
T45 |
5 |
|
T25 |
1 |
|
T58 |
6 |
| true |
2764 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9303 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T50 |
2 |
| others[1] |
636 |
1 |
|
T7 |
4 |
|
T45 |
17 |
|
T25 |
1 |
| others[2] |
653 |
1 |
|
T7 |
8 |
|
T41 |
1 |
|
T45 |
21 |
| others[3] |
1121 |
1 |
|
T1 |
1 |
|
T7 |
6 |
|
T19 |
1 |
| false |
388 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T8 |
1 |
| true |
410 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9243 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T50 |
2 |
| others[1] |
704 |
1 |
|
T7 |
7 |
|
T45 |
14 |
|
T25 |
1 |
| others[2] |
675 |
1 |
|
T7 |
6 |
|
T45 |
19 |
|
T46 |
3 |
| others[3] |
1149 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
8 |
| false |
324 |
1 |
|
T45 |
15 |
|
T46 |
1 |
|
T58 |
8 |
| true |
416 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2110 |
1 |
|
T7 |
3 |
|
T40 |
1 |
|
T50 |
2 |
| others[1] |
2144 |
1 |
|
T7 |
5 |
|
T45 |
17 |
|
T58 |
14 |
| others[2] |
2161 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
2 |
| others[3] |
3725 |
1 |
|
T7 |
9 |
|
T41 |
1 |
|
T45 |
11 |
| false |
1128 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T45 |
13 |
| true |
1243 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8861 |
1 |
|
T2 |
1 |
|
T40 |
1 |
|
T41 |
1 |
| others[1] |
222 |
1 |
|
T45 |
13 |
|
T58 |
17 |
|
T34 |
1 |
| others[2] |
218 |
1 |
|
T19 |
1 |
|
T45 |
8 |
|
T58 |
6 |
| others[3] |
373 |
1 |
|
T1 |
1 |
|
T45 |
21 |
|
T58 |
19 |
| false |
123 |
1 |
|
T45 |
4 |
|
T58 |
6 |
|
T22 |
1 |
| true |
2714 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9019 |
1 |
|
T13 |
1 |
|
T7 |
2 |
|
T43 |
1 |
| others[1] |
398 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T19 |
1 |
| others[2] |
402 |
1 |
|
T5 |
1 |
|
T7 |
3 |
|
T40 |
1 |
| others[3] |
647 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
2 |
| false |
201 |
1 |
|
T7 |
2 |
|
T45 |
7 |
|
T58 |
2 |
| true |
1844 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8843 |
1 |
|
T50 |
2 |
|
T45 |
9 |
|
T58 |
13 |
| others[1] |
227 |
1 |
|
T5 |
1 |
|
T41 |
1 |
|
T45 |
13 |
| others[2] |
237 |
1 |
|
T45 |
9 |
|
T139 |
1 |
|
T58 |
13 |
| others[3] |
342 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T19 |
1 |
| false |
118 |
1 |
|
T40 |
1 |
|
T45 |
7 |
|
T58 |
4 |
| true |
2744 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8856 |
1 |
|
T2 |
1 |
|
T50 |
2 |
|
T23 |
1 |
| others[1] |
223 |
1 |
|
T45 |
9 |
|
T58 |
13 |
|
T210 |
1 |
| others[2] |
196 |
1 |
|
T45 |
9 |
|
T58 |
11 |
|
T209 |
1 |
| others[3] |
355 |
1 |
|
T40 |
1 |
|
T45 |
17 |
|
T58 |
19 |
| false |
96 |
1 |
|
T45 |
4 |
|
T139 |
1 |
|
T58 |
2 |
| true |
2785 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9284 |
1 |
|
T7 |
8 |
|
T8 |
1 |
|
T50 |
2 |
| others[1] |
665 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T45 |
22 |
| others[2] |
661 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T45 |
22 |
| others[3] |
1116 |
1 |
|
T7 |
9 |
|
T19 |
1 |
|
T23 |
1 |
| false |
364 |
1 |
|
T7 |
3 |
|
T41 |
1 |
|
T45 |
13 |
| true |
421 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |