Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	187871	1		T2	562		T4	30		T5	697
auto[FlashEraseBank]	166965	1		T2	461		T4	52		T5	435

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	189592	1		T4	48		T5	1132		T7	5
auto[FlashOpProgram]	147308	1		T2	1023		T4	34		T6	1006
auto[FlashOpErase]	14136	1		T7	10		T21	10		T24	12
auto[FlashOpInvalid]	3800	1		T149	200		T192	200		T193	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	189592	1		T4	48		T5	1132		T7	5
op[FlashOpProgram]	147308	1		T2	1023		T4	34		T6	1006
op[FlashOpErase]	14136	1		T7	10		T21	10		T24	12
read_erase_read	565	1		T7	1		T21	1		T24	4
read_prog_read	1018	1		T4	34		T33	1		T23	6

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	239332	1		T2	752		T4	3		T5	898
auto[FlashPartInfo]	112783	1		T2	271		T4	8		T5	234
auto[FlashPartInfo1]	630	1		T14	1		T19	15		T23	2
auto[FlashPartInfo2]	2091	1		T4	71		T33	2		T19	25

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	140549	1		T4	3		T5	898		T7	4
auto[FlashPartData]	auto[FlashOpProgram]	91657	1		T2	752		T6	696		T7	6
auto[FlashPartData]	auto[FlashOpErase]	3398	1		T7	10		T45	35		T96	1
auto[FlashPartData]	auto[FlashOpInvalid]	3728	1		T149	198		T192	200		T193	198
auto[FlashPartInfo]	auto[FlashOpRead]	47150	1		T4	8		T5	234		T7	1
auto[FlashPartInfo]	auto[FlashOpProgram]	54867	1		T2	271		T6	310		T33	1
auto[FlashPartInfo]	auto[FlashOpErase]	10714	1		T21	10		T24	12		T14	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	52	1		T149	2		T193	2		T323	2
auto[FlashPartInfo1]	auto[FlashOpRead]	557	1		T14	1		T19	15		T23	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	66	1		T133	2		T134	32		T324	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T133	2		T325	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T133	4		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1336	1		T4	37		T33	2		T19	25
auto[FlashPartInfo2]	auto[FlashOpProgram]	718	1		T4	34		T23	10		T25	4
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T22	1		T141	1		T132	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T133	2		T326	2		T327	2