Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
61.90	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	16	16	50.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	16	16	50.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27666	1		T7	4		T45	16		T46	4
auto[1]	9	1		T180	2		T194	3		T273	1
auto[2]	12	1		T48	4		T286	8		-	-
auto[3]	44	1		T33	2		T122	1		T123	2

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	6933	1		T7	1		T33	1		T45	4
evic_idx[1]	6935	1		T7	1		T45	4		T46	1
evic_idx[2]	6933	1		T7	1		T45	4		T46	1
evic_idx[3]	6930	1		T7	1		T33	1		T45	4

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	26952	1		T114	640		T172	528		T29	360
evic_op[2]	251	1		T33	2		T149	4		T122	1

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Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	16	16	50.00	16

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[3]]	--	--	12
*	[evic_op[2]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6738	1		T114	160		T172	132		T29	90
evic_idx[0]	evic_op[2]	auto[0]	49	1		T149	1		T169	1		T287	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T194	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T33	1		T288	1		T179	1
evic_idx[1]	evic_op[1]	auto[0]	6739	1		T114	160		T172	132		T29	90
evic_idx[1]	evic_op[2]	auto[0]	50	1		T149	1		T287	1		T289	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T194	1		T188	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T271	1		T290	1		T291	1
evic_idx[2]	evic_op[1]	auto[0]	6738	1		T114	160		T172	132		T29	90
evic_idx[2]	evic_op[2]	auto[0]	52	1		T149	1		T287	1		T289	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T180	1		T194	1		T273	1
evic_idx[2]	evic_op[2]	auto[3]	7	1		T123	1		T292	1		T293	1
evic_idx[3]	evic_op[1]	auto[0]	6737	1		T114	160		T172	132		T29	90
evic_idx[3]	evic_op[2]	auto[0]	47	1		T149	1		T287	1		T289	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T180	1		T294	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	12	1		T33	1		T122	1		T123	1