Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	49847	1		T2	5705		T116	1600		T117	1232
prog_lvl[2]	3249	1		T116	799		T117	615		T267	94
prog_lvl[3]	5	1		T116	1		T117	1		T267	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6741	1		T5	84		T118	2		T174	3
rd_lvl[2]	23399	1		T5	135		T328	4221		T118	14
rd_lvl[3]	9533	1		T5	1265		T328	1875		T118	11
rd_lvl[4]	11220	1		T5	554		T118	14		T174	16
rd_lvl[5]	7205	1		T118	2		T174	12		T329	741
rd_lvl[6]	7630	1		T330	1245		T118	6		T174	147
rd_lvl[7]	10279	1		T5	54		T41	1009		T330	645
rd_lvl[8]	8830	1		T41	571		T331	1190		T174	907
rd_lvl[9]	3611	1		T118	353		T331	230		T174	1
rd_lvl[10]	4321	1		T19	581		T118	713		T272	314
rd_lvl[11]	4553	1		T19	405		T113	455		T174	9
rd_lvl[12]	5032	1		T8	628		T113	401		T332	250
rd_lvl[13]	4948	1		T8	230		T118	14		T333	566
rd_lvl[14]	3753	1		T19	2		T334	533		T333	386
rd_lvl[15]	4798	1		T334	477		T119	407		T335	301