Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287930	1		T2	7968		T3	1		T4	1
all_pins[1]	287930	1		T2	7968		T3	1		T4	1
all_pins[2]	287930	1		T2	7968		T3	1		T4	1
all_pins[3]	287930	1		T2	7968		T3	1		T4	1
all_pins[4]	287930	1		T2	7968		T3	1		T4	1
all_pins[5]	287930	1		T2	7968		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1397437	1		T2	38818		T3	6		T4	6
values[0x1]	330143	1		T2	8990		T5	3236		T6	5030
transitions[0x0=>0x1]	309739	1		T2	8990		T5	3174		T6	5030
transitions[0x1=>0x0]	309742	1		T2	8990		T5	3174		T6	5030

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	229180	1		T2	5706		T3	1		T4	1
all_pins[0]	values[0x1]	58750	1		T2	2262		T6	4024		T116	2512
all_pins[0]	transitions[0x0=>0x1]	58738	1		T2	2262		T6	4024		T116	2512
all_pins[0]	transitions[0x1=>0x0]	60909	1		T2	5705		T116	3200		T117	2464
all_pins[1]	values[0x0]	227009	1		T2	2263		T3	1		T4	1
all_pins[1]	values[0x1]	60921	1		T2	5705		T116	3200		T117	2464
all_pins[1]	transitions[0x0=>0x1]	60916	1		T2	5705		T116	3200		T117	2464
all_pins[1]	transitions[0x1=>0x0]	7418	1		T19	2		T208	1		T209	4
all_pins[2]	values[0x0]	280507	1		T2	7968		T3	1		T4	1
all_pins[2]	values[0x1]	7423	1		T19	2		T208	1		T209	4
all_pins[2]	transitions[0x0=>0x1]	4953	1		T19	2		T208	1		T209	3
all_pins[2]	transitions[0x1=>0x0]	116046	1		T5	2104		T8	858		T41	1580
all_pins[3]	values[0x0]	169414	1		T2	7968		T3	1		T4	1
all_pins[3]	values[0x1]	118516	1		T5	2104		T8	858		T41	1580
all_pins[3]	transitions[0x0=>0x1]	100623	1		T5	2042		T8	858		T41	1580
all_pins[3]	transitions[0x1=>0x0]	66602	1		T2	1023		T5	1070		T6	1006
all_pins[4]	values[0x0]	203435	1		T2	6945		T3	1		T4	1
all_pins[4]	values[0x1]	84495	1		T2	1023		T5	1132		T6	1006
all_pins[4]	transitions[0x0=>0x1]	84483	1		T2	1023		T5	1132		T6	1006
all_pins[4]	transitions[0x1=>0x0]	26	1		T210	5		T296	1		T253	3
all_pins[5]	values[0x0]	287892	1		T2	7968		T3	1		T4	1
all_pins[5]	values[0x1]	38	1		T208	2		T210	5		T296	3
all_pins[5]	transitions[0x0=>0x1]	26	1		T208	2		T210	3		T296	2
all_pins[5]	transitions[0x1=>0x0]	58741	1		T2	2262		T6	4024		T116	2512