Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99	1		T261	4		T208	7		T209	7
all_values[1]	99	1		T261	4		T208	7		T209	7
all_values[2]	99	1		T261	4		T208	7		T209	7
all_values[3]	99	1		T261	4		T208	7		T209	7
all_values[4]	99	1		T261	4		T208	7		T209	7
all_values[5]	99	1		T261	4		T208	7		T209	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	306	1		T261	12		T208	20		T209	19
auto[1]	288	1		T261	12		T208	22		T209	23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	227	1		T261	8		T208	19		T209	16
auto[1]	367	1		T261	16		T208	23		T209	26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	356	1		T261	14		T208	26		T209	27
auto[1]	238	1		T261	10		T208	16		T209	15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1		T208	2		T209	1		T210	3
all_values[0]	auto[0]	auto[0]	auto[1]	7	1		T209	1		T210	1		T297	1
all_values[0]	auto[0]	auto[1]	auto[0]	19	1		T208	1		T209	2		T296	2
all_values[0]	auto[0]	auto[1]	auto[1]	12	1		T261	1		T208	1		T210	1
all_values[0]	auto[1]	auto[0]	auto[1]	17	1		T261	2		T208	1		T209	1
all_values[0]	auto[1]	auto[1]	auto[1]	19	1		T261	1		T208	2		T209	2
all_values[1]	auto[0]	auto[0]	auto[0]	18	1		T296	3		T295	2		T250	2
all_values[1]	auto[0]	auto[0]	auto[1]	9	1		T209	3		T250	1		T253	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T261	2		T208	2		T209	1
all_values[1]	auto[0]	auto[1]	auto[1]	10	1		T261	1		T209	1		T210	1
all_values[1]	auto[1]	auto[0]	auto[1]	23	1		T208	2		T209	2		T210	4
all_values[1]	auto[1]	auto[1]	auto[1]	18	1		T261	1		T208	3		T210	2
all_values[2]	auto[0]	auto[0]	auto[0]	27	1		T208	3		T209	1		T210	2
all_values[2]	auto[0]	auto[0]	auto[1]	10	1		T261	2		T210	1		T250	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T208	2		T210	2		T295	1
all_values[2]	auto[0]	auto[1]	auto[1]	8	1		T209	3		T253	1		T298	1
all_values[2]	auto[1]	auto[0]	auto[1]	22	1		T261	2		T208	1		T210	2
all_values[2]	auto[1]	auto[1]	auto[1]	16	1		T208	1		T209	3		T296	1
all_values[3]	auto[0]	auto[0]	auto[0]	17	1		T208	2		T253	4		T280	2
all_values[3]	auto[0]	auto[0]	auto[1]	10	1		T209	1		T210	1		T296	1
all_values[3]	auto[0]	auto[1]	auto[0]	18	1		T261	2		T208	2		T209	1
all_values[3]	auto[0]	auto[1]	auto[1]	13	1		T208	1		T209	2		T295	1
all_values[3]	auto[1]	auto[0]	auto[1]	20	1		T208	1		T209	2		T210	3
all_values[3]	auto[1]	auto[1]	auto[1]	21	1		T261	2		T208	1		T209	1
all_values[4]	auto[0]	auto[0]	auto[0]	11	1		T208	1		T209	2		T210	1
all_values[4]	auto[0]	auto[0]	auto[1]	11	1		T208	1		T296	1		T295	2
all_values[4]	auto[0]	auto[1]	auto[0]	22	1		T208	1		T209	3		T210	4
all_values[4]	auto[0]	auto[1]	auto[1]	15	1		T261	2		T208	2		T210	1
all_values[4]	auto[1]	auto[0]	auto[1]	28	1		T261	2		T208	2		T210	1
all_values[4]	auto[1]	auto[1]	auto[1]	12	1		T209	2		T296	1		T295	1
all_values[5]	auto[0]	auto[0]	auto[0]	23	1		T261	4		T208	2		T209	4
all_values[5]	auto[0]	auto[0]	auto[1]	6	1		T295	1		T253	1		T298	1
all_values[5]	auto[0]	auto[1]	auto[0]	10	1		T208	1		T209	1		T250	2
all_values[5]	auto[0]	auto[1]	auto[1]	18	1		T208	2		T210	2		T296	1
all_values[5]	auto[1]	auto[0]	auto[1]	22	1		T208	2		T209	1		T295	2
all_values[5]	auto[1]	auto[1]	auto[1]	20	1		T209	1		T210	3		T296	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal