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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.34 93.95 98.95 90.48 97.21 98.31 97.84


Total test records in report: 944
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T764 /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.4270117959 Feb 07 01:50:48 PM PST 24 Feb 07 01:51:23 PM PST 24 92374400 ps
T765 /workspace/coverage/default/17.flash_ctrl_connect.1252975608 Feb 07 01:52:13 PM PST 24 Feb 07 01:52:29 PM PST 24 17068200 ps
T766 /workspace/coverage/default/4.flash_ctrl_smoke_hw.1075945234 Feb 07 01:48:43 PM PST 24 Feb 07 01:49:10 PM PST 24 111897000 ps
T767 /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2935599017 Feb 07 01:48:01 PM PST 24 Feb 07 01:48:20 PM PST 24 48482000 ps
T768 /workspace/coverage/default/69.flash_ctrl_connect.1584238054 Feb 07 01:56:11 PM PST 24 Feb 07 01:56:28 PM PST 24 28792200 ps
T769 /workspace/coverage/default/63.flash_ctrl_otp_reset.1933511095 Feb 07 01:56:02 PM PST 24 Feb 07 01:58:18 PM PST 24 193528300 ps
T770 /workspace/coverage/default/12.flash_ctrl_mp_regions.3197527176 Feb 07 01:50:57 PM PST 24 Feb 07 01:53:49 PM PST 24 22863355800 ps
T771 /workspace/coverage/default/14.flash_ctrl_rw.769925520 Feb 07 01:51:30 PM PST 24 Feb 07 02:00:12 PM PST 24 6990928900 ps
T772 /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3859135092 Feb 07 01:54:10 PM PST 24 Feb 07 01:56:35 PM PST 24 5771759100 ps
T773 /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1728727811 Feb 07 01:50:24 PM PST 24 Feb 07 01:53:25 PM PST 24 16127555300 ps
T774 /workspace/coverage/default/29.flash_ctrl_alert_test.2064594229 Feb 07 01:54:13 PM PST 24 Feb 07 01:54:27 PM PST 24 22825200 ps
T775 /workspace/coverage/default/23.flash_ctrl_prog_reset.633083421 Feb 07 01:53:20 PM PST 24 Feb 07 01:53:34 PM PST 24 19348800 ps
T776 /workspace/coverage/default/9.flash_ctrl_sec_info_access.1591132856 Feb 07 01:50:24 PM PST 24 Feb 07 01:51:46 PM PST 24 2397891800 ps
T777 /workspace/coverage/default/26.flash_ctrl_otp_reset.4200185982 Feb 07 01:53:39 PM PST 24 Feb 07 01:55:53 PM PST 24 41519300 ps
T302 /workspace/coverage/default/4.flash_ctrl_host_dir_rd.467345288 Feb 07 01:48:44 PM PST 24 Feb 07 01:49:23 PM PST 24 44748300 ps
T286 /workspace/coverage/default/1.flash_ctrl_erase_suspend.2296302507 Feb 07 01:47:16 PM PST 24 Feb 07 01:54:27 PM PST 24 4256235500 ps
T778 /workspace/coverage/default/10.flash_ctrl_invalid_op.1082844631 Feb 07 01:50:34 PM PST 24 Feb 07 01:51:51 PM PST 24 16121815800 ps
T779 /workspace/coverage/default/1.flash_ctrl_invalid_op.1588034489 Feb 07 01:47:27 PM PST 24 Feb 07 01:48:48 PM PST 24 2206065300 ps
T780 /workspace/coverage/default/2.flash_ctrl_rand_ops.3008029636 Feb 07 01:47:45 PM PST 24 Feb 07 01:50:50 PM PST 24 57553300 ps
T781 /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.977587366 Feb 07 01:51:57 PM PST 24 Feb 07 01:52:30 PM PST 24 588859900 ps
T211 /workspace/coverage/default/0.flash_ctrl_sec_cm.20463757 Feb 07 01:47:05 PM PST 24 Feb 07 03:06:13 PM PST 24 1664290700 ps
T782 /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2495566622 Feb 07 01:54:17 PM PST 24 Feb 07 01:57:58 PM PST 24 7727574500 ps
T783 /workspace/coverage/default/42.flash_ctrl_connect.597570573 Feb 07 01:55:22 PM PST 24 Feb 07 01:55:39 PM PST 24 116596000 ps
T784 /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3465366866 Feb 07 01:47:00 PM PST 24 Feb 07 01:47:16 PM PST 24 58087300 ps
T785 /workspace/coverage/default/14.flash_ctrl_wo.729355282 Feb 07 01:51:28 PM PST 24 Feb 07 01:55:02 PM PST 24 4983312400 ps
T786 /workspace/coverage/default/21.flash_ctrl_alert_test.2037822050 Feb 07 01:53:10 PM PST 24 Feb 07 01:53:27 PM PST 24 474672100 ps
T95 /workspace/coverage/default/1.flash_ctrl_rma_err.1161317816 Feb 07 01:47:33 PM PST 24 Feb 07 02:03:44 PM PST 24 61290824800 ps
T787 /workspace/coverage/default/13.flash_ctrl_connect.2813073841 Feb 07 01:51:38 PM PST 24 Feb 07 01:51:54 PM PST 24 45209900 ps
T788 /workspace/coverage/default/25.flash_ctrl_otp_reset.2902693936 Feb 07 01:53:27 PM PST 24 Feb 07 01:55:44 PM PST 24 38428400 ps
T789 /workspace/coverage/default/1.flash_ctrl_serr_counter.2471868386 Feb 07 01:47:16 PM PST 24 Feb 07 01:48:30 PM PST 24 12271061900 ps
T790 /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1648930071 Feb 07 01:51:40 PM PST 24 Feb 07 01:52:32 PM PST 24 10053513900 ps
T791 /workspace/coverage/default/4.flash_ctrl_rw_evict.68419965 Feb 07 01:48:57 PM PST 24 Feb 07 01:49:28 PM PST 24 41193400 ps
T792 /workspace/coverage/default/44.flash_ctrl_alert_test.3004787302 Feb 07 01:55:34 PM PST 24 Feb 07 01:55:49 PM PST 24 136558900 ps
T793 /workspace/coverage/default/14.flash_ctrl_smoke.293148462 Feb 07 01:51:23 PM PST 24 Feb 07 01:53:28 PM PST 24 58256900 ps
T794 /workspace/coverage/default/26.flash_ctrl_prog_reset.2032622806 Feb 07 01:53:39 PM PST 24 Feb 07 01:53:54 PM PST 24 66146100 ps
T795 /workspace/coverage/default/2.flash_ctrl_invalid_op.3110907588 Feb 07 01:48:03 PM PST 24 Feb 07 01:49:14 PM PST 24 1703597300 ps
T796 /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1086762952 Feb 07 01:50:25 PM PST 24 Feb 07 01:52:51 PM PST 24 22751960300 ps
T797 /workspace/coverage/default/1.flash_ctrl_mp_regions.1188772672 Feb 07 01:47:14 PM PST 24 Feb 07 01:53:21 PM PST 24 30587111700 ps
T798 /workspace/coverage/default/35.flash_ctrl_connect.2776250436 Feb 07 01:54:41 PM PST 24 Feb 07 01:54:58 PM PST 24 74681100 ps
T799 /workspace/coverage/default/9.flash_ctrl_prog_reset.64513123 Feb 07 01:50:30 PM PST 24 Feb 07 01:50:45 PM PST 24 21452400 ps
T800 /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.693403965 Feb 07 01:52:12 PM PST 24 Feb 07 01:52:43 PM PST 24 151625200 ps
T801 /workspace/coverage/default/56.flash_ctrl_connect.2237234913 Feb 07 01:55:59 PM PST 24 Feb 07 01:56:13 PM PST 24 50035000 ps
T802 /workspace/coverage/default/16.flash_ctrl_rand_ops.1454128802 Feb 07 01:51:54 PM PST 24 Feb 07 02:02:34 PM PST 24 455772200 ps
T803 /workspace/coverage/default/19.flash_ctrl_smoke.3434438972 Feb 07 01:52:39 PM PST 24 Feb 07 01:54:46 PM PST 24 22463700 ps
T804 /workspace/coverage/default/12.flash_ctrl_prog_reset.2231554496 Feb 07 01:51:10 PM PST 24 Feb 07 01:51:27 PM PST 24 30781800 ps
T805 /workspace/coverage/default/16.flash_ctrl_rw.311071589 Feb 07 01:51:58 PM PST 24 Feb 07 02:00:19 PM PST 24 3546468900 ps
T806 /workspace/coverage/default/28.flash_ctrl_smoke.2452047387 Feb 07 01:53:50 PM PST 24 Feb 07 01:57:34 PM PST 24 39050500 ps
T807 /workspace/coverage/default/17.flash_ctrl_re_evict.3995703233 Feb 07 01:52:16 PM PST 24 Feb 07 01:52:47 PM PST 24 82701300 ps
T808 /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.980838064 Feb 07 01:49:29 PM PST 24 Feb 07 01:55:59 PM PST 24 51200426900 ps
T32 /workspace/coverage/default/1.flash_ctrl_access_after_disable.3093798241 Feb 07 01:47:28 PM PST 24 Feb 07 01:47:42 PM PST 24 13325100 ps
T809 /workspace/coverage/default/1.flash_ctrl_smoke.3268359494 Feb 07 01:47:12 PM PST 24 Feb 07 01:48:28 PM PST 24 26913000 ps
T810 /workspace/coverage/default/7.flash_ctrl_rw.3027803882 Feb 07 01:49:35 PM PST 24 Feb 07 01:59:21 PM PST 24 31474421500 ps
T177 /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1402570454 Feb 07 01:48:01 PM PST 24 Feb 07 01:48:21 PM PST 24 15392500 ps
T811 /workspace/coverage/default/27.flash_ctrl_alert_test.1696951344 Feb 07 01:53:57 PM PST 24 Feb 07 01:54:16 PM PST 24 99781700 ps
T812 /workspace/coverage/default/74.flash_ctrl_connect.2375418468 Feb 07 01:56:17 PM PST 24 Feb 07 01:56:31 PM PST 24 86463500 ps
T11 /workspace/coverage/default/1.flash_ctrl_wr_intg.804403670 Feb 07 01:47:42 PM PST 24 Feb 07 01:47:59 PM PST 24 677333800 ps
T813 /workspace/coverage/default/69.flash_ctrl_otp_reset.3577390749 Feb 07 01:56:14 PM PST 24 Feb 07 01:58:26 PM PST 24 217721500 ps
T324 /workspace/coverage/default/3.flash_ctrl_full_mem_access.2454151125 Feb 07 01:48:17 PM PST 24 Feb 07 02:30:21 PM PST 24 186798449700 ps
T814 /workspace/coverage/default/5.flash_ctrl_smoke.2687497872 Feb 07 01:48:53 PM PST 24 Feb 07 01:50:11 PM PST 24 81504000 ps
T815 /workspace/coverage/default/18.flash_ctrl_wo.1844037573 Feb 07 01:52:25 PM PST 24 Feb 07 01:55:34 PM PST 24 4364206900 ps
T816 /workspace/coverage/default/40.flash_ctrl_sec_info_access.1302524535 Feb 07 01:55:17 PM PST 24 Feb 07 01:56:35 PM PST 24 4547888800 ps
T817 /workspace/coverage/default/32.flash_ctrl_sec_info_access.1866533857 Feb 07 01:54:27 PM PST 24 Feb 07 01:55:28 PM PST 24 1792093200 ps
T818 /workspace/coverage/default/19.flash_ctrl_alert_test.2293055725 Feb 07 01:53:00 PM PST 24 Feb 07 01:53:14 PM PST 24 168920200 ps
T819 /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3349751513 Feb 07 01:54:20 PM PST 24 Feb 07 01:54:53 PM PST 24 76037100 ps
T820 /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2070107807 Feb 07 01:48:52 PM PST 24 Feb 07 01:49:12 PM PST 24 85152100 ps
T821 /workspace/coverage/default/2.flash_ctrl_phy_arb.4021990512 Feb 07 01:47:43 PM PST 24 Feb 07 01:54:12 PM PST 24 2861173100 ps
T822 /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3478475402 Feb 07 01:55:16 PM PST 24 Feb 07 01:58:51 PM PST 24 20799783000 ps
T823 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3348175160 Feb 07 01:48:42 PM PST 24 Feb 07 01:49:05 PM PST 24 135507500 ps
T824 /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2356987406 Feb 07 01:50:21 PM PST 24 Feb 07 01:50:36 PM PST 24 26562900 ps
T825 /workspace/coverage/default/17.flash_ctrl_smoke.4210901495 Feb 07 01:52:06 PM PST 24 Feb 07 01:54:59 PM PST 24 132587800 ps
T826 /workspace/coverage/default/4.flash_ctrl_prog_reset.3435718764 Feb 07 01:48:56 PM PST 24 Feb 07 01:49:10 PM PST 24 37434900 ps
T827 /workspace/coverage/default/35.flash_ctrl_smoke.3625722197 Feb 07 01:54:37 PM PST 24 Feb 07 01:57:05 PM PST 24 97403200 ps
T828 /workspace/coverage/default/67.flash_ctrl_connect.3132728114 Feb 07 01:56:05 PM PST 24 Feb 07 01:56:20 PM PST 24 58301100 ps
T829 /workspace/coverage/default/28.flash_ctrl_intr_rd.1766182498 Feb 07 01:53:54 PM PST 24 Feb 07 01:56:41 PM PST 24 3961242000 ps
T830 /workspace/coverage/default/18.flash_ctrl_rand_ops.1495180232 Feb 07 01:52:24 PM PST 24 Feb 07 02:00:45 PM PST 24 234129100 ps
T831 /workspace/coverage/default/2.flash_ctrl_smoke.2857113585 Feb 07 01:47:31 PM PST 24 Feb 07 01:49:35 PM PST 24 60446200 ps
T832 /workspace/coverage/default/48.flash_ctrl_smoke.569557002 Feb 07 01:55:44 PM PST 24 Feb 07 01:58:10 PM PST 24 59103600 ps
T833 /workspace/coverage/default/2.flash_ctrl_stress_all.174049770 Feb 07 01:47:54 PM PST 24 Feb 07 02:00:26 PM PST 24 628744200 ps
T834 /workspace/coverage/default/61.flash_ctrl_connect.2716858956 Feb 07 01:56:04 PM PST 24 Feb 07 01:56:21 PM PST 24 14455300 ps
T189 /workspace/coverage/default/12.flash_ctrl_rw_evict.2272937096 Feb 07 01:51:07 PM PST 24 Feb 07 01:51:42 PM PST 24 47447700 ps
T835 /workspace/coverage/default/38.flash_ctrl_sec_info_access.878157677 Feb 07 01:55:20 PM PST 24 Feb 07 01:56:25 PM PST 24 1181761400 ps
T836 /workspace/coverage/default/1.flash_ctrl_alert_test.2058992213 Feb 07 01:47:43 PM PST 24 Feb 07 01:47:58 PM PST 24 227212400 ps
T837 /workspace/coverage/default/26.flash_ctrl_disable.106141811 Feb 07 01:53:40 PM PST 24 Feb 07 01:54:03 PM PST 24 12300700 ps
T838 /workspace/coverage/default/22.flash_ctrl_smoke.1784387193 Feb 07 01:53:09 PM PST 24 Feb 07 01:55:35 PM PST 24 55256100 ps
T839 /workspace/coverage/default/0.flash_ctrl_ro.770721425 Feb 07 01:46:56 PM PST 24 Feb 07 01:48:20 PM PST 24 380489900 ps
T840 /workspace/coverage/default/0.flash_ctrl_error_mp.2138291388 Feb 07 01:46:58 PM PST 24 Feb 07 02:23:20 PM PST 24 14331811900 ps
T841 /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1488909307 Feb 07 01:48:45 PM PST 24 Feb 07 01:49:46 PM PST 24 10031457500 ps
T842 /workspace/coverage/default/33.flash_ctrl_smoke.3930171275 Feb 07 01:54:23 PM PST 24 Feb 07 01:56:51 PM PST 24 145021400 ps
T843 /workspace/coverage/default/5.flash_ctrl_phy_arb.3670912339 Feb 07 01:49:07 PM PST 24 Feb 07 01:53:07 PM PST 24 141870400 ps
T844 /workspace/coverage/default/7.flash_ctrl_rand_ops.1820097961 Feb 07 01:49:27 PM PST 24 Feb 07 02:08:32 PM PST 24 400055700 ps
T845 /workspace/coverage/default/14.flash_ctrl_prog_reset.2977321807 Feb 07 01:51:31 PM PST 24 Feb 07 01:51:48 PM PST 24 214169600 ps
T846 /workspace/coverage/default/23.flash_ctrl_intr_rd.3562067925 Feb 07 01:53:13 PM PST 24 Feb 07 01:55:53 PM PST 24 5475923200 ps
T847 /workspace/coverage/default/76.flash_ctrl_otp_reset.2877485475 Feb 07 01:56:19 PM PST 24 Feb 07 01:58:30 PM PST 24 318798500 ps
T848 /workspace/coverage/default/14.flash_ctrl_otp_reset.633082476 Feb 07 01:51:34 PM PST 24 Feb 07 01:53:28 PM PST 24 157186200 ps
T849 /workspace/coverage/default/17.flash_ctrl_rand_ops.3887573215 Feb 07 01:52:09 PM PST 24 Feb 07 02:07:32 PM PST 24 464374900 ps
T850 /workspace/coverage/default/4.flash_ctrl_fs_sup.4131170115 Feb 07 01:48:53 PM PST 24 Feb 07 01:49:28 PM PST 24 1166714200 ps
T851 /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.4123014994 Feb 07 01:49:33 PM PST 24 Feb 07 02:02:34 PM PST 24 40124999700 ps
T145 /workspace/coverage/default/3.flash_ctrl_mp_regions.2557808384 Feb 07 01:48:20 PM PST 24 Feb 07 01:56:24 PM PST 24 5882471700 ps
T852 /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3821368349 Feb 07 01:53:01 PM PST 24 Feb 07 01:56:36 PM PST 24 22085938100 ps
T853 /workspace/coverage/default/1.flash_ctrl_phy_arb.268278645 Feb 07 01:47:14 PM PST 24 Feb 07 01:53:04 PM PST 24 735077000 ps
T854 /workspace/coverage/default/16.flash_ctrl_phy_arb.3730941607 Feb 07 01:51:57 PM PST 24 Feb 07 01:55:16 PM PST 24 88892400 ps
T855 /workspace/coverage/default/5.flash_ctrl_ro_serr.3616492932 Feb 07 01:49:06 PM PST 24 Feb 07 01:51:01 PM PST 24 973518000 ps
T856 /workspace/coverage/default/6.flash_ctrl_re_evict.1702321598 Feb 07 01:49:28 PM PST 24 Feb 07 01:50:07 PM PST 24 247584300 ps
T857 /workspace/coverage/default/22.flash_ctrl_intr_rd.1585243029 Feb 07 01:53:08 PM PST 24 Feb 07 01:55:37 PM PST 24 1078046700 ps
T858 /workspace/coverage/default/22.flash_ctrl_disable.2715208377 Feb 07 01:53:06 PM PST 24 Feb 07 01:53:29 PM PST 24 15163000 ps
T859 /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3239361254 Feb 07 01:52:16 PM PST 24 Feb 07 01:53:40 PM PST 24 10017996800 ps
T860 /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1064233973 Feb 07 01:46:57 PM PST 24 Feb 07 02:01:52 PM PST 24 160184006100 ps
T861 /workspace/coverage/default/73.flash_ctrl_otp_reset.2019030218 Feb 07 01:56:13 PM PST 24 Feb 07 01:58:25 PM PST 24 249076900 ps
T301 /workspace/coverage/default/0.flash_ctrl_disable.125425165 Feb 07 01:47:06 PM PST 24 Feb 07 01:47:27 PM PST 24 19016300 ps
T862 /workspace/coverage/default/15.flash_ctrl_rw.2223115875 Feb 07 01:51:54 PM PST 24 Feb 07 02:00:58 PM PST 24 6449025900 ps
T863 /workspace/coverage/default/8.flash_ctrl_wo.1440996738 Feb 07 01:49:52 PM PST 24 Feb 07 01:52:28 PM PST 24 1879812100 ps
T864 /workspace/coverage/default/2.flash_ctrl_connect.2093371287 Feb 07 01:48:00 PM PST 24 Feb 07 01:48:20 PM PST 24 18751600 ps
T865 /workspace/coverage/default/33.flash_ctrl_alert_test.868544809 Feb 07 01:54:33 PM PST 24 Feb 07 01:54:47 PM PST 24 27779200 ps
T866 /workspace/coverage/default/7.flash_ctrl_prog_reset.700452008 Feb 07 01:49:49 PM PST 24 Feb 07 01:50:05 PM PST 24 36929900 ps
T867 /workspace/coverage/default/20.flash_ctrl_sec_info_access.753139453 Feb 07 01:53:09 PM PST 24 Feb 07 01:54:16 PM PST 24 5079932500 ps
T868 /workspace/coverage/default/51.flash_ctrl_connect.3421315048 Feb 07 01:55:51 PM PST 24 Feb 07 01:56:07 PM PST 24 15280800 ps
T869 /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4267960136 Feb 07 01:47:45 PM PST 24 Feb 07 01:48:34 PM PST 24 59965200 ps
T870 /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4131196819 Feb 07 01:49:16 PM PST 24 Feb 07 01:51:11 PM PST 24 10012311600 ps
T871 /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1299135122 Feb 07 01:47:33 PM PST 24 Feb 07 01:47:48 PM PST 24 44326800 ps
T872 /workspace/coverage/default/0.flash_ctrl_stress_all.1699891291 Feb 07 01:47:03 PM PST 24 Feb 07 01:50:43 PM PST 24 168146800 ps
T873 /workspace/coverage/default/12.flash_ctrl_wo.3773932073 Feb 07 01:51:09 PM PST 24 Feb 07 01:54:44 PM PST 24 4938938600 ps
T874 /workspace/coverage/default/37.flash_ctrl_rw_evict.3893291736 Feb 07 01:55:08 PM PST 24 Feb 07 01:55:39 PM PST 24 28806200 ps
T875 /workspace/coverage/default/3.flash_ctrl_serr_address.3147987436 Feb 07 01:48:20 PM PST 24 Feb 07 01:49:23 PM PST 24 1866666000 ps
T876 /workspace/coverage/default/22.flash_ctrl_connect.3916475342 Feb 07 01:53:15 PM PST 24 Feb 07 01:53:32 PM PST 24 176884500 ps
T877 /workspace/coverage/default/18.flash_ctrl_re_evict.3225847885 Feb 07 01:52:43 PM PST 24 Feb 07 01:53:22 PM PST 24 127128500 ps
T878 /workspace/coverage/default/21.flash_ctrl_otp_reset.799552464 Feb 07 01:53:09 PM PST 24 Feb 07 01:55:21 PM PST 24 37999300 ps
T879 /workspace/coverage/default/0.flash_ctrl_integrity.3671957763 Feb 07 01:47:13 PM PST 24 Feb 07 01:55:58 PM PST 24 11372093100 ps
T880 /workspace/coverage/default/0.flash_ctrl_connect.3020369519 Feb 07 01:47:02 PM PST 24 Feb 07 01:47:21 PM PST 24 19585500 ps
T881 /workspace/coverage/default/3.flash_ctrl_rand_ops.3722575222 Feb 07 01:48:14 PM PST 24 Feb 07 01:50:58 PM PST 24 100117200 ps
T882 /workspace/coverage/default/6.flash_ctrl_rw_serr.4127261003 Feb 07 01:49:30 PM PST 24 Feb 07 01:57:39 PM PST 24 2841524400 ps
T883 /workspace/coverage/default/3.flash_ctrl_rw_serr.1122154646 Feb 07 01:48:20 PM PST 24 Feb 07 01:58:24 PM PST 24 7445261300 ps
T884 /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1775244595 Feb 07 01:51:55 PM PST 24 Feb 07 01:52:10 PM PST 24 15730900 ps
T885 /workspace/coverage/default/21.flash_ctrl_connect.175609617 Feb 07 01:53:08 PM PST 24 Feb 07 01:53:25 PM PST 24 112565400 ps
T886 /workspace/coverage/default/4.flash_ctrl_oversize_error.3337707151 Feb 07 01:48:56 PM PST 24 Feb 07 01:51:50 PM PST 24 4462018100 ps
T887 /workspace/coverage/default/1.flash_ctrl_connect.1167718869 Feb 07 01:47:46 PM PST 24 Feb 07 01:48:04 PM PST 24 159021000 ps
T888 /workspace/coverage/default/13.flash_ctrl_wo.2154929147 Feb 07 01:51:19 PM PST 24 Feb 07 01:54:16 PM PST 24 3994985400 ps
T889 /workspace/coverage/default/5.flash_ctrl_rw.3902235106 Feb 07 01:49:09 PM PST 24 Feb 07 01:58:23 PM PST 24 8149591400 ps
T890 /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.37050678 Feb 07 01:51:20 PM PST 24 Feb 07 02:04:12 PM PST 24 160169587600 ps
T891 /workspace/coverage/default/10.flash_ctrl_phy_arb.3655986221 Feb 07 01:50:33 PM PST 24 Feb 07 01:57:53 PM PST 24 94143500 ps
T892 /workspace/coverage/default/3.flash_ctrl_rw_evict.2039485170 Feb 07 01:48:34 PM PST 24 Feb 07 01:49:07 PM PST 24 306223100 ps
T893 /workspace/coverage/default/9.flash_ctrl_rw.2787398516 Feb 07 01:50:20 PM PST 24 Feb 07 02:00:08 PM PST 24 7866757600 ps
T325 /workspace/coverage/default/2.flash_ctrl_mp_regions.1642749656 Feb 07 01:48:02 PM PST 24 Feb 07 01:57:09 PM PST 24 26475115000 ps
T894 /workspace/coverage/default/5.flash_ctrl_wo.1533201824 Feb 07 01:49:07 PM PST 24 Feb 07 01:52:33 PM PST 24 4782981200 ps
T895 /workspace/coverage/default/54.flash_ctrl_connect.1647074710 Feb 07 01:55:57 PM PST 24 Feb 07 01:56:13 PM PST 24 43420500 ps
T896 /workspace/coverage/default/12.flash_ctrl_sec_info_access.1167070844 Feb 07 01:51:07 PM PST 24 Feb 07 01:52:17 PM PST 24 3465506900 ps
T897 /workspace/coverage/default/9.flash_ctrl_wo.4169431879 Feb 07 01:50:21 PM PST 24 Feb 07 01:53:27 PM PST 24 8024414100 ps
T898 /workspace/coverage/default/41.flash_ctrl_connect.2381910192 Feb 07 01:55:23 PM PST 24 Feb 07 01:55:37 PM PST 24 41156400 ps
T899 /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2115515527 Feb 07 01:52:38 PM PST 24 Feb 07 01:52:52 PM PST 24 48176100 ps
T900 /workspace/coverage/default/1.flash_ctrl_smoke_hw.21174911 Feb 07 01:47:14 PM PST 24 Feb 07 01:47:41 PM PST 24 59544500 ps
T901 /workspace/coverage/default/5.flash_ctrl_intr_wr.3450003871 Feb 07 01:49:03 PM PST 24 Feb 07 01:50:58 PM PST 24 8694870800 ps
T902 /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1117609470 Feb 07 01:49:33 PM PST 24 Feb 07 01:51:40 PM PST 24 3427315400 ps
T903 /workspace/coverage/default/18.flash_ctrl_rw.1730633127 Feb 07 01:52:24 PM PST 24 Feb 07 02:01:40 PM PST 24 8715688000 ps
T904 /workspace/coverage/default/11.flash_ctrl_phy_arb.362887643 Feb 07 01:50:45 PM PST 24 Feb 07 01:51:59 PM PST 24 109209000 ps
T905 /workspace/coverage/default/43.flash_ctrl_connect.1203119476 Feb 07 01:55:29 PM PST 24 Feb 07 01:55:46 PM PST 24 25217100 ps
T906 /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.702340718 Feb 07 01:53:46 PM PST 24 Feb 07 01:57:23 PM PST 24 9248132100 ps
T907 /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3642194804 Feb 07 01:50:04 PM PST 24 Feb 07 01:50:34 PM PST 24 41834900 ps
T91 /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3785381720 Feb 07 01:46:59 PM PST 24 Feb 07 02:17:41 PM PST 24 324947632000 ps
T908 /workspace/coverage/default/4.flash_ctrl_phy_arb.3944594905 Feb 07 01:48:41 PM PST 24 Feb 07 01:55:09 PM PST 24 753837500 ps
T909 /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3199702844 Feb 07 01:51:21 PM PST 24 Feb 07 01:53:32 PM PST 24 1489244800 ps
T910 /workspace/coverage/default/48.flash_ctrl_alert_test.3555355147 Feb 07 01:55:51 PM PST 24 Feb 07 01:56:06 PM PST 24 58402400 ps
T911 /workspace/coverage/default/7.flash_ctrl_fetch_code.3474599603 Feb 07 01:49:36 PM PST 24 Feb 07 01:49:59 PM PST 24 109422500 ps
T912 /workspace/coverage/default/39.flash_ctrl_smoke.2637109843 Feb 07 01:55:17 PM PST 24 Feb 07 01:56:09 PM PST 24 19865000 ps
T913 /workspace/coverage/default/23.flash_ctrl_smoke.3623237454 Feb 07 01:53:08 PM PST 24 Feb 07 01:54:47 PM PST 24 18868000 ps
T914 /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1800555259 Feb 07 01:51:55 PM PST 24 Feb 07 01:52:09 PM PST 24 18816600 ps
T915 /workspace/coverage/default/39.flash_ctrl_alert_test.1004486664 Feb 07 01:55:19 PM PST 24 Feb 07 01:55:35 PM PST 24 106957300 ps
T916 /workspace/coverage/default/10.flash_ctrl_alert_test.2689277264 Feb 07 01:50:45 PM PST 24 Feb 07 01:51:04 PM PST 24 38740700 ps
T917 /workspace/coverage/default/14.flash_ctrl_intr_rd.3684444336 Feb 07 01:51:30 PM PST 24 Feb 07 01:54:11 PM PST 24 1225618400 ps
T918 /workspace/coverage/default/1.flash_ctrl_ro.1791338680 Feb 07 01:47:35 PM PST 24 Feb 07 01:49:38 PM PST 24 476001300 ps
T919 /workspace/coverage/default/21.flash_ctrl_intr_rd.6785105 Feb 07 01:53:11 PM PST 24 Feb 07 01:55:49 PM PST 24 7003306300 ps
T920 /workspace/coverage/default/10.flash_ctrl_rw.1122033984 Feb 07 01:50:35 PM PST 24 Feb 07 01:59:08 PM PST 24 11087649000 ps
T921 /workspace/coverage/default/22.flash_ctrl_sec_info_access.1171736984 Feb 07 01:53:15 PM PST 24 Feb 07 01:54:15 PM PST 24 508872000 ps
T922 /workspace/coverage/default/1.flash_ctrl_rw_serr.3421642280 Feb 07 01:47:18 PM PST 24 Feb 07 01:56:50 PM PST 24 14116627600 ps
T923 /workspace/coverage/default/8.flash_ctrl_rw_serr.1231788680 Feb 07 01:49:55 PM PST 24 Feb 07 02:00:09 PM PST 24 7886940700 ps
T924 /workspace/coverage/default/4.flash_ctrl_derr_detect.349787358 Feb 07 01:48:52 PM PST 24 Feb 07 01:50:40 PM PST 24 368321700 ps
T925 /workspace/coverage/default/47.flash_ctrl_alert_test.3181480953 Feb 07 01:55:40 PM PST 24 Feb 07 01:55:54 PM PST 24 27237800 ps
T926 /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.489873649 Feb 07 01:51:39 PM PST 24 Feb 07 01:51:54 PM PST 24 28968400 ps
T927 /workspace/coverage/default/8.flash_ctrl_error_prog_win.2884104910 Feb 07 01:50:05 PM PST 24 Feb 07 02:03:31 PM PST 24 1575729900 ps
T928 /workspace/coverage/default/36.flash_ctrl_alert_test.1566762349 Feb 07 01:54:52 PM PST 24 Feb 07 01:55:07 PM PST 24 159668800 ps
T929 /workspace/coverage/default/34.flash_ctrl_alert_test.3719879848 Feb 07 01:54:31 PM PST 24 Feb 07 01:54:46 PM PST 24 133252000 ps
T930 /workspace/coverage/default/2.flash_ctrl_intr_wr.917845128 Feb 07 01:47:51 PM PST 24 Feb 07 01:49:43 PM PST 24 7699330600 ps
T931 /workspace/coverage/default/9.flash_ctrl_ro_serr.1605494434 Feb 07 01:50:22 PM PST 24 Feb 07 01:52:23 PM PST 24 1081523500 ps
T932 /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.790644347 Feb 07 01:47:05 PM PST 24 Feb 07 01:49:01 PM PST 24 1678652500 ps
T933 /workspace/coverage/default/6.flash_ctrl_connect.4113842348 Feb 07 01:49:28 PM PST 24 Feb 07 01:49:45 PM PST 24 76570700 ps
T934 /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1297239118 Feb 07 01:49:19 PM PST 24 Feb 07 01:49:50 PM PST 24 108329000 ps
T935 /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.333626110 Feb 07 01:55:22 PM PST 24 Feb 07 01:56:25 PM PST 24 688312800 ps
T936 /workspace/coverage/default/28.flash_ctrl_alert_test.2370226638 Feb 07 01:53:58 PM PST 24 Feb 07 01:54:16 PM PST 24 46068800 ps
T937 /workspace/coverage/default/24.flash_ctrl_sec_info_access.2802325712 Feb 07 01:53:30 PM PST 24 Feb 07 01:54:48 PM PST 24 32410710500 ps
T938 /workspace/coverage/default/1.flash_ctrl_prog_reset.1099047340 Feb 07 01:47:16 PM PST 24 Feb 07 01:47:30 PM PST 24 29716400 ps
T939 /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3480921236 Feb 07 01:49:21 PM PST 24 Feb 07 01:51:14 PM PST 24 1555634400 ps
T940 /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3352480466 Feb 07 01:49:27 PM PST 24 Feb 07 01:49:41 PM PST 24 26365400 ps
T941 /workspace/coverage/default/30.flash_ctrl_rw_evict.4268021023 Feb 07 01:54:09 PM PST 24 Feb 07 01:54:44 PM PST 24 54557100 ps
T942 /workspace/coverage/default/31.flash_ctrl_alert_test.312038639 Feb 07 01:54:19 PM PST 24 Feb 07 01:54:34 PM PST 24 35320600 ps
T943 /workspace/coverage/default/12.flash_ctrl_connect.218106319 Feb 07 01:51:07 PM PST 24 Feb 07 01:51:26 PM PST 24 49354000 ps
T944 /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.872631796 Feb 07 01:51:39 PM PST 24 Feb 07 01:53:56 PM PST 24 10012168600 ps

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.3569905432
Short name T7
Test name
Test status
Simulation time 2143410200 ps
CPU time 578.73 seconds
Started Feb 07 01:52:02 PM PST 24
Finished Feb 07 02:01:42 PM PST 24
Peak memory 259904 kb
Host smart-29ba2fc4-5af2-4aab-85fb-343e6ca66d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569905432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3569905432
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1661322628
Short name T200
Test name
Test status
Simulation time 2566838700 ps
CPU time 763.98 seconds
Started Feb 07 12:43:20 PM PST 24
Finished Feb 07 12:56:11 PM PST 24
Peak memory 261248 kb
Host smart-99488eb8-0e3d-466e-b32d-bef785432142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661322628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1661322628
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3862465140
Short name T51
Test name
Test status
Simulation time 334663276200 ps
CPU time 1686.48 seconds
Started Feb 07 01:47:46 PM PST 24
Finished Feb 07 02:15:54 PM PST 24
Peak memory 258464 kb
Host smart-cd2079f4-2a18-4128-a985-6b2331df585d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862465140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3862465140
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2192172662
Short name T5
Test name
Test status
Simulation time 1349919100 ps
CPU time 166.19 seconds
Started Feb 07 01:55:07 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 288752 kb
Host smart-31c8ed59-3608-4a08-866a-4f4d85ddf204
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192172662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2192172662
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.96281488
Short name T45
Test name
Test status
Simulation time 10854341300 ps
CPU time 339.84 seconds
Started Feb 07 01:48:37 PM PST 24
Finished Feb 07 01:54:17 PM PST 24
Peak memory 271884 kb
Host smart-8b51fc83-d79e-417d-82d8-c64464668dcc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96281488 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.96281488
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2266014028
Short name T15
Test name
Test status
Simulation time 1463295000 ps
CPU time 4659.89 seconds
Started Feb 07 01:48:40 PM PST 24
Finished Feb 07 03:06:22 PM PST 24
Peak memory 283204 kb
Host smart-19c9eee2-fd2f-4840-9363-99bd96a6e705
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266014028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2266014028
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.3380356663
Short name T38
Test name
Test status
Simulation time 16833256100 ps
CPU time 605.05 seconds
Started Feb 07 01:48:01 PM PST 24
Finished Feb 07 01:58:12 PM PST 24
Peak memory 327052 kb
Host smart-24c4f8bf-97e2-4875-b598-a8812cd020cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380356663 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.3380356663
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.226334755
Short name T47
Test name
Test status
Simulation time 11925266300 ps
CPU time 73.63 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:48:33 PM PST 24
Peak memory 259180 kb
Host smart-aa8dfab3-9ead-407f-8983-bb7e09c6e772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226334755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.226334755
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1195539653
Short name T3
Test name
Test status
Simulation time 16304100 ps
CPU time 13.6 seconds
Started Feb 07 01:50:58 PM PST 24
Finished Feb 07 01:51:12 PM PST 24
Peak memory 264076 kb
Host smart-9a8437aa-c517-4f62-9e5e-3ddcfc8df531
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195539653 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1195539653
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.1772257482
Short name T46
Test name
Test status
Simulation time 1426174000 ps
CPU time 363.33 seconds
Started Feb 07 01:46:54 PM PST 24
Finished Feb 07 01:52:58 PM PST 24
Peak memory 259536 kb
Host smart-96bf6511-a83e-474b-8429-c294d29f825f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772257482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.1772257482
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2333731707
Short name T234
Test name
Test status
Simulation time 63044300 ps
CPU time 19.39 seconds
Started Feb 07 12:43:21 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 263816 kb
Host smart-cabd659b-990d-4ae5-9ce5-b3545842b4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333731707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
333731707
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3635494122
Short name T535
Test name
Test status
Simulation time 36463700 ps
CPU time 133.59 seconds
Started Feb 07 01:52:07 PM PST 24
Finished Feb 07 01:54:21 PM PST 24
Peak memory 258112 kb
Host smart-dff4c2eb-1059-4812-972d-c60e4f923beb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635494122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3635494122
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3052464195
Short name T208
Test name
Test status
Simulation time 44515300 ps
CPU time 13.68 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:43:48 PM PST 24
Peak memory 262032 kb
Host smart-c45d3c8b-baba-4176-9705-f6576a81c341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052464195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3052464195
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3075886540
Short name T93
Test name
Test status
Simulation time 10031986600 ps
CPU time 63.1 seconds
Started Feb 07 01:47:42 PM PST 24
Finished Feb 07 01:48:46 PM PST 24
Peak memory 292436 kb
Host smart-f9105bf7-89ac-49e9-b4e0-5548fe93001d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075886540 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3075886540
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.438642765
Short name T114
Test name
Test status
Simulation time 23125832900 ps
CPU time 132.06 seconds
Started Feb 07 01:51:40 PM PST 24
Finished Feb 07 01:53:53 PM PST 24
Peak memory 258560 kb
Host smart-f81e0d48-6e28-4c3c-bde6-4162e04927c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438642765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.438642765
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2120469091
Short name T62
Test name
Test status
Simulation time 77835600 ps
CPU time 133.32 seconds
Started Feb 07 01:55:24 PM PST 24
Finished Feb 07 01:57:38 PM PST 24
Peak memory 260708 kb
Host smart-f6a85b32-61e7-41d7-867c-f0aa9119e97c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120469091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2120469091
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1744541138
Short name T19
Test name
Test status
Simulation time 76161399500 ps
CPU time 207.99 seconds
Started Feb 07 01:54:00 PM PST 24
Finished Feb 07 01:57:34 PM PST 24
Peak memory 291708 kb
Host smart-f541c635-ccb4-47ce-8309-698226442c41
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744541138 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1744541138
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.439067379
Short name T14
Test name
Test status
Simulation time 39542900 ps
CPU time 13.54 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:47:14 PM PST 24
Peak memory 264136 kb
Host smart-f9fdac6f-c840-425c-9f49-c27011ed978f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439067379 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.439067379
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2020874060
Short name T65
Test name
Test status
Simulation time 10019092700 ps
CPU time 148.34 seconds
Started Feb 07 01:48:52 PM PST 24
Finished Feb 07 01:51:22 PM PST 24
Peak memory 264000 kb
Host smart-7790348d-8fcd-41d2-85ff-21c94ae57496
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020874060 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2020874060
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1200146584
Short name T287
Test name
Test status
Simulation time 16626912700 ps
CPU time 76.43 seconds
Started Feb 07 01:48:35 PM PST 24
Finished Feb 07 01:49:52 PM PST 24
Peak memory 262820 kb
Host smart-9f3495c7-b8df-43a4-a9e8-06841b61cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200146584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1200146584
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.796104892
Short name T84
Test name
Test status
Simulation time 39748323300 ps
CPU time 822.89 seconds
Started Feb 07 01:47:59 PM PST 24
Finished Feb 07 02:01:48 PM PST 24
Peak memory 259696 kb
Host smart-e041a4cd-32fc-4928-bc8f-2a323c479ec5
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796104892 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.796104892
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1995803755
Short name T78
Test name
Test status
Simulation time 106717000 ps
CPU time 131.52 seconds
Started Feb 07 01:53:55 PM PST 24
Finished Feb 07 01:56:12 PM PST 24
Peak memory 258436 kb
Host smart-e11095e9-00e5-404d-b8db-53e67098d9f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995803755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1995803755
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2599271225
Short name T56
Test name
Test status
Simulation time 675521500 ps
CPU time 70.02 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:49:45 PM PST 24
Peak memory 258036 kb
Host smart-c8cb8e7b-6ae2-4944-9373-8094bda0db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599271225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2599271225
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3785381720
Short name T91
Test name
Test status
Simulation time 324947632000 ps
CPU time 1839.27 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 264040 kb
Host smart-264eac4a-a845-4eaf-81f4-b44b0a0236c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785381720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.3785381720
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.4258876919
Short name T60
Test name
Test status
Simulation time 10303836500 ps
CPU time 74.92 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:48:12 PM PST 24
Peak memory 258068 kb
Host smart-aef62216-3bf9-4a52-84df-9925e9dc66cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258876919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.4258876919
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2105404514
Short name T133
Test name
Test status
Simulation time 1016877500 ps
CPU time 91.23 seconds
Started Feb 07 01:52:49 PM PST 24
Finished Feb 07 01:54:21 PM PST 24
Peak memory 258208 kb
Host smart-173c3c68-d7ea-4492-a0d5-9157bd23c269
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105404514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
105404514
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1331186182
Short name T33
Test name
Test status
Simulation time 43992100 ps
CPU time 31.88 seconds
Started Feb 07 01:55:07 PM PST 24
Finished Feb 07 01:55:40 PM PST 24
Peak memory 272400 kb
Host smart-0002fd61-089e-4175-b1a0-6ce30754aa36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331186182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1331186182
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3300685424
Short name T30
Test name
Test status
Simulation time 34770631500 ps
CPU time 428.37 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:54:05 PM PST 24
Peak memory 272876 kb
Host smart-7bd7d602-b268-468e-9bac-51c24a8d4246
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300685424 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3300685424
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.1597739433
Short name T112
Test name
Test status
Simulation time 584475500 ps
CPU time 68.15 seconds
Started Feb 07 01:48:53 PM PST 24
Finished Feb 07 01:50:02 PM PST 24
Peak memory 272476 kb
Host smart-86b2c55d-8093-4be3-a8d3-89a8b1aab20f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597739433 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.1597739433
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2395866195
Short name T248
Test name
Test status
Simulation time 17278100 ps
CPU time 13.48 seconds
Started Feb 07 12:43:13 PM PST 24
Finished Feb 07 12:43:27 PM PST 24
Peak memory 263652 kb
Host smart-c61e1e4b-bc4b-4ba5-93d1-d6d2d3eb3f09
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395866195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2395866195
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2904024393
Short name T36
Test name
Test status
Simulation time 343460200 ps
CPU time 24.76 seconds
Started Feb 07 01:47:16 PM PST 24
Finished Feb 07 01:47:41 PM PST 24
Peak memory 264088 kb
Host smart-938ea708-50ec-4853-8b70-3b01f0d8fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904024393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2904024393
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2349808742
Short name T235
Test name
Test status
Simulation time 1048242700 ps
CPU time 888.56 seconds
Started Feb 07 12:43:04 PM PST 24
Finished Feb 07 12:57:59 PM PST 24
Peak memory 263956 kb
Host smart-07649531-ff02-4c8f-a2c1-10e54cd90db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349808742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2349808742
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.804403670
Short name T11
Test name
Test status
Simulation time 677333800 ps
CPU time 15.19 seconds
Started Feb 07 01:47:42 PM PST 24
Finished Feb 07 01:47:59 PM PST 24
Peak memory 264088 kb
Host smart-ff2e021b-2f49-4c94-b79a-5839e551167e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804403670 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.804403670
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1777444397
Short name T209
Test name
Test status
Simulation time 20434000 ps
CPU time 13.33 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 261880 kb
Host smart-c4ca8204-9770-4a2c-b7f0-7afa42c3add0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777444397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1777444397
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3509714045
Short name T228
Test name
Test status
Simulation time 11211000 ps
CPU time 21.89 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:55:44 PM PST 24
Peak memory 272384 kb
Host smart-fd8f6ceb-fdd7-4b57-bd07-30b8a7c0331f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509714045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3509714045
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2312371004
Short name T82
Test name
Test status
Simulation time 10087871300 ps
CPU time 39.76 seconds
Started Feb 07 01:52:18 PM PST 24
Finished Feb 07 01:52:58 PM PST 24
Peak memory 263212 kb
Host smart-48f3a556-eb31-4232-a295-928aec557bad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312371004 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2312371004
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3787767520
Short name T224
Test name
Test status
Simulation time 144952900 ps
CPU time 14.79 seconds
Started Feb 07 12:43:05 PM PST 24
Finished Feb 07 12:43:25 PM PST 24
Peak memory 270104 kb
Host smart-dedbce39-3223-4b2c-93db-7288c35c759a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787767520 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3787767520
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3646668422
Short name T157
Test name
Test status
Simulation time 65674600 ps
CPU time 17.8 seconds
Started Feb 07 01:48:30 PM PST 24
Finished Feb 07 01:48:49 PM PST 24
Peak memory 263236 kb
Host smart-ad290718-1654-4a2c-a341-e89b873a6333
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646668422 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3646668422
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.181126555
Short name T267
Test name
Test status
Simulation time 8387364700 ps
CPU time 117.76 seconds
Started Feb 07 01:48:52 PM PST 24
Finished Feb 07 01:50:51 PM PST 24
Peak memory 264044 kb
Host smart-18e1cb12-ccf6-4fe4-9f49-a9b256f1487c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181126555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.181126555
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.23606937
Short name T272
Test name
Test status
Simulation time 4711239200 ps
CPU time 159.41 seconds
Started Feb 07 01:52:47 PM PST 24
Finished Feb 07 01:55:27 PM PST 24
Peak memory 291276 kb
Host smart-60b34248-6074-4d98-b153-e75e12075f3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23606937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash
_ctrl_intr_rd.23606937
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1187481557
Short name T43
Test name
Test status
Simulation time 26153300 ps
CPU time 13.63 seconds
Started Feb 07 01:49:53 PM PST 24
Finished Feb 07 01:50:07 PM PST 24
Peak memory 264144 kb
Host smart-f692f9cc-884a-4f7a-b553-4f25401ee8c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187481557 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1187481557
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3320089744
Short name T63
Test name
Test status
Simulation time 22551500 ps
CPU time 13.8 seconds
Started Feb 07 01:47:30 PM PST 24
Finished Feb 07 01:47:44 PM PST 24
Peak memory 277236 kb
Host smart-10c6b4df-ed99-494a-9503-9fb2d2562309
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3320089744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3320089744
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1402570454
Short name T177
Test name
Test status
Simulation time 15392500 ps
CPU time 14.11 seconds
Started Feb 07 01:48:01 PM PST 24
Finished Feb 07 01:48:21 PM PST 24
Peak memory 264308 kb
Host smart-c79296d0-d5dc-4f84-b31b-d815f317bd0d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402570454 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1402570454
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.973357061
Short name T487
Test name
Test status
Simulation time 3026201200 ps
CPU time 439.03 seconds
Started Feb 07 01:52:49 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 313292 kb
Host smart-bc47f6f4-4b80-445f-bf88-9e01b55f8c8d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973357061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ct
rl_rw.973357061
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2407668468
Short name T233
Test name
Test status
Simulation time 131348800 ps
CPU time 18.23 seconds
Started Feb 07 12:43:23 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 263868 kb
Host smart-ff7b16e1-fb60-4cd6-8b13-594232e6591b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407668468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2407668468
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.575282283
Short name T42
Test name
Test status
Simulation time 25587800 ps
CPU time 13.18 seconds
Started Feb 07 01:49:32 PM PST 24
Finished Feb 07 01:49:46 PM PST 24
Peak memory 264056 kb
Host smart-5ebc3e74-1b91-4657-ac72-1f0b91076c09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575282283 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.575282283
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3216613922
Short name T384
Test name
Test status
Simulation time 43483100 ps
CPU time 13.58 seconds
Started Feb 07 01:51:41 PM PST 24
Finished Feb 07 01:51:56 PM PST 24
Peak memory 264076 kb
Host smart-81e71480-4e08-499b-8881-8c5c99efb780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216613922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3216613922
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1535486042
Short name T253
Test name
Test status
Simulation time 170362400 ps
CPU time 13.47 seconds
Started Feb 07 12:43:22 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 262348 kb
Host smart-7a20662f-990a-4900-b621-f533d269a131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535486042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1535486042
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.37669771
Short name T194
Test name
Test status
Simulation time 573882000 ps
CPU time 37.19 seconds
Started Feb 07 01:47:03 PM PST 24
Finished Feb 07 01:47:42 PM PST 24
Peak memory 274024 kb
Host smart-635c630a-a1e5-4a76-877a-3fc30e38216a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37669771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_fs_sup.37669771
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2695685139
Short name T757
Test name
Test status
Simulation time 19169300 ps
CPU time 13.66 seconds
Started Feb 07 01:52:04 PM PST 24
Finished Feb 07 01:52:18 PM PST 24
Peak memory 264028 kb
Host smart-03087184-6a3d-4b05-a2c8-7477bdd7a4c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695685139 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2695685139
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.298544515
Short name T31
Test name
Test status
Simulation time 22835100 ps
CPU time 13.57 seconds
Started Feb 07 01:48:00 PM PST 24
Finished Feb 07 01:48:19 PM PST 24
Peak memory 264028 kb
Host smart-3dfcdfdc-8d91-4127-a6c0-57b5598b1392
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298544515 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.298544515
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1683137625
Short name T120
Test name
Test status
Simulation time 18539500 ps
CPU time 21.2 seconds
Started Feb 07 01:47:57 PM PST 24
Finished Feb 07 01:48:20 PM PST 24
Peak memory 264088 kb
Host smart-407c4667-8a59-4f27-bc0f-b73f3d1508d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683137625 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1683137625
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.669990933
Short name T242
Test name
Test status
Simulation time 897351800 ps
CPU time 905.06 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:58:26 PM PST 24
Peak memory 263916 kb
Host smart-f7f0b4c8-ff55-4e79-af00-9a3b7a9b933a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669990933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.669990933
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.20463757
Short name T211
Test name
Test status
Simulation time 1664290700 ps
CPU time 4746.38 seconds
Started Feb 07 01:47:05 PM PST 24
Finished Feb 07 03:06:13 PM PST 24
Peak memory 285768 kb
Host smart-69a09fd2-6be0-4b97-bfaa-637a815ec3ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.20463757
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1203743449
Short name T206
Test name
Test status
Simulation time 40929100 ps
CPU time 13.4 seconds
Started Feb 07 01:51:56 PM PST 24
Finished Feb 07 01:52:10 PM PST 24
Peak memory 273652 kb
Host smart-8149d859-96e9-4d70-8572-2f84936b5f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203743449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1203743449
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.469467965
Short name T162
Test name
Test status
Simulation time 692027400 ps
CPU time 1932.94 seconds
Started Feb 07 01:46:55 PM PST 24
Finished Feb 07 02:19:08 PM PST 24
Peak memory 263548 kb
Host smart-545844f3-930b-4b49-aa51-dfb498a2d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469467965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.469467965
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.3517381902
Short name T128
Test name
Test status
Simulation time 3663302300 ps
CPU time 167.12 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:51:11 PM PST 24
Peak memory 280604 kb
Host smart-ed30e03a-5475-4a3d-9db3-10b6cc9f0ea7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517381902 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.3517381902
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1136649843
Short name T175
Test name
Test status
Simulation time 10043669400 ps
CPU time 139.2 seconds
Started Feb 07 01:47:56 PM PST 24
Finished Feb 07 01:50:16 PM PST 24
Peak memory 288820 kb
Host smart-8377547b-0eda-4b89-ab18-485b7d432444
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136649843 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1136649843
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.467345288
Short name T302
Test name
Test status
Simulation time 44748300 ps
CPU time 37.78 seconds
Started Feb 07 01:48:44 PM PST 24
Finished Feb 07 01:49:23 PM PST 24
Peak memory 262676 kb
Host smart-2dfdd2da-c0f0-4ebb-bc89-a5e247ff732f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467345288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.467345288
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3134970566
Short name T316
Test name
Test status
Simulation time 4971677300 ps
CPU time 65.58 seconds
Started Feb 07 01:47:05 PM PST 24
Finished Feb 07 01:48:11 PM PST 24
Peak memory 262180 kb
Host smart-ff8cccf5-9e66-408e-87b3-51bd7dad1d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134970566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3134970566
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1351262237
Short name T292
Test name
Test status
Simulation time 34374500 ps
CPU time 31.55 seconds
Started Feb 07 01:47:26 PM PST 24
Finished Feb 07 01:47:58 PM PST 24
Peak memory 272424 kb
Host smart-5cbd9ab8-c711-405e-82ff-24f56588acd4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351262237 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1351262237
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1960344168
Short name T312
Test name
Test status
Simulation time 1257858600 ps
CPU time 70.14 seconds
Started Feb 07 01:51:38 PM PST 24
Finished Feb 07 01:52:49 PM PST 24
Peak memory 260976 kb
Host smart-908f3cf5-38a7-4497-af30-6ea6d3be8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960344168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1960344168
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3960065420
Short name T671
Test name
Test status
Simulation time 1170445400 ps
CPU time 146.27 seconds
Started Feb 07 01:52:12 PM PST 24
Finished Feb 07 01:54:39 PM PST 24
Peak memory 292780 kb
Host smart-1d308b2e-0a0a-4a73-a817-90a3529b4661
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960065420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3960065420
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.4099104699
Short name T309
Test name
Test status
Simulation time 2746352600 ps
CPU time 68.03 seconds
Started Feb 07 01:54:31 PM PST 24
Finished Feb 07 01:55:40 PM PST 24
Peak memory 262656 kb
Host smart-e8c612fc-29ee-499b-a08d-0b117d98ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099104699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.4099104699
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.2474406431
Short name T294
Test name
Test status
Simulation time 74957900 ps
CPU time 28.34 seconds
Started Feb 07 01:51:29 PM PST 24
Finished Feb 07 01:51:59 PM PST 24
Peak memory 272388 kb
Host smart-b5cb75fa-d8a1-4078-8d69-273b9c42aa5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474406431 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.2474406431
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.1566311375
Short name T259
Test name
Test status
Simulation time 171691900 ps
CPU time 14.01 seconds
Started Feb 07 01:48:30 PM PST 24
Finished Feb 07 01:48:45 PM PST 24
Peak memory 264076 kb
Host smart-ad7313cf-6c7e-48cb-969f-0175146ee2be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566311375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.1566311375
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.125425165
Short name T301
Test name
Test status
Simulation time 19016300 ps
CPU time 20.62 seconds
Started Feb 07 01:47:06 PM PST 24
Finished Feb 07 01:47:27 PM PST 24
Peak memory 272360 kb
Host smart-5e15f53c-bdad-4048-b7ad-cdcfd84c4804
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125425165 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.125425165
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.224872124
Short name T203
Test name
Test status
Simulation time 440600000 ps
CPU time 770.32 seconds
Started Feb 07 12:43:14 PM PST 24
Finished Feb 07 12:56:05 PM PST 24
Peak memory 261532 kb
Host smart-6532db92-f963-4468-bd4e-fa92c1e20741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224872124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.224872124
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.632849966
Short name T265
Test name
Test status
Simulation time 5123982400 ps
CPU time 167.46 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:54:45 PM PST 24
Peak memory 292416 kb
Host smart-b391601b-f4a4-467a-a47b-509b2f3aacbd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632849966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.632849966
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2935819687
Short name T29
Test name
Test status
Simulation time 4789444100 ps
CPU time 72.71 seconds
Started Feb 07 01:47:00 PM PST 24
Finished Feb 07 01:48:15 PM PST 24
Peak memory 259304 kb
Host smart-439eb3d8-752b-41ba-981c-8e122a3c373e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935819687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2935819687
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.2296302507
Short name T286
Test name
Test status
Simulation time 4256235500 ps
CPU time 430.3 seconds
Started Feb 07 01:47:16 PM PST 24
Finished Feb 07 01:54:27 PM PST 24
Peak memory 259464 kb
Host smart-b2f25373-ab82-41a2-9bee-b5311a4f59ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296302507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2296302507
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3382145882
Short name T27
Test name
Test status
Simulation time 19377300 ps
CPU time 20.93 seconds
Started Feb 07 01:50:41 PM PST 24
Finished Feb 07 01:51:03 PM PST 24
Peak memory 272384 kb
Host smart-b1c99a44-7881-4a12-9a05-9e7b6f0173f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382145882 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3382145882
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.959984284
Short name T307
Test name
Test status
Simulation time 525891000 ps
CPU time 63.37 seconds
Started Feb 07 01:50:37 PM PST 24
Finished Feb 07 01:51:42 PM PST 24
Peak memory 261772 kb
Host smart-81d4e877-e8c9-4011-977f-b798f0049da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959984284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.959984284
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2232894156
Short name T319
Test name
Test status
Simulation time 11215500000 ps
CPU time 76.13 seconds
Started Feb 07 01:51:38 PM PST 24
Finished Feb 07 01:52:55 PM PST 24
Peak memory 257732 kb
Host smart-c15fcde3-12ca-403a-a14b-8cd503efce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232894156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2232894156
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.223859182
Short name T100
Test name
Test status
Simulation time 20131000 ps
CPU time 23.38 seconds
Started Feb 07 01:52:13 PM PST 24
Finished Feb 07 01:52:37 PM PST 24
Peak memory 272284 kb
Host smart-21a59ac8-0233-4c9c-b5c1-1011455c3261
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223859182 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.223859182
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.4105218738
Short name T305
Test name
Test status
Simulation time 6257869500 ps
CPU time 80.44 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:53:37 PM PST 24
Peak memory 257876 kb
Host smart-1ade9341-abd1-4e2a-b133-3fcf959c90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105218738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4105218738
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.631577181
Short name T300
Test name
Test status
Simulation time 26762600 ps
CPU time 21.98 seconds
Started Feb 07 01:53:08 PM PST 24
Finished Feb 07 01:53:31 PM PST 24
Peak memory 272372 kb
Host smart-41c4a1ad-80e2-4839-9560-10794c562b30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631577181 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.631577181
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.182482275
Short name T472
Test name
Test status
Simulation time 18398200 ps
CPU time 13.81 seconds
Started Feb 07 01:47:26 PM PST 24
Finished Feb 07 01:47:40 PM PST 24
Peak memory 264028 kb
Host smart-37370ef1-6699-4caa-b4fd-060269a1c8a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182482275 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.182482275
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1933127030
Short name T169
Test name
Test status
Simulation time 38840500 ps
CPU time 28.89 seconds
Started Feb 07 01:54:24 PM PST 24
Finished Feb 07 01:54:54 PM PST 24
Peak memory 272416 kb
Host smart-dae6e0c6-4a55-4397-920e-048f5d3ab1ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933127030 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1933127030
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1153058594
Short name T237
Test name
Test status
Simulation time 47939500 ps
CPU time 18.45 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:43:52 PM PST 24
Peak memory 263788 kb
Host smart-b063abe9-3e43-4637-9cd5-d3436d226ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153058594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1153058594
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3205331747
Short name T236
Test name
Test status
Simulation time 88565900 ps
CPU time 18.19 seconds
Started Feb 07 12:43:31 PM PST 24
Finished Feb 07 12:43:53 PM PST 24
Peak memory 263704 kb
Host smart-57d9f56e-c890-4c59-953d-accf37afccf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205331747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3205331747
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.2272937096
Short name T189
Test name
Test status
Simulation time 47447700 ps
CPU time 31.93 seconds
Started Feb 07 01:51:07 PM PST 24
Finished Feb 07 01:51:42 PM PST 24
Peak memory 272444 kb
Host smart-9fd6b680-a435-42fa-aec6-a38227f633af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272937096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.2272937096
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.953097569
Short name T97
Test name
Test status
Simulation time 27081400 ps
CPU time 14.09 seconds
Started Feb 07 01:48:57 PM PST 24
Finished Feb 07 01:49:12 PM PST 24
Peak memory 264312 kb
Host smart-f5e39431-d81d-4bf9-9e49-a7f250427248
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=953097569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.953097569
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3419557544
Short name T263
Test name
Test status
Simulation time 645226200 ps
CPU time 748.73 seconds
Started Feb 07 12:43:04 PM PST 24
Finished Feb 07 12:55:39 PM PST 24
Peak memory 261204 kb
Host smart-3dd25772-84f0-4e58-b48c-bfdb445c9e74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419557544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3419557544
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.54491867
Short name T260
Test name
Test status
Simulation time 30671000 ps
CPU time 15.38 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 263776 kb
Host smart-f2e2e8ab-2108-41ac-8660-b7d1f1e7fe6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54491867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.54491867
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2138291388
Short name T840
Test name
Test status
Simulation time 14331811900 ps
CPU time 2179.67 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 02:23:20 PM PST 24
Peak memory 260796 kb
Host smart-ac2e8e9c-d8c4-4bfc-bcb0-256f281d4a25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138291388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2138291388
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3928507200
Short name T505
Test name
Test status
Simulation time 1366770900 ps
CPU time 837.76 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 02:00:56 PM PST 24
Peak memory 264028 kb
Host smart-8147becc-da5a-43ab-ace2-6e1e7b699068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928507200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3928507200
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.3297507042
Short name T124
Test name
Test status
Simulation time 36401656400 ps
CPU time 584.39 seconds
Started Feb 07 01:47:44 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 330272 kb
Host smart-2acb8706-8c0f-4610-91bb-8e23eecf6827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297507042 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.3297507042
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.4253735276
Short name T123
Test name
Test status
Simulation time 42456100 ps
CPU time 30.8 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:52:56 PM PST 24
Peak memory 272384 kb
Host smart-60681d38-1875-4754-a069-09826e13c8b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253735276 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.4253735276
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2999347258
Short name T244
Test name
Test status
Simulation time 43153600 ps
CPU time 46.03 seconds
Started Feb 07 12:43:02 PM PST 24
Finished Feb 07 12:43:51 PM PST 24
Peak memory 259896 kb
Host smart-7d3c68d4-459e-49ae-a1e9-154a6583df24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999347258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2999347258
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3855744441
Short name T281
Test name
Test status
Simulation time 72445200 ps
CPU time 16.58 seconds
Started Feb 07 12:43:12 PM PST 24
Finished Feb 07 12:43:29 PM PST 24
Peak memory 259888 kb
Host smart-a2c6cc77-0457-4271-a7eb-d9f741c572df
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855744441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3855744441
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3685596132
Short name T210
Test name
Test status
Simulation time 18530700 ps
CPU time 13.48 seconds
Started Feb 07 12:43:02 PM PST 24
Finished Feb 07 12:43:19 PM PST 24
Peak memory 261152 kb
Host smart-b57e5e22-cc75-492d-9691-b7df89707661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685596132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
685596132
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3359459461
Short name T240
Test name
Test status
Simulation time 114992900 ps
CPU time 18.5 seconds
Started Feb 07 12:43:04 PM PST 24
Finished Feb 07 12:43:28 PM PST 24
Peak memory 260068 kb
Host smart-e1b0ad51-ebed-4917-b75c-81312aa8e25e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359459461 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3359459461
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.90010676
Short name T347
Test name
Test status
Simulation time 19989300 ps
CPU time 15.4 seconds
Started Feb 07 12:43:08 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 259996 kb
Host smart-ba7531a2-ea7a-47bf-9d8b-add943657482
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90010676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.90010676
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3945911818
Short name T283
Test name
Test status
Simulation time 8023815800 ps
CPU time 74.93 seconds
Started Feb 07 12:43:01 PM PST 24
Finished Feb 07 12:44:20 PM PST 24
Peak memory 259664 kb
Host smart-d43c7d99-ec28-4d1e-9a98-6c7524e5e770
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945911818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3945911818
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1866503515
Short name T353
Test name
Test status
Simulation time 9522606600 ps
CPU time 83.03 seconds
Started Feb 07 12:43:05 PM PST 24
Finished Feb 07 12:44:33 PM PST 24
Peak memory 259944 kb
Host smart-362c5e54-2b62-429e-83aa-4120c1c38b0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866503515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1866503515
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2815486335
Short name T255
Test name
Test status
Simulation time 26241500 ps
CPU time 13.31 seconds
Started Feb 07 12:43:02 PM PST 24
Finished Feb 07 12:43:19 PM PST 24
Peak memory 261124 kb
Host smart-4e60ccf4-41c3-4d39-943e-b06a5cf7ab31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815486335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2815486335
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.184129985
Short name T220
Test name
Test status
Simulation time 1330712700 ps
CPU time 452.72 seconds
Started Feb 07 12:43:13 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 261284 kb
Host smart-4ef4645d-5c09-406b-9e3b-ff7d62df8f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184129985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.184129985
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.33075503
Short name T246
Test name
Test status
Simulation time 154297700 ps
CPU time 17.07 seconds
Started Feb 07 12:43:21 PM PST 24
Finished Feb 07 12:43:45 PM PST 24
Peak memory 259928 kb
Host smart-4ed178f4-f4f9-4c91-ba7c-b25cb2c8925e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33075503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.flash_ctrl_csr_rw.33075503
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3458264637
Short name T247
Test name
Test status
Simulation time 133035300 ps
CPU time 17.89 seconds
Started Feb 07 12:43:15 PM PST 24
Finished Feb 07 12:43:34 PM PST 24
Peak memory 262156 kb
Host smart-20131041-01b6-47b8-8272-05151f7b9a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458264637 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3458264637
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2128570396
Short name T241
Test name
Test status
Simulation time 20997600 ps
CPU time 12.99 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 259904 kb
Host smart-7aee37ed-668d-464c-81d8-719b3b357843
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128570396 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2128570396
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2064310896
Short name T251
Test name
Test status
Simulation time 28975200 ps
CPU time 12.91 seconds
Started Feb 07 12:43:13 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 259780 kb
Host smart-f7823891-f548-49c6-a496-23904bbbbcbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064310896 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2064310896
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1221719820
Short name T243
Test name
Test status
Simulation time 2750470100 ps
CPU time 895.11 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:58:17 PM PST 24
Peak memory 263836 kb
Host smart-10f10903-04dc-4254-bc74-5f980f2c34e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221719820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1221719820
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3835106567
Short name T346
Test name
Test status
Simulation time 16344700 ps
CPU time 13.7 seconds
Started Feb 07 12:43:16 PM PST 24
Finished Feb 07 12:43:30 PM PST 24
Peak memory 261956 kb
Host smart-8de0890c-2787-4cd7-9a22-cdbbd1d2fdda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835106567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3835106567
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1150355386
Short name T249
Test name
Test status
Simulation time 122938700 ps
CPU time 29.15 seconds
Started Feb 07 12:43:16 PM PST 24
Finished Feb 07 12:43:46 PM PST 24
Peak memory 261612 kb
Host smart-4592237d-d549-45bb-bccd-4bcd7285c1c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150355386 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1150355386
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.627234629
Short name T351
Test name
Test status
Simulation time 14451100 ps
CPU time 13.03 seconds
Started Feb 07 12:43:21 PM PST 24
Finished Feb 07 12:43:41 PM PST 24
Peak memory 259748 kb
Host smart-20ba2206-ad6f-4764-8e58-80543576c61e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627234629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.627234629
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.888240142
Short name T262
Test name
Test status
Simulation time 47816500 ps
CPU time 15.23 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 263800 kb
Host smart-1ec69537-d673-44ec-aec5-538775379eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888240142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.888240142
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1638720688
Short name T299
Test name
Test status
Simulation time 122603200 ps
CPU time 17.1 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 278776 kb
Host smart-1b273c6e-a610-45ac-bb79-d6adc7843c91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638720688 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1638720688
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.784963219
Short name T239
Test name
Test status
Simulation time 1921035700 ps
CPU time 31.75 seconds
Started Feb 07 12:43:21 PM PST 24
Finished Feb 07 12:43:59 PM PST 24
Peak memory 259912 kb
Host smart-89f3d147-b27d-402e-a83f-0a34a455724d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784963219 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.784963219
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1220692278
Short name T342
Test name
Test status
Simulation time 15063100 ps
CPU time 13.18 seconds
Started Feb 07 12:43:16 PM PST 24
Finished Feb 07 12:43:30 PM PST 24
Peak memory 259752 kb
Host smart-38509762-0c59-488b-9321-049fefa07c56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220692278 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.1220692278
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1188511562
Short name T352
Test name
Test status
Simulation time 537897700 ps
CPU time 16.24 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 260008 kb
Host smart-9b68e2a9-52f6-485d-84eb-9ba5c7822221
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188511562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1188511562
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1631337749
Short name T222
Test name
Test status
Simulation time 159335700 ps
CPU time 15.99 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:43:52 PM PST 24
Peak memory 271928 kb
Host smart-09849214-af09-4f41-b031-e2c4d576c324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631337749 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1631337749
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1358794698
Short name T221
Test name
Test status
Simulation time 77671200 ps
CPU time 17.13 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:39 PM PST 24
Peak memory 271968 kb
Host smart-894c5d4e-5dee-446f-8943-373ecb95b5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358794698 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1358794698
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.454526188
Short name T364
Test name
Test status
Simulation time 113579500 ps
CPU time 17.32 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:38 PM PST 24
Peak memory 260044 kb
Host smart-ec65f3aa-82c3-44df-b94f-55c63dacc53a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454526188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_csr_rw.454526188
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1264332548
Short name T53
Test name
Test status
Simulation time 223836200 ps
CPU time 20.78 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 259924 kb
Host smart-eb0a38e9-3c83-455f-af85-21502e9b77b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264332548 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1264332548
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2351839091
Short name T223
Test name
Test status
Simulation time 5783968700 ps
CPU time 762.34 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:56:17 PM PST 24
Peak memory 263720 kb
Host smart-37d8533b-d5a0-4544-b0b6-6286b38475cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351839091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.2351839091
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2214200070
Short name T252
Test name
Test status
Simulation time 58637200 ps
CPU time 16.24 seconds
Started Feb 07 12:43:31 PM PST 24
Finished Feb 07 12:43:51 PM PST 24
Peak memory 259744 kb
Host smart-e962b6f8-f54a-435d-98ff-f5f9e5c6ef24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214200070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2214200070
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2786394421
Short name T348
Test name
Test status
Simulation time 76803700 ps
CPU time 17.33 seconds
Started Feb 07 12:43:26 PM PST 24
Finished Feb 07 12:43:48 PM PST 24
Peak memory 263656 kb
Host smart-82f0a8c9-8478-490b-abd8-a9edb1017a2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786394421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.2786394421
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1626735540
Short name T360
Test name
Test status
Simulation time 12460500 ps
CPU time 15.33 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:43:48 PM PST 24
Peak memory 259896 kb
Host smart-4facc9b1-26c9-4c2e-b7be-5b4a59e96e33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626735540 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1626735540
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.444125607
Short name T254
Test name
Test status
Simulation time 19061700 ps
CPU time 15.27 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:43:48 PM PST 24
Peak memory 259944 kb
Host smart-c55dfcd0-5a79-4286-bf52-21fd7d354c16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444125607 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.444125607
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1696292501
Short name T225
Test name
Test status
Simulation time 55573900 ps
CPU time 45.61 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:57 PM PST 24
Peak memory 259980 kb
Host smart-11f63b24-edbd-4313-8247-af507251986b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696292501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1696292501
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.687652192
Short name T261
Test name
Test status
Simulation time 65166400 ps
CPU time 13.24 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:24 PM PST 24
Peak memory 261992 kb
Host smart-6aa30a9b-9e90-4ee8-82ab-d4230d9cb5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687652192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.687652192
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2810328886
Short name T361
Test name
Test status
Simulation time 36149600 ps
CPU time 14.97 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 260028 kb
Host smart-417b2b58-99cb-4fa6-85c9-199ed88a6c5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810328886 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2810328886
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1455808249
Short name T363
Test name
Test status
Simulation time 27474300 ps
CPU time 15.86 seconds
Started Feb 07 12:43:00 PM PST 24
Finished Feb 07 12:43:21 PM PST 24
Peak memory 259840 kb
Host smart-0618d3c2-7c02-49ad-b60a-79f394eec06d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455808249 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1455808249
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3419108889
Short name T350
Test name
Test status
Simulation time 118183600 ps
CPU time 13.32 seconds
Started Feb 07 12:43:31 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 262092 kb
Host smart-317780ad-8dd3-4824-95e7-d21fbbc560b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419108889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
3419108889
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.861687702
Short name T354
Test name
Test status
Simulation time 15160400 ps
CPU time 13.35 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:43:46 PM PST 24
Peak memory 262144 kb
Host smart-218b6b4f-95d1-461c-a85c-3560e9d32247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861687702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.861687702
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.759539126
Short name T295
Test name
Test status
Simulation time 48881600 ps
CPU time 13.22 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:43:46 PM PST 24
Peak memory 262100 kb
Host smart-e452bdec-9a4c-413d-8891-3bdd3f678074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759539126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.759539126
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3410714326
Short name T357
Test name
Test status
Simulation time 46264800 ps
CPU time 13.2 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 262152 kb
Host smart-998ec8da-7241-4f88-b7ff-ca31ae344fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410714326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
3410714326
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2989556886
Short name T201
Test name
Test status
Simulation time 1592827100 ps
CPU time 38.71 seconds
Started Feb 07 12:43:05 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 259956 kb
Host smart-d7f13c06-df22-4e1f-a12f-9e4156bdbdb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989556886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2989556886
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.797132348
Short name T245
Test name
Test status
Simulation time 4792207200 ps
CPU time 44.9 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:56 PM PST 24
Peak memory 259932 kb
Host smart-b2f82925-c356-41a2-92a7-6db182bcba9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797132348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.797132348
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1112152147
Short name T256
Test name
Test status
Simulation time 53552700 ps
CPU time 13.51 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:25 PM PST 24
Peak memory 263584 kb
Host smart-681b6073-2080-4611-8d95-25be99bc3129
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112152147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1112152147
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1152292435
Short name T365
Test name
Test status
Simulation time 18483100 ps
CPU time 13.21 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:24 PM PST 24
Peak memory 260000 kb
Host smart-930ce931-90bc-46ae-aa2c-dab6574589eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152292435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1152292435
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4014963688
Short name T54
Test name
Test status
Simulation time 57615500 ps
CPU time 19.64 seconds
Started Feb 07 12:43:11 PM PST 24
Finished Feb 07 12:43:32 PM PST 24
Peak memory 259952 kb
Host smart-633c2c2c-deea-47de-88ba-f8ee44021ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014963688 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.4014963688
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2302022263
Short name T344
Test name
Test status
Simulation time 13070500 ps
CPU time 15.86 seconds
Started Feb 07 12:43:06 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 259864 kb
Host smart-45d00280-34b8-4abb-b6a4-b996c297dbdb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302022263 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2302022263
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2036755358
Short name T358
Test name
Test status
Simulation time 41955200 ps
CPU time 15.44 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 259716 kb
Host smart-2b1eb2e9-b808-452f-9df3-2a38412a586c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036755358 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2036755358
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3008147061
Short name T355
Test name
Test status
Simulation time 62774800 ps
CPU time 13.45 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 262020 kb
Host smart-1e7c0e92-5b67-44aa-888e-1db5ab85d618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008147061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3008147061
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.19518290
Short name T345
Test name
Test status
Simulation time 56295100 ps
CPU time 13.47 seconds
Started Feb 07 12:43:20 PM PST 24
Finished Feb 07 12:43:40 PM PST 24
Peak memory 262196 kb
Host smart-49c924bb-4137-4fd9-8c5e-412ae9ab0b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19518290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.19518290
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1433495508
Short name T297
Test name
Test status
Simulation time 29591900 ps
CPU time 13.3 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 262088 kb
Host smart-c13b0a84-e219-4445-987f-a05b9e119b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433495508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1433495508
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3523680144
Short name T278
Test name
Test status
Simulation time 1559414200 ps
CPU time 34.85 seconds
Started Feb 07 12:43:10 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 259868 kb
Host smart-90bc69fc-39bb-4ad0-ba6e-77016e99729c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523680144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.3523680144
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1541213399
Short name T202
Test name
Test status
Simulation time 67027100 ps
CPU time 38.73 seconds
Started Feb 07 12:43:06 PM PST 24
Finished Feb 07 12:43:50 PM PST 24
Peak memory 259828 kb
Host smart-852fcbc7-952e-4aeb-8d91-315d2464736c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541213399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1541213399
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.836102480
Short name T322
Test name
Test status
Simulation time 17063800 ps
CPU time 13.38 seconds
Started Feb 07 12:43:07 PM PST 24
Finished Feb 07 12:43:24 PM PST 24
Peak memory 263200 kb
Host smart-915adb16-2196-4fa4-8042-063f6c81d222
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836102480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.836102480
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.279161551
Short name T55
Test name
Test status
Simulation time 293261100 ps
CPU time 15.14 seconds
Started Feb 07 12:43:16 PM PST 24
Finished Feb 07 12:43:32 PM PST 24
Peak memory 259988 kb
Host smart-cda5d22e-9590-47a6-91dc-e2a337f5bf17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279161551 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.279161551
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1448744268
Short name T356
Test name
Test status
Simulation time 33910000 ps
CPU time 15.45 seconds
Started Feb 07 12:43:05 PM PST 24
Finished Feb 07 12:43:26 PM PST 24
Peak memory 259828 kb
Host smart-157a1858-4c9e-4cd8-a6a9-b2729baaa044
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448744268 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1448744268
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3708359492
Short name T250
Test name
Test status
Simulation time 15466900 ps
CPU time 13.58 seconds
Started Feb 07 12:43:40 PM PST 24
Finished Feb 07 12:43:55 PM PST 24
Peak memory 262040 kb
Host smart-cd76a9b6-930d-49b0-9dc3-ac5cbac3d77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708359492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3708359492
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.739548939
Short name T349
Test name
Test status
Simulation time 71726000 ps
CPU time 13.63 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 262132 kb
Host smart-a059fdea-7245-4aa4-be5b-b8cc7803ba71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739548939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.739548939
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3821208464
Short name T296
Test name
Test status
Simulation time 52554400 ps
CPU time 13.5 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 262244 kb
Host smart-a2113bc4-70df-46a6-beb2-5017c3a11080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821208464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
3821208464
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3004333454
Short name T284
Test name
Test status
Simulation time 783519400 ps
CPU time 30.12 seconds
Started Feb 07 12:43:21 PM PST 24
Finished Feb 07 12:43:58 PM PST 24
Peak memory 259932 kb
Host smart-4262b2dc-d2ac-4a10-bf0d-1adc99fa1b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004333454 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3004333454
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3170514987
Short name T343
Test name
Test status
Simulation time 195124100 ps
CPU time 15.57 seconds
Started Feb 07 12:43:12 PM PST 24
Finished Feb 07 12:43:28 PM PST 24
Peak memory 259892 kb
Host smart-297c41ef-dd3a-4b27-87a1-138cd132d1ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170514987 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3170514987
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1795333057
Short name T341
Test name
Test status
Simulation time 15515500 ps
CPU time 13.2 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:34 PM PST 24
Peak memory 259896 kb
Host smart-e6d8b09c-9170-4cee-8854-0050e532b307
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795333057 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1795333057
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2359733024
Short name T359
Test name
Test status
Simulation time 14754200 ps
CPU time 13.46 seconds
Started Feb 07 12:43:24 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 259528 kb
Host smart-c6459778-d608-4e97-bde6-34bcc7bcf472
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359733024 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2359733024
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3025028934
Short name T279
Test name
Test status
Simulation time 141472100 ps
CPU time 17.24 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:38 PM PST 24
Peak memory 259988 kb
Host smart-2086df3d-02ce-4967-a3d1-14a176c91341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025028934 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3025028934
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2849037412
Short name T282
Test name
Test status
Simulation time 14257300 ps
CPU time 15.4 seconds
Started Feb 07 12:43:22 PM PST 24
Finished Feb 07 12:43:44 PM PST 24
Peak memory 259920 kb
Host smart-4238a156-dc99-4769-935d-23ed7211d459
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849037412 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2849037412
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3877730653
Short name T338
Test name
Test status
Simulation time 31261900 ps
CPU time 14.69 seconds
Started Feb 07 12:43:19 PM PST 24
Finished Feb 07 12:43:36 PM PST 24
Peak memory 272088 kb
Host smart-7437b1a5-867b-4924-8e72-661daba0bdba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877730653 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3877730653
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1990390727
Short name T280
Test name
Test status
Simulation time 224852500 ps
CPU time 13.8 seconds
Started Feb 07 12:43:24 PM PST 24
Finished Feb 07 12:43:43 PM PST 24
Peak memory 261824 kb
Host smart-8a794ae0-51f8-405c-8f82-3eab16ff1e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990390727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1
990390727
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.717042609
Short name T238
Test name
Test status
Simulation time 40915900 ps
CPU time 12.9 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:33 PM PST 24
Peak memory 259908 kb
Host smart-b6d70f43-2f0d-40d8-a52a-3ae85ab105d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717042609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.717042609
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2669689392
Short name T204
Test name
Test status
Simulation time 25402200 ps
CPU time 16.31 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 263772 kb
Host smart-eb3aa45f-7c9f-4744-b457-a4ba21038bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669689392 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2669689392
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2915435532
Short name T362
Test name
Test status
Simulation time 127519500 ps
CPU time 16.93 seconds
Started Feb 07 12:43:24 PM PST 24
Finished Feb 07 12:43:46 PM PST 24
Peak memory 259828 kb
Host smart-839be532-e7ee-4ff1-8092-d77a685f1193
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915435532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2915435532
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.684095642
Short name T298
Test name
Test status
Simulation time 83707400 ps
CPU time 13.19 seconds
Started Feb 07 12:43:18 PM PST 24
Finished Feb 07 12:43:33 PM PST 24
Peak memory 262000 kb
Host smart-75c02cb2-13a9-4292-9577-bdbc16ceed3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684095642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.684095642
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.975894882
Short name T677
Test name
Test status
Simulation time 114019800 ps
CPU time 13.83 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 01:47:29 PM PST 24
Peak memory 264148 kb
Host smart-7934bb8c-a717-4d6e-9a6b-537ef7e4fdc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975894882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.975894882
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.628146037
Short name T478
Test name
Test status
Simulation time 37026900 ps
CPU time 13.73 seconds
Started Feb 07 01:47:12 PM PST 24
Finished Feb 07 01:47:26 PM PST 24
Peak memory 264020 kb
Host smart-6aaa780d-fbef-4f1f-9451-0a9e88f47fe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628146037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_config_regwen.628146037
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.3020369519
Short name T880
Test name
Test status
Simulation time 19585500 ps
CPU time 15.58 seconds
Started Feb 07 01:47:02 PM PST 24
Finished Feb 07 01:47:21 PM PST 24
Peak memory 273760 kb
Host smart-11474d60-eb74-4ab6-a19f-90e1fd2fcec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020369519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3020369519
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.3598946531
Short name T711
Test name
Test status
Simulation time 430922500 ps
CPU time 104.71 seconds
Started Feb 07 01:47:02 PM PST 24
Finished Feb 07 01:48:49 PM PST 24
Peak memory 279604 kb
Host smart-659fe67a-cc01-4939-ad8b-f96442e66cb2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598946531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.3598946531
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.243146674
Short name T134
Test name
Test status
Simulation time 489666055000 ps
CPU time 3318.05 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 02:42:15 PM PST 24
Peak memory 261120 kb
Host smart-a9ed8c74-fbca-4429-bdf9-dddece61087c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243146674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_full_mem_access.243146674
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.600110708
Short name T269
Test name
Test status
Simulation time 50912100 ps
CPU time 91.84 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:48:32 PM PST 24
Peak memory 260764 kb
Host smart-d2c93580-90dd-4028-b1a7-8e9bda32d851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600110708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.600110708
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1047294571
Short name T72
Test name
Test status
Simulation time 15518800 ps
CPU time 13.37 seconds
Started Feb 07 01:47:17 PM PST 24
Finished Feb 07 01:47:31 PM PST 24
Peak memory 262980 kb
Host smart-52657987-f788-40bd-8561-71938ebc50d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047294571 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1047294571
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.632610899
Short name T590
Test name
Test status
Simulation time 275336678000 ps
CPU time 1811.06 seconds
Started Feb 07 01:46:54 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 258336 kb
Host smart-514a2e18-9a13-4571-aef2-8f76d5ad4b73
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632610899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.632610899
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1064233973
Short name T860
Test name
Test status
Simulation time 160184006100 ps
CPU time 894.11 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 02:01:52 PM PST 24
Peak memory 258204 kb
Host smart-b82d70cb-2461-440f-afce-3b5755884da5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064233973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1064233973
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.3671957763
Short name T879
Test name
Test status
Simulation time 11372093100 ps
CPU time 524.98 seconds
Started Feb 07 01:47:13 PM PST 24
Finished Feb 07 01:55:58 PM PST 24
Peak memory 324212 kb
Host smart-9f8167a9-ef6a-4b6d-81f1-c957e6d2bf35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671957763 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.3671957763
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2463749246
Short name T8
Test name
Test status
Simulation time 8662869600 ps
CPU time 193.69 seconds
Started Feb 07 01:47:00 PM PST 24
Finished Feb 07 01:50:16 PM PST 24
Peak memory 282984 kb
Host smart-033c815a-ef36-42cc-9eb2-72d6fded2177
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463749246 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2463749246
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.1732943267
Short name T448
Test name
Test status
Simulation time 4599653000 ps
CPU time 106.59 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:48:48 PM PST 24
Peak memory 264044 kb
Host smart-947e8d60-b98e-46cd-a319-3302a22bc42e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732943267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.1732943267
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.769735467
Short name T438
Test name
Test status
Simulation time 46367948200 ps
CPU time 350.6 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:52:52 PM PST 24
Peak memory 263992 kb
Host smart-5e0d622a-e08d-45f0-b19a-eb6eac4d5fec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769
735467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.769735467
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1063989035
Short name T326
Test name
Test status
Simulation time 2017688300 ps
CPU time 85.83 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 01:48:24 PM PST 24
Peak memory 257992 kb
Host smart-92e6d028-2e98-4390-93f5-4083b71a2eda
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063989035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1063989035
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.4084773646
Short name T466
Test name
Test status
Simulation time 6305498400 ps
CPU time 204.39 seconds
Started Feb 07 01:47:03 PM PST 24
Finished Feb 07 01:50:30 PM PST 24
Peak memory 280620 kb
Host smart-8cf83358-129c-43df-89ab-7cba9e30d2c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084773646 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.4084773646
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2110950204
Short name T130
Test name
Test status
Simulation time 25579800 ps
CPU time 14 seconds
Started Feb 07 01:47:17 PM PST 24
Finished Feb 07 01:47:32 PM PST 24
Peak memory 277472 kb
Host smart-00847f00-0df1-4a24-90c9-cfc94eae57a6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2110950204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2110950204
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.2757108202
Short name T549
Test name
Test status
Simulation time 1636631400 ps
CPU time 215.9 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:50:32 PM PST 24
Peak memory 259880 kb
Host smart-6ffd62ae-cfa5-41a0-a38c-61611d41618d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757108202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2757108202
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1014284284
Short name T158
Test name
Test status
Simulation time 106701400 ps
CPU time 18.19 seconds
Started Feb 07 01:47:00 PM PST 24
Finished Feb 07 01:47:20 PM PST 24
Peak memory 264336 kb
Host smart-daee613a-8988-45f1-a1fd-a4cc71348a9d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014284284 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1014284284
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4126801015
Short name T226
Test name
Test status
Simulation time 45238800 ps
CPU time 13.87 seconds
Started Feb 07 01:47:13 PM PST 24
Finished Feb 07 01:47:28 PM PST 24
Peak memory 264248 kb
Host smart-166d61b3-52c4-4b80-8b35-e4d0f1bddd61
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126801015 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4126801015
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3962493996
Short name T266
Test name
Test status
Simulation time 119676700 ps
CPU time 16.79 seconds
Started Feb 07 01:47:04 PM PST 24
Finished Feb 07 01:47:22 PM PST 24
Peak memory 263996 kb
Host smart-eb67fa19-2e21-4493-ade8-1cfa47b8c5ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962493996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3962493996
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.1567821755
Short name T591
Test name
Test status
Simulation time 147682700 ps
CPU time 1281.23 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 02:08:19 PM PST 24
Peak memory 284608 kb
Host smart-8af565b6-03aa-45c4-a8bf-b9d234d28cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567821755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.1567821755
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.790644347
Short name T932
Test name
Test status
Simulation time 1678652500 ps
CPU time 114.85 seconds
Started Feb 07 01:47:05 PM PST 24
Finished Feb 07 01:49:01 PM PST 24
Peak memory 263476 kb
Host smart-92cc2072-d8e3-4e50-b4c0-698ecccdc9ed
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790644347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.790644347
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1861915187
Short name T182
Test name
Test status
Simulation time 84542300 ps
CPU time 43.89 seconds
Started Feb 07 01:47:17 PM PST 24
Finished Feb 07 01:48:02 PM PST 24
Peak memory 272412 kb
Host smart-111783d9-1508-49da-9b5f-ecac91af4d3e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861915187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1861915187
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2597501071
Short name T545
Test name
Test status
Simulation time 62260300 ps
CPU time 32.21 seconds
Started Feb 07 01:47:05 PM PST 24
Finished Feb 07 01:47:38 PM PST 24
Peak memory 272304 kb
Host smart-471bf4f3-8dba-408b-bf9d-45acc481b9b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597501071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2597501071
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3465366866
Short name T784
Test name
Test status
Simulation time 58087300 ps
CPU time 14.52 seconds
Started Feb 07 01:47:00 PM PST 24
Finished Feb 07 01:47:16 PM PST 24
Peak memory 264108 kb
Host smart-283e5dde-1875-4764-abba-b3f5e3d07af8
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3465366866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3465366866
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.227473604
Short name T669
Test name
Test status
Simulation time 22744500 ps
CPU time 21.58 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:23 PM PST 24
Peak memory 264200 kb
Host smart-5f9103e2-4b5e-484e-b118-1582e68e520a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227473604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_read_word_sweep_serr.227473604
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.770721425
Short name T839
Test name
Test status
Simulation time 380489900 ps
CPU time 83.39 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:48:20 PM PST 24
Peak memory 280432 kb
Host smart-57cd23aa-804f-42a3-bece-645146842302
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770721425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_ro.770721425
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.4190396286
Short name T517
Test name
Test status
Simulation time 4982517000 ps
CPU time 127.56 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:49:05 PM PST 24
Peak memory 280660 kb
Host smart-5453aa0a-61d1-44c4-a177-fe627899a502
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190396286 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.4190396286
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1853085993
Short name T653
Test name
Test status
Simulation time 12800937500 ps
CPU time 474.19 seconds
Started Feb 07 01:46:55 PM PST 24
Finished Feb 07 01:54:49 PM PST 24
Peak memory 312168 kb
Host smart-10c849ed-9bf0-4d15-8880-4bd8544386f9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853085993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.1853085993
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.1123723921
Short name T513
Test name
Test status
Simulation time 88567200 ps
CPU time 31.87 seconds
Started Feb 07 01:47:03 PM PST 24
Finished Feb 07 01:47:37 PM PST 24
Peak memory 272076 kb
Host smart-5e1e3771-df61-4e3f-9899-609191c9ef9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123723921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.1123723921
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4231240608
Short name T515
Test name
Test status
Simulation time 70281700 ps
CPU time 30.68 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 01:47:29 PM PST 24
Peak memory 272388 kb
Host smart-f91d9604-0693-46df-88c8-3e7f2d25c44a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231240608 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4231240608
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.761009045
Short name T496
Test name
Test status
Simulation time 2034215400 ps
CPU time 51.46 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:53 PM PST 24
Peak memory 264136 kb
Host smart-963b2c8d-2bc8-47b0-aa0d-b2d7e3da529f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761009045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.761009045
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.1164839009
Short name T415
Test name
Test status
Simulation time 1141930700 ps
CPU time 71.46 seconds
Started Feb 07 01:47:10 PM PST 24
Finished Feb 07 01:48:23 PM PST 24
Peak memory 280608 kb
Host smart-ef1022c9-99e0-4ec0-b9b5-c2363771d912
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164839009 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.1164839009
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.456819300
Short name T385
Test name
Test status
Simulation time 58790200 ps
CPU time 149.36 seconds
Started Feb 07 01:46:55 PM PST 24
Finished Feb 07 01:49:25 PM PST 24
Peak memory 275828 kb
Host smart-675206c2-2452-4d58-ae7e-cf3e71104b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456819300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.456819300
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1386191452
Short name T427
Test name
Test status
Simulation time 13346200 ps
CPU time 23.48 seconds
Started Feb 07 01:46:53 PM PST 24
Finished Feb 07 01:47:17 PM PST 24
Peak memory 257888 kb
Host smart-4b05dbe3-06fb-4ae7-a59b-ff55ff029041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386191452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1386191452
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.1699891291
Short name T872
Test name
Test status
Simulation time 168146800 ps
CPU time 217.54 seconds
Started Feb 07 01:47:03 PM PST 24
Finished Feb 07 01:50:43 PM PST 24
Peak memory 269232 kb
Host smart-2a483295-ab44-46ae-b4a2-55700194ad0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699891291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.1699891291
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.4243652367
Short name T507
Test name
Test status
Simulation time 77089900 ps
CPU time 26.63 seconds
Started Feb 07 01:46:52 PM PST 24
Finished Feb 07 01:47:19 PM PST 24
Peak memory 260620 kb
Host smart-ee8c18d8-46a6-4041-a0ac-21c8bb73819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243652367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4243652367
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.337359762
Short name T393
Test name
Test status
Simulation time 10336716200 ps
CPU time 221.17 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 01:50:39 PM PST 24
Peak memory 264008 kb
Host smart-4c61a96f-a89c-464a-a7ee-2b11689ab344
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337359762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_wo.337359762
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.2313475231
Short name T9
Test name
Test status
Simulation time 45759100 ps
CPU time 14.89 seconds
Started Feb 07 01:47:03 PM PST 24
Finished Feb 07 01:47:20 PM PST 24
Peak memory 263804 kb
Host smart-b521e56a-9c2f-4b23-b2b4-c0bb0b9e9215
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313475231 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2313475231
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3093798241
Short name T32
Test name
Test status
Simulation time 13325100 ps
CPU time 13.5 seconds
Started Feb 07 01:47:28 PM PST 24
Finished Feb 07 01:47:42 PM PST 24
Peak memory 264200 kb
Host smart-83f4c43b-9e27-4628-ae91-43552c36003b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093798241 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3093798241
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2058992213
Short name T836
Test name
Test status
Simulation time 227212400 ps
CPU time 14.05 seconds
Started Feb 07 01:47:43 PM PST 24
Finished Feb 07 01:47:58 PM PST 24
Peak memory 264040 kb
Host smart-2c637e33-9b4b-4dc3-bfa8-49aef33015e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058992213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
058992213
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1167718869
Short name T887
Test name
Test status
Simulation time 159021000 ps
CPU time 15.53 seconds
Started Feb 07 01:47:46 PM PST 24
Finished Feb 07 01:48:04 PM PST 24
Peak memory 273672 kb
Host smart-1829384c-730b-4ca5-9e50-f8f2b43fcc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167718869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1167718869
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1849821015
Short name T171
Test name
Test status
Simulation time 128281000 ps
CPU time 105.11 seconds
Started Feb 07 01:47:29 PM PST 24
Finished Feb 07 01:49:15 PM PST 24
Peak memory 272476 kb
Host smart-bdfaf631-68a7-4222-9d0a-8e51bc22ad17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849821015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1849821015
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.43497663
Short name T52
Test name
Test status
Simulation time 4725298500 ps
CPU time 2203.77 seconds
Started Feb 07 01:47:31 PM PST 24
Finished Feb 07 02:24:16 PM PST 24
Peak memory 263992 kb
Host smart-c20ab4d8-5ac7-49e5-a90a-9530db3d66f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43497663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error
_mp.43497663
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3084759636
Short name T163
Test name
Test status
Simulation time 947089000 ps
CPU time 2597.65 seconds
Started Feb 07 01:47:27 PM PST 24
Finished Feb 07 02:30:45 PM PST 24
Peak memory 263388 kb
Host smart-6f6d4e6d-ffd5-477d-b8c1-4f72580b5e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084759636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3084759636
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2250402015
Short name T215
Test name
Test status
Simulation time 1304298800 ps
CPU time 871.56 seconds
Started Feb 07 01:47:24 PM PST 24
Finished Feb 07 02:01:57 PM PST 24
Peak memory 264040 kb
Host smart-66f3b633-d628-449a-b612-8afc99d670ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250402015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2250402015
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2041677940
Short name T273
Test name
Test status
Simulation time 1095878500 ps
CPU time 36.6 seconds
Started Feb 07 01:47:31 PM PST 24
Finished Feb 07 01:48:08 PM PST 24
Peak memory 272300 kb
Host smart-e0536ff5-0baf-4877-a153-a5d2689a81e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041677940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2041677940
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1260655379
Short name T275
Test name
Test status
Simulation time 15334900 ps
CPU time 13.51 seconds
Started Feb 07 01:47:42 PM PST 24
Finished Feb 07 01:47:56 PM PST 24
Peak memory 264180 kb
Host smart-a878b6ff-3c8f-4e96-aaee-3d743b4e40e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260655379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1260655379
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2053607076
Short name T87
Test name
Test status
Simulation time 129853579800 ps
CPU time 1882.23 seconds
Started Feb 07 01:47:15 PM PST 24
Finished Feb 07 02:18:38 PM PST 24
Peak memory 257848 kb
Host smart-70381983-cd30-45c1-bb02-6fde56f8db49
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053607076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2053607076
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2579821672
Short name T107
Test name
Test status
Simulation time 40120553900 ps
CPU time 709.93 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:59:09 PM PST 24
Peak memory 258184 kb
Host smart-d3281e0c-77ea-4177-ba51-6ad553b0db51
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579821672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2579821672
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.2284020983
Short name T474
Test name
Test status
Simulation time 28669772600 ps
CPU time 143.56 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 01:49:39 PM PST 24
Peak memory 258532 kb
Host smart-e7e178ca-d037-4221-af50-f3eca5cc81bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284020983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.2284020983
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3401190852
Short name T761
Test name
Test status
Simulation time 66745998000 ps
CPU time 203.73 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:50:42 PM PST 24
Peak memory 288804 kb
Host smart-4ac6068c-43ad-466c-ba1e-6e83e6c9fd0c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401190852 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3401190852
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.483105617
Short name T455
Test name
Test status
Simulation time 6444847400 ps
CPU time 95.42 seconds
Started Feb 07 01:47:27 PM PST 24
Finished Feb 07 01:49:03 PM PST 24
Peak memory 264036 kb
Host smart-d47331ad-28ac-42fc-a497-1b985ee57ca0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483105617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.483105617
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.657697127
Short name T389
Test name
Test status
Simulation time 49843639300 ps
CPU time 404.96 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:54:04 PM PST 24
Peak memory 264032 kb
Host smart-67326c1c-3b80-40ed-8d59-82e5c935551f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657
697127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.657697127
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1588034489
Short name T779
Test name
Test status
Simulation time 2206065300 ps
CPU time 80.45 seconds
Started Feb 07 01:47:27 PM PST 24
Finished Feb 07 01:48:48 PM PST 24
Peak memory 258188 kb
Host smart-d34d0fed-a086-4076-ae99-0d1f4c793c21
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588034489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1588034489
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1953253048
Short name T13
Test name
Test status
Simulation time 25554100 ps
CPU time 13.7 seconds
Started Feb 07 01:47:51 PM PST 24
Finished Feb 07 01:48:06 PM PST 24
Peak memory 264040 kb
Host smart-041b24b7-af38-4d07-ac7e-12a960c922d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953253048 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1953253048
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.1188772672
Short name T797
Test name
Test status
Simulation time 30587111700 ps
CPU time 366.46 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 01:53:21 PM PST 24
Peak memory 272340 kb
Host smart-c079e6af-8b03-4eaa-b1cc-9c6bafff94bb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188772672 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.1188772672
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.1635086664
Short name T536
Test name
Test status
Simulation time 40057700 ps
CPU time 132.95 seconds
Started Feb 07 01:47:13 PM PST 24
Finished Feb 07 01:49:27 PM PST 24
Peak memory 258232 kb
Host smart-be882be6-fb74-4d35-aca5-0e68ed866408
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635086664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.1635086664
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.1023193940
Short name T679
Test name
Test status
Simulation time 1909807800 ps
CPU time 139.23 seconds
Started Feb 07 01:48:16 PM PST 24
Finished Feb 07 01:50:39 PM PST 24
Peak memory 280576 kb
Host smart-17f07f56-d142-47b5-868a-51c4f6c60eef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023193940 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1023193940
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.268278645
Short name T853
Test name
Test status
Simulation time 735077000 ps
CPU time 348.32 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 01:53:04 PM PST 24
Peak memory 264028 kb
Host smart-48bd6403-870a-4bc5-beaa-63ca61430266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268278645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.268278645
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2090890602
Short name T159
Test name
Test status
Simulation time 115206100 ps
CPU time 14.75 seconds
Started Feb 07 01:47:34 PM PST 24
Finished Feb 07 01:47:50 PM PST 24
Peak memory 264288 kb
Host smart-3393b79d-63b8-4aaa-a244-25ca7bfddfe1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090890602 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2090890602
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1299135122
Short name T871
Test name
Test status
Simulation time 44326800 ps
CPU time 14.21 seconds
Started Feb 07 01:47:33 PM PST 24
Finished Feb 07 01:47:48 PM PST 24
Peak memory 264292 kb
Host smart-f1d95fd7-5497-462c-a3ef-b5242e87a753
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299135122 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1299135122
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1099047340
Short name T938
Test name
Test status
Simulation time 29716400 ps
CPU time 13.39 seconds
Started Feb 07 01:47:16 PM PST 24
Finished Feb 07 01:47:30 PM PST 24
Peak memory 263948 kb
Host smart-19cd0182-34ac-45a6-9b00-787cf5dd42c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099047340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1099047340
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1516547604
Short name T68
Test name
Test status
Simulation time 1978193600 ps
CPU time 1319.37 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 02:09:15 PM PST 24
Peak memory 287976 kb
Host smart-a3726588-b85a-4c8c-a9a7-966b60c7b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516547604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1516547604
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.4234136702
Short name T552
Test name
Test status
Simulation time 13365117500 ps
CPU time 252.06 seconds
Started Feb 07 01:47:13 PM PST 24
Finished Feb 07 01:51:26 PM PST 24
Peak memory 263428 kb
Host smart-0fa3a887-3535-4253-8cf2-ca633d5621d7
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234136702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4234136702
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1213703772
Short name T532
Test name
Test status
Simulation time 128084700 ps
CPU time 31.6 seconds
Started Feb 07 01:47:41 PM PST 24
Finished Feb 07 01:48:14 PM PST 24
Peak memory 272396 kb
Host smart-166e49a6-78f1-40d2-963f-99a4f0938e6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213703772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1213703772
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.97639593
Short name T611
Test name
Test status
Simulation time 33461800 ps
CPU time 22.94 seconds
Started Feb 07 01:47:15 PM PST 24
Finished Feb 07 01:47:39 PM PST 24
Peak memory 264204 kb
Host smart-89faf0f7-6fbb-4f50-b443-5869cd74bbaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97639593 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.97639593
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.583757100
Short name T391
Test name
Test status
Simulation time 39773300 ps
CPU time 22.4 seconds
Started Feb 07 01:47:33 PM PST 24
Finished Feb 07 01:47:56 PM PST 24
Peak memory 264104 kb
Host smart-a728788b-4d65-4b91-a334-5a789c8e041d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583757100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.583757100
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1161317816
Short name T95
Test name
Test status
Simulation time 61290824800 ps
CPU time 969.86 seconds
Started Feb 07 01:47:33 PM PST 24
Finished Feb 07 02:03:44 PM PST 24
Peak memory 360280 kb
Host smart-f0167eb7-7e9f-4277-bb4c-035c1806acc4
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161317816 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1161317816
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.1791338680
Short name T918
Test name
Test status
Simulation time 476001300 ps
CPU time 121.91 seconds
Started Feb 07 01:47:35 PM PST 24
Finished Feb 07 01:49:38 PM PST 24
Peak memory 280524 kb
Host smart-cd241e72-d7ff-4808-ad47-5449fadfebb0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791338680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.1791338680
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2647401733
Short name T198
Test name
Test status
Simulation time 1152343500 ps
CPU time 123.08 seconds
Started Feb 07 01:47:20 PM PST 24
Finished Feb 07 01:49:24 PM PST 24
Peak memory 280616 kb
Host smart-20f43ab7-32af-4212-b758-830077788755
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647401733 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2647401733
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.71048777
Short name T551
Test name
Test status
Simulation time 3499993800 ps
CPU time 489.49 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:55:28 PM PST 24
Peak memory 313252 kb
Host smart-ab3beeab-361b-40be-80f2-385f8a4f27a2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71048777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_rw.71048777
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3421642280
Short name T922
Test name
Test status
Simulation time 14116627600 ps
CPU time 571.15 seconds
Started Feb 07 01:47:18 PM PST 24
Finished Feb 07 01:56:50 PM PST 24
Peak memory 310392 kb
Host smart-98ce54c4-f602-44f8-8a2d-86fa82b7837b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421642280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3421642280
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.3135642441
Short name T17
Test name
Test status
Simulation time 1279678300 ps
CPU time 4785.32 seconds
Started Feb 07 01:47:32 PM PST 24
Finished Feb 07 03:07:18 PM PST 24
Peak memory 285952 kb
Host smart-880dcd18-e69d-40d2-8440-162cf3c4b9b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135642441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3135642441
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2317524519
Short name T311
Test name
Test status
Simulation time 1965314400 ps
CPU time 71.5 seconds
Started Feb 07 01:47:39 PM PST 24
Finished Feb 07 01:48:51 PM PST 24
Peak memory 257892 kb
Host smart-26facde3-f490-45fa-9075-6efdbdcc32e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317524519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2317524519
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2422285472
Short name T405
Test name
Test status
Simulation time 1503187600 ps
CPU time 55.19 seconds
Started Feb 07 01:47:16 PM PST 24
Finished Feb 07 01:48:12 PM PST 24
Peak memory 264160 kb
Host smart-7a2cd918-249d-4d37-af65-bd499913df82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422285472 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2422285472
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2471868386
Short name T789
Test name
Test status
Simulation time 12271061900 ps
CPU time 72.46 seconds
Started Feb 07 01:47:16 PM PST 24
Finished Feb 07 01:48:30 PM PST 24
Peak memory 272456 kb
Host smart-8a279d66-66f8-4ff4-b8a6-eb59cfff3b36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471868386 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2471868386
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3268359494
Short name T809
Test name
Test status
Simulation time 26913000 ps
CPU time 75.61 seconds
Started Feb 07 01:47:12 PM PST 24
Finished Feb 07 01:48:28 PM PST 24
Peak memory 273680 kb
Host smart-58596084-282a-435b-ab94-fa29ce8db3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268359494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3268359494
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.21174911
Short name T900
Test name
Test status
Simulation time 59544500 ps
CPU time 26.51 seconds
Started Feb 07 01:47:14 PM PST 24
Finished Feb 07 01:47:41 PM PST 24
Peak memory 257896 kb
Host smart-44328e34-45c8-4ece-bbe8-dcbe64a4ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21174911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.21174911
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1277789944
Short name T452
Test name
Test status
Simulation time 135522400 ps
CPU time 436.51 seconds
Started Feb 07 01:47:43 PM PST 24
Finished Feb 07 01:55:00 PM PST 24
Peak memory 277432 kb
Host smart-d2eea0f2-4082-4dea-9d3d-532219c22192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277789944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1277789944
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.3224887279
Short name T707
Test name
Test status
Simulation time 28733700 ps
CPU time 26.72 seconds
Started Feb 07 01:47:19 PM PST 24
Finished Feb 07 01:47:46 PM PST 24
Peak memory 260680 kb
Host smart-9d92f840-a451-4e1a-8fb6-18ed478bd708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224887279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3224887279
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.2689277264
Short name T916
Test name
Test status
Simulation time 38740700 ps
CPU time 13.85 seconds
Started Feb 07 01:50:45 PM PST 24
Finished Feb 07 01:51:04 PM PST 24
Peak memory 264076 kb
Host smart-7ea726aa-0a1a-499f-9ff1-5a3a54595906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689277264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
2689277264
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.3736172311
Short name T483
Test name
Test status
Simulation time 16166200 ps
CPU time 13.72 seconds
Started Feb 07 01:50:37 PM PST 24
Finished Feb 07 01:50:52 PM PST 24
Peak memory 273616 kb
Host smart-9f24815a-d9ec-4510-96fb-48738d6dcdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736172311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3736172311
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2056159074
Short name T94
Test name
Test status
Simulation time 10043169400 ps
CPU time 60 seconds
Started Feb 07 01:50:39 PM PST 24
Finished Feb 07 01:51:41 PM PST 24
Peak memory 280352 kb
Host smart-873753d1-5ccf-4af3-8a12-ca82b8208553
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056159074 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2056159074
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3359221656
Short name T178
Test name
Test status
Simulation time 14957200 ps
CPU time 13.5 seconds
Started Feb 07 01:50:34 PM PST 24
Finished Feb 07 01:50:49 PM PST 24
Peak memory 264052 kb
Host smart-52e413f7-429c-45f7-b314-27c2db3f8878
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359221656 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3359221656
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.253446286
Short name T106
Test name
Test status
Simulation time 290238033000 ps
CPU time 798.89 seconds
Started Feb 07 01:50:31 PM PST 24
Finished Feb 07 02:03:51 PM PST 24
Peak memory 258344 kb
Host smart-77ce06b4-86c3-4843-85eb-7800d7b6dce5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253446286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.253446286
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2287965171
Short name T490
Test name
Test status
Simulation time 4270903200 ps
CPU time 48.21 seconds
Started Feb 07 01:50:27 PM PST 24
Finished Feb 07 01:51:16 PM PST 24
Peak memory 259636 kb
Host smart-ffba344b-851a-456f-b559-e5ef85312eb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287965171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2287965171
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1853311372
Short name T583
Test name
Test status
Simulation time 5367948900 ps
CPU time 165.76 seconds
Started Feb 07 01:50:32 PM PST 24
Finished Feb 07 01:53:18 PM PST 24
Peak memory 292088 kb
Host smart-dcce34cd-2bd0-4aaa-9be7-db0c2428d34e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853311372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1853311372
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3916435676
Short name T333
Test name
Test status
Simulation time 11291237700 ps
CPU time 196.85 seconds
Started Feb 07 01:50:40 PM PST 24
Finished Feb 07 01:53:58 PM PST 24
Peak memory 283132 kb
Host smart-fc037743-0073-40f1-aa8e-315f1468f51a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916435676 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3916435676
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.1082844631
Short name T778
Test name
Test status
Simulation time 16121815800 ps
CPU time 75.72 seconds
Started Feb 07 01:50:34 PM PST 24
Finished Feb 07 01:51:51 PM PST 24
Peak memory 259052 kb
Host smart-11aa17a7-0254-4d1a-ba1a-c1de293749dc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082844631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1
082844631
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2499720004
Short name T491
Test name
Test status
Simulation time 15917200 ps
CPU time 13.61 seconds
Started Feb 07 01:50:39 PM PST 24
Finished Feb 07 01:50:54 PM PST 24
Peak memory 264092 kb
Host smart-e2a40181-bbb6-43e0-8e35-56d1a3be37cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499720004 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2499720004
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.4124496653
Short name T66
Test name
Test status
Simulation time 7725778300 ps
CPU time 521 seconds
Started Feb 07 01:50:33 PM PST 24
Finished Feb 07 01:59:15 PM PST 24
Peak memory 272692 kb
Host smart-34bdad93-5189-4002-bbc5-12cdee66563e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124496653 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.4124496653
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3655986221
Short name T891
Test name
Test status
Simulation time 94143500 ps
CPU time 439.76 seconds
Started Feb 07 01:50:33 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 259864 kb
Host smart-6dd316d7-4328-4906-b28b-54651f0a10d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655986221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3655986221
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2838498031
Short name T395
Test name
Test status
Simulation time 70647100 ps
CPU time 13.66 seconds
Started Feb 07 01:50:37 PM PST 24
Finished Feb 07 01:50:52 PM PST 24
Peak memory 263940 kb
Host smart-700b97f5-3818-440a-bd1e-c197c3ab49e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838498031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2838498031
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2709692847
Short name T495
Test name
Test status
Simulation time 1722878900 ps
CPU time 103.07 seconds
Started Feb 07 01:50:40 PM PST 24
Finished Feb 07 01:52:24 PM PST 24
Peak memory 280492 kb
Host smart-42f18aca-77d6-4508-9848-bb3833457907
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709692847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.2709692847
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1122033984
Short name T920
Test name
Test status
Simulation time 11087649000 ps
CPU time 511.26 seconds
Started Feb 07 01:50:35 PM PST 24
Finished Feb 07 01:59:08 PM PST 24
Peak memory 313152 kb
Host smart-f5243b07-cd31-4ee1-89c9-a71bf6d976a4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122033984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.1122033984
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2096037425
Short name T290
Test name
Test status
Simulation time 48375000 ps
CPU time 31.27 seconds
Started Feb 07 01:50:35 PM PST 24
Finished Feb 07 01:51:07 PM PST 24
Peak memory 272320 kb
Host smart-0dfa0893-f48e-4720-b42d-b776adf84f4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096037425 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2096037425
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.3178295389
Short name T597
Test name
Test status
Simulation time 26084400 ps
CPU time 101.32 seconds
Started Feb 07 01:50:30 PM PST 24
Finished Feb 07 01:52:12 PM PST 24
Peak memory 273724 kb
Host smart-60815ea8-6af5-4cb7-951b-fbbd8a7190a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178295389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3178295389
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1118714819
Short name T479
Test name
Test status
Simulation time 7100963900 ps
CPU time 137.51 seconds
Started Feb 07 01:50:34 PM PST 24
Finished Feb 07 01:52:52 PM PST 24
Peak memory 264096 kb
Host smart-e1f0e0d1-08d1-4b1f-8241-f5f8f5cb2bf6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118714819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.1118714819
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1415009990
Short name T748
Test name
Test status
Simulation time 74414000 ps
CPU time 13.92 seconds
Started Feb 07 01:51:13 PM PST 24
Finished Feb 07 01:51:28 PM PST 24
Peak memory 263744 kb
Host smart-7cc54ab9-122c-46a8-9828-048153610e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415009990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1415009990
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2118020609
Short name T148
Test name
Test status
Simulation time 52900500 ps
CPU time 15.76 seconds
Started Feb 07 01:50:55 PM PST 24
Finished Feb 07 01:51:12 PM PST 24
Peak memory 273808 kb
Host smart-a99498c0-c0a0-4160-a406-eb184d896af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118020609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2118020609
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2784084285
Short name T85
Test name
Test status
Simulation time 10038292800 ps
CPU time 95.44 seconds
Started Feb 07 01:51:12 PM PST 24
Finished Feb 07 01:52:50 PM PST 24
Peak memory 272160 kb
Host smart-958d755e-9777-4822-a750-eb1ae6bcb623
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784084285 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2784084285
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2466489568
Short name T548
Test name
Test status
Simulation time 74519200 ps
CPU time 13.7 seconds
Started Feb 07 01:50:56 PM PST 24
Finished Feb 07 01:51:11 PM PST 24
Peak memory 264036 kb
Host smart-f0a50457-d05b-431e-80c6-a6057f4bef24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466489568 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2466489568
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3798468103
Short name T569
Test name
Test status
Simulation time 11251526300 ps
CPU time 166.31 seconds
Started Feb 07 01:50:44 PM PST 24
Finished Feb 07 01:53:32 PM PST 24
Peak memory 292416 kb
Host smart-d2c75859-da55-45f1-a8a5-57b8e181d410
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798468103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3798468103
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2386878564
Short name T464
Test name
Test status
Simulation time 17338495400 ps
CPU time 183.87 seconds
Started Feb 07 01:50:45 PM PST 24
Finished Feb 07 01:53:54 PM PST 24
Peak memory 291772 kb
Host smart-5a4be4be-28cd-425e-828b-b2e4c6fec94c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386878564 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2386878564
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.606880926
Short name T565
Test name
Test status
Simulation time 4375622900 ps
CPU time 71.76 seconds
Started Feb 07 01:50:47 PM PST 24
Finished Feb 07 01:52:03 PM PST 24
Peak memory 258876 kb
Host smart-e29c5d73-4972-4697-97dd-0561eba5223f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606880926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.606880926
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3126958477
Short name T537
Test name
Test status
Simulation time 31406333800 ps
CPU time 196.59 seconds
Started Feb 07 01:50:46 PM PST 24
Finished Feb 07 01:54:08 PM PST 24
Peak memory 261144 kb
Host smart-6327a967-b244-42a9-a5da-f30bd30cdd55
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126958477 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3126958477
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.1853531089
Short name T88
Test name
Test status
Simulation time 69098800 ps
CPU time 134.03 seconds
Started Feb 07 01:50:46 PM PST 24
Finished Feb 07 01:53:06 PM PST 24
Peak memory 258048 kb
Host smart-4eee5770-8758-44d2-be8a-fc9c985cd8d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853531089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.1853531089
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.362887643
Short name T904
Test name
Test status
Simulation time 109209000 ps
CPU time 68.8 seconds
Started Feb 07 01:50:45 PM PST 24
Finished Feb 07 01:51:59 PM PST 24
Peak memory 263732 kb
Host smart-2ed95614-a438-44c5-9c65-cb1b30af1b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362887643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.362887643
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.421352369
Short name T150
Test name
Test status
Simulation time 400813300 ps
CPU time 273.72 seconds
Started Feb 07 01:50:45 PM PST 24
Finished Feb 07 01:55:24 PM PST 24
Peak memory 280380 kb
Host smart-8addf7d3-0bac-4025-9129-1e47dcb09338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421352369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.421352369
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3733428236
Short name T695
Test name
Test status
Simulation time 122465700 ps
CPU time 30.4 seconds
Started Feb 07 01:50:46 PM PST 24
Finished Feb 07 01:51:22 PM PST 24
Peak memory 272388 kb
Host smart-8725ab78-c79d-4f2a-83fa-cbbb9effbd1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733428236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3733428236
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.544615919
Short name T579
Test name
Test status
Simulation time 1642294000 ps
CPU time 104.38 seconds
Started Feb 07 01:50:44 PM PST 24
Finished Feb 07 01:52:30 PM PST 24
Peak memory 280456 kb
Host smart-12568dad-d69c-4d4e-9f9e-a93ad849f2f7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544615919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_ro.544615919
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1521033282
Short name T127
Test name
Test status
Simulation time 13477070600 ps
CPU time 562.22 seconds
Started Feb 07 01:50:46 PM PST 24
Finished Feb 07 02:00:14 PM PST 24
Peak memory 313200 kb
Host smart-81715c33-a915-49d4-9ad7-6abfdacbc7ee
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521033282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.1521033282
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.2041293544
Short name T168
Test name
Test status
Simulation time 53469800 ps
CPU time 32.49 seconds
Started Feb 07 01:50:43 PM PST 24
Finished Feb 07 01:51:17 PM PST 24
Peak memory 272400 kb
Host smart-b61878cc-1f66-4c22-843b-d6ef5136cfd0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041293544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.2041293544
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.4270117959
Short name T764
Test name
Test status
Simulation time 92374400 ps
CPU time 31.56 seconds
Started Feb 07 01:50:48 PM PST 24
Finished Feb 07 01:51:23 PM PST 24
Peak memory 272364 kb
Host smart-d80032f7-6ae1-4e40-997c-7fe1fac8fac2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270117959 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.4270117959
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3089801863
Short name T736
Test name
Test status
Simulation time 5246997400 ps
CPU time 66.43 seconds
Started Feb 07 01:50:54 PM PST 24
Finished Feb 07 01:52:02 PM PST 24
Peak memory 262780 kb
Host smart-843be9c8-f2e7-404f-b820-9e94e0f471df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089801863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3089801863
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.1230017976
Short name T471
Test name
Test status
Simulation time 34630800 ps
CPU time 74.7 seconds
Started Feb 07 01:50:44 PM PST 24
Finished Feb 07 01:52:00 PM PST 24
Peak memory 273332 kb
Host smart-09cf8070-0216-4e99-af6e-fd82247cf450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230017976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1230017976
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.2854669257
Short name T131
Test name
Test status
Simulation time 1898906800 ps
CPU time 143.88 seconds
Started Feb 07 01:50:51 PM PST 24
Finished Feb 07 01:53:18 PM PST 24
Peak memory 264048 kb
Host smart-b176aa10-db65-4175-ad6c-c50ed972b0e3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854669257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.2854669257
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1308906660
Short name T649
Test name
Test status
Simulation time 120435500 ps
CPU time 13.63 seconds
Started Feb 07 01:51:17 PM PST 24
Finished Feb 07 01:51:32 PM PST 24
Peak memory 264040 kb
Host smart-df5b84bd-e64f-420b-9903-1bf7ae161982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308906660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1308906660
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.218106319
Short name T943
Test name
Test status
Simulation time 49354000 ps
CPU time 15.62 seconds
Started Feb 07 01:51:07 PM PST 24
Finished Feb 07 01:51:26 PM PST 24
Peak memory 273660 kb
Host smart-a120f9a2-d6d1-4aad-9640-e3dd311b6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218106319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.218106319
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1613698806
Short name T92
Test name
Test status
Simulation time 10011575000 ps
CPU time 137.99 seconds
Started Feb 07 01:51:21 PM PST 24
Finished Feb 07 01:53:40 PM PST 24
Peak memory 370912 kb
Host smart-3da60883-655a-4697-945b-b715fcbc760b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613698806 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1613698806
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2157378073
Short name T185
Test name
Test status
Simulation time 25625400 ps
CPU time 13.45 seconds
Started Feb 07 01:51:14 PM PST 24
Finished Feb 07 01:51:28 PM PST 24
Peak memory 264060 kb
Host smart-b6c98a2c-2823-4dd4-b43a-de5648819639
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157378073 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2157378073
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3600985440
Short name T620
Test name
Test status
Simulation time 150176278500 ps
CPU time 752.98 seconds
Started Feb 07 01:50:58 PM PST 24
Finished Feb 07 02:03:32 PM PST 24
Peak memory 258296 kb
Host smart-75bc4f36-edc3-4df0-9cb8-f767023872ba
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600985440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3600985440
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2023323079
Short name T650
Test name
Test status
Simulation time 1808644900 ps
CPU time 37.42 seconds
Started Feb 07 01:51:12 PM PST 24
Finished Feb 07 01:51:52 PM PST 24
Peak memory 258332 kb
Host smart-5de563cb-3481-4a41-953a-bc37dc175644
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023323079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2023323079
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.311482537
Short name T329
Test name
Test status
Simulation time 16710153300 ps
CPU time 216.99 seconds
Started Feb 07 01:51:08 PM PST 24
Finished Feb 07 01:54:48 PM PST 24
Peak memory 291756 kb
Host smart-92a975ab-2761-4b89-95b0-430045e275d6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311482537 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.311482537
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.3400172115
Short name T192
Test name
Test status
Simulation time 972538400 ps
CPU time 90.04 seconds
Started Feb 07 01:51:09 PM PST 24
Finished Feb 07 01:52:43 PM PST 24
Peak memory 258084 kb
Host smart-7cdd2e1b-5649-4747-b9aa-9e88d48386ac
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400172115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3
400172115
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1074995008
Short name T277
Test name
Test status
Simulation time 15079800 ps
CPU time 14.05 seconds
Started Feb 07 01:51:12 PM PST 24
Finished Feb 07 01:51:28 PM PST 24
Peak memory 264128 kb
Host smart-de2735cb-ba1b-419d-87c7-b15009d5ca52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074995008 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1074995008
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3197527176
Short name T770
Test name
Test status
Simulation time 22863355800 ps
CPU time 170.98 seconds
Started Feb 07 01:50:57 PM PST 24
Finished Feb 07 01:53:49 PM PST 24
Peak memory 261092 kb
Host smart-1965814c-ac63-4217-b794-af02f7254bf4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197527176 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3197527176
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2968554515
Short name T61
Test name
Test status
Simulation time 39982100 ps
CPU time 110.74 seconds
Started Feb 07 01:50:59 PM PST 24
Finished Feb 07 01:52:51 PM PST 24
Peak memory 258048 kb
Host smart-bdf27202-d353-4774-b26d-92847a396b62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968554515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2968554515
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1540524652
Short name T683
Test name
Test status
Simulation time 2875609300 ps
CPU time 213.8 seconds
Started Feb 07 01:50:54 PM PST 24
Finished Feb 07 01:54:30 PM PST 24
Peak memory 264048 kb
Host smart-e44a1664-de0b-4d04-8edf-894c768d2b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540524652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1540524652
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.2231554496
Short name T804
Test name
Test status
Simulation time 30781800 ps
CPU time 13.47 seconds
Started Feb 07 01:51:10 PM PST 24
Finished Feb 07 01:51:27 PM PST 24
Peak memory 264076 kb
Host smart-666bd530-8443-4408-86b2-ee3bcf554907
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231554496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.2231554496
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.863811632
Short name T661
Test name
Test status
Simulation time 310140900 ps
CPU time 1331.83 seconds
Started Feb 07 01:50:58 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 285548 kb
Host smart-88b7f81f-0388-472e-897f-0cccd286694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863811632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.863811632
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.2814548569
Short name T337
Test name
Test status
Simulation time 194948500 ps
CPU time 32.29 seconds
Started Feb 07 01:51:11 PM PST 24
Finished Feb 07 01:51:46 PM PST 24
Peak memory 272316 kb
Host smart-e5acd7af-0687-4844-b8c8-24127b77d1b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814548569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.2814548569
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2893775745
Short name T585
Test name
Test status
Simulation time 424005800 ps
CPU time 126.17 seconds
Started Feb 07 01:51:10 PM PST 24
Finished Feb 07 01:53:20 PM PST 24
Peak memory 280568 kb
Host smart-d2191b42-5096-4722-af36-36427bc037b4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893775745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.2893775745
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.648443792
Short name T662
Test name
Test status
Simulation time 3374524000 ps
CPU time 495.18 seconds
Started Feb 07 01:51:07 PM PST 24
Finished Feb 07 01:59:25 PM PST 24
Peak memory 313320 kb
Host smart-0d469c73-4795-45d3-824a-d78c65573c53
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648443792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ct
rl_rw.648443792
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.692002916
Short name T293
Test name
Test status
Simulation time 31414300 ps
CPU time 30.27 seconds
Started Feb 07 01:51:09 PM PST 24
Finished Feb 07 01:51:41 PM PST 24
Peak memory 272424 kb
Host smart-aa4c65ce-7971-40c8-a7f4-723965942552
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692002916 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.692002916
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1167070844
Short name T896
Test name
Test status
Simulation time 3465506900 ps
CPU time 66.51 seconds
Started Feb 07 01:51:07 PM PST 24
Finished Feb 07 01:52:17 PM PST 24
Peak memory 257868 kb
Host smart-781e0d22-7e2c-48c3-b01a-f6ed25141a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167070844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1167070844
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2662306169
Short name T742
Test name
Test status
Simulation time 55235900 ps
CPU time 149.73 seconds
Started Feb 07 01:51:01 PM PST 24
Finished Feb 07 01:53:33 PM PST 24
Peak memory 275748 kb
Host smart-7591d93e-b6a3-42a1-b8df-b9cb72f2578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662306169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2662306169
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3773932073
Short name T873
Test name
Test status
Simulation time 4938938600 ps
CPU time 210.81 seconds
Started Feb 07 01:51:09 PM PST 24
Finished Feb 07 01:54:44 PM PST 24
Peak memory 263884 kb
Host smart-a924466a-b003-456a-910a-c3e6caad1e01
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773932073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.3773932073
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2343949397
Short name T501
Test name
Test status
Simulation time 72257700 ps
CPU time 13.9 seconds
Started Feb 07 01:51:23 PM PST 24
Finished Feb 07 01:51:39 PM PST 24
Peak memory 263940 kb
Host smart-fe1e9513-1c4d-4b5c-8445-0d1cb308f446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343949397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2343949397
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2813073841
Short name T787
Test name
Test status
Simulation time 45209900 ps
CPU time 15.81 seconds
Started Feb 07 01:51:38 PM PST 24
Finished Feb 07 01:51:54 PM PST 24
Peak memory 273508 kb
Host smart-3647bd6d-7219-4de7-907f-75b7a55abf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813073841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2813073841
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.1042874760
Short name T657
Test name
Test status
Simulation time 32464300 ps
CPU time 21.99 seconds
Started Feb 07 01:51:27 PM PST 24
Finished Feb 07 01:51:50 PM PST 24
Peak memory 272440 kb
Host smart-75fde5da-24fe-446d-8ecb-7cabdbd2893f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042874760 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.1042874760
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.872631796
Short name T944
Test name
Test status
Simulation time 10012168600 ps
CPU time 136.05 seconds
Started Feb 07 01:51:39 PM PST 24
Finished Feb 07 01:53:56 PM PST 24
Peak memory 370816 kb
Host smart-60de0608-c9fc-4f79-bb05-d1b4c7f08a45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872631796 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.872631796
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3452399517
Short name T622
Test name
Test status
Simulation time 46326000 ps
CPU time 13.52 seconds
Started Feb 07 01:51:22 PM PST 24
Finished Feb 07 01:51:36 PM PST 24
Peak memory 264144 kb
Host smart-638b7c7d-7675-4c44-a696-e06b1345b45a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452399517 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3452399517
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.37050678
Short name T890
Test name
Test status
Simulation time 160169587600 ps
CPU time 770.37 seconds
Started Feb 07 01:51:20 PM PST 24
Finished Feb 07 02:04:12 PM PST 24
Peak memory 257844 kb
Host smart-94311fb0-5194-4d7d-a030-c04b67eb806a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37050678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.flash_ctrl_hw_rma_reset.37050678
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3199702844
Short name T909
Test name
Test status
Simulation time 1489244800 ps
CPU time 130.37 seconds
Started Feb 07 01:51:21 PM PST 24
Finished Feb 07 01:53:32 PM PST 24
Peak memory 257896 kb
Host smart-82d4e5c3-e1c5-44da-b04c-b4300d9c5763
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199702844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3199702844
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.2630337070
Short name T598
Test name
Test status
Simulation time 6520281500 ps
CPU time 67.74 seconds
Started Feb 07 01:51:21 PM PST 24
Finished Feb 07 01:52:30 PM PST 24
Peak memory 258100 kb
Host smart-8f59f282-f30b-49ff-9122-8b434b03d01f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630337070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.2
630337070
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3214473951
Short name T430
Test name
Test status
Simulation time 15367800 ps
CPU time 13.41 seconds
Started Feb 07 01:51:23 PM PST 24
Finished Feb 07 01:51:37 PM PST 24
Peak memory 263980 kb
Host smart-85a4452e-c863-43b9-906b-93ee8ff220e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214473951 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3214473951
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2627826637
Short name T67
Test name
Test status
Simulation time 38162772500 ps
CPU time 296.98 seconds
Started Feb 07 01:51:19 PM PST 24
Finished Feb 07 01:56:17 PM PST 24
Peak memory 272072 kb
Host smart-1df6198b-e0e7-4445-b948-58dba396f976
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627826637 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2627826637
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.431687396
Short name T480
Test name
Test status
Simulation time 193402400 ps
CPU time 236.01 seconds
Started Feb 07 01:51:13 PM PST 24
Finished Feb 07 01:55:11 PM PST 24
Peak memory 264072 kb
Host smart-5aaee505-6e0a-4e3c-a3a9-5a65f2fe8eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431687396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.431687396
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3118905658
Short name T621
Test name
Test status
Simulation time 118594900 ps
CPU time 16.32 seconds
Started Feb 07 01:51:22 PM PST 24
Finished Feb 07 01:51:39 PM PST 24
Peak memory 264036 kb
Host smart-549618dd-71c4-4770-8375-67ccc6e10dd0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118905658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3118905658
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1150803928
Short name T726
Test name
Test status
Simulation time 3661168800 ps
CPU time 1281.21 seconds
Started Feb 07 01:51:13 PM PST 24
Finished Feb 07 02:12:36 PM PST 24
Peak memory 284896 kb
Host smart-abc3bfb9-6e21-4986-ac12-be3e3a7134d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150803928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1150803928
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.498788714
Short name T173
Test name
Test status
Simulation time 1389839200 ps
CPU time 340.6 seconds
Started Feb 07 01:51:21 PM PST 24
Finished Feb 07 01:57:03 PM PST 24
Peak memory 307816 kb
Host smart-4a2e3548-9e23-4b89-b7eb-8dc92910ecaa
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498788714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ct
rl_rw.498788714
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.3133473291
Short name T190
Test name
Test status
Simulation time 278968500 ps
CPU time 31.41 seconds
Started Feb 07 01:51:24 PM PST 24
Finished Feb 07 01:51:57 PM PST 24
Peak memory 272408 kb
Host smart-13b22873-5478-45bd-85d8-756928eebb9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133473291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.3133473291
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2541366418
Short name T257
Test name
Test status
Simulation time 34110700 ps
CPU time 125.33 seconds
Started Feb 07 01:51:16 PM PST 24
Finished Feb 07 01:53:22 PM PST 24
Peak memory 274996 kb
Host smart-d2cf24c1-cd0f-4e5a-8c9d-a66b4e9442bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541366418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2541366418
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.2154929147
Short name T888
Test name
Test status
Simulation time 3994985400 ps
CPU time 175.97 seconds
Started Feb 07 01:51:19 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 264044 kb
Host smart-94c9d4d0-1003-4c12-9884-b82b8b5e181d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154929147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.2154929147
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.1453136100
Short name T651
Test name
Test status
Simulation time 34841600 ps
CPU time 13.53 seconds
Started Feb 07 01:51:40 PM PST 24
Finished Feb 07 01:51:54 PM PST 24
Peak memory 273772 kb
Host smart-17e1bd6d-088b-46ae-8d29-ffe80e35e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453136100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1453136100
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1648930071
Short name T790
Test name
Test status
Simulation time 10053513900 ps
CPU time 50.79 seconds
Started Feb 07 01:51:40 PM PST 24
Finished Feb 07 01:52:32 PM PST 24
Peak memory 276004 kb
Host smart-24dbec98-930e-4321-953f-beb58ff2a50a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648930071 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1648930071
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.3613141239
Short name T701
Test name
Test status
Simulation time 16476600 ps
CPU time 13.62 seconds
Started Feb 07 01:51:42 PM PST 24
Finished Feb 07 01:51:56 PM PST 24
Peak memory 264052 kb
Host smart-12f571b9-4615-4413-a6ce-0dbb517bfd89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613141239 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.3613141239
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.4011512413
Short name T404
Test name
Test status
Simulation time 3043230400 ps
CPU time 64.29 seconds
Started Feb 07 01:51:34 PM PST 24
Finished Feb 07 01:52:39 PM PST 24
Peak memory 258364 kb
Host smart-ad754afd-4341-44a7-8316-8e424527fb71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011512413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.4011512413
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3684444336
Short name T917
Test name
Test status
Simulation time 1225618400 ps
CPU time 161.02 seconds
Started Feb 07 01:51:30 PM PST 24
Finished Feb 07 01:54:11 PM PST 24
Peak memory 292328 kb
Host smart-7aa2508d-feac-4a33-a153-0a633c23495b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684444336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3684444336
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1978788577
Short name T327
Test name
Test status
Simulation time 6762424400 ps
CPU time 62.34 seconds
Started Feb 07 01:51:27 PM PST 24
Finished Feb 07 01:52:30 PM PST 24
Peak memory 258152 kb
Host smart-46e65aaf-4375-40f7-9477-d8197f171273
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978788577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
978788577
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.489873649
Short name T926
Test name
Test status
Simulation time 28968400 ps
CPU time 13.75 seconds
Started Feb 07 01:51:39 PM PST 24
Finished Feb 07 01:51:54 PM PST 24
Peak memory 264052 kb
Host smart-195746f5-1588-411d-9ab7-e1ef917b7b37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489873649 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.489873649
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.4179903783
Short name T681
Test name
Test status
Simulation time 5317968200 ps
CPU time 151.53 seconds
Started Feb 07 01:51:32 PM PST 24
Finished Feb 07 01:54:05 PM PST 24
Peak memory 259992 kb
Host smart-2c141f7e-cee3-42bd-b32e-eb7d8dfd2859
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179903783 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.4179903783
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.633082476
Short name T848
Test name
Test status
Simulation time 157186200 ps
CPU time 112.67 seconds
Started Feb 07 01:51:34 PM PST 24
Finished Feb 07 01:53:28 PM PST 24
Peak memory 258316 kb
Host smart-ef43d6cd-8522-4e43-9a02-fa12c9a8ec7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633082476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot
p_reset.633082476
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.2977321807
Short name T845
Test name
Test status
Simulation time 214169600 ps
CPU time 15.62 seconds
Started Feb 07 01:51:31 PM PST 24
Finished Feb 07 01:51:48 PM PST 24
Peak memory 264028 kb
Host smart-036312f1-057d-45bc-9753-33a14e6e7ccf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977321807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.2977321807
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3871974534
Short name T22
Test name
Test status
Simulation time 186301600 ps
CPU time 1026.65 seconds
Started Feb 07 01:51:25 PM PST 24
Finished Feb 07 02:08:33 PM PST 24
Peak memory 285224 kb
Host smart-6997f591-d73b-4fcd-bf63-707a05a35881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871974534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3871974534
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.4000353960
Short name T539
Test name
Test status
Simulation time 124826300 ps
CPU time 39.04 seconds
Started Feb 07 01:51:32 PM PST 24
Finished Feb 07 01:52:12 PM PST 24
Peak memory 272392 kb
Host smart-0eaf8f3d-cf1a-443b-ba0f-91ff1fdbbee2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000353960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.4000353960
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1865177971
Short name T690
Test name
Test status
Simulation time 4611426600 ps
CPU time 113.02 seconds
Started Feb 07 01:51:34 PM PST 24
Finished Feb 07 01:53:28 PM PST 24
Peak memory 280468 kb
Host smart-dda01a78-75d9-42de-b1f8-804d135a4a18
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865177971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.1865177971
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.769925520
Short name T771
Test name
Test status
Simulation time 6990928900 ps
CPU time 521.14 seconds
Started Feb 07 01:51:30 PM PST 24
Finished Feb 07 02:00:12 PM PST 24
Peak memory 312584 kb
Host smart-f1a8a5ce-dea2-49b2-b800-6aaf2dca7b01
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769925520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ct
rl_rw.769925520
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1100056516
Short name T555
Test name
Test status
Simulation time 95158800 ps
CPU time 31.32 seconds
Started Feb 07 01:51:29 PM PST 24
Finished Feb 07 01:52:02 PM PST 24
Peak memory 272448 kb
Host smart-130e29b8-d9ef-46e6-a07e-740c37682850
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100056516 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1100056516
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.293148462
Short name T793
Test name
Test status
Simulation time 58256900 ps
CPU time 123.74 seconds
Started Feb 07 01:51:23 PM PST 24
Finished Feb 07 01:53:28 PM PST 24
Peak memory 275332 kb
Host smart-5e6a2602-45e8-4c5d-98cf-1206a03de7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293148462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.293148462
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.729355282
Short name T785
Test name
Test status
Simulation time 4983312400 ps
CPU time 212.53 seconds
Started Feb 07 01:51:28 PM PST 24
Finished Feb 07 01:55:02 PM PST 24
Peak memory 264028 kb
Host smart-d6a62587-f2f6-4f9b-beed-70e13352bdbd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729355282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_wo.729355282
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1286105095
Short name T197
Test name
Test status
Simulation time 232487000 ps
CPU time 14.34 seconds
Started Feb 07 01:51:47 PM PST 24
Finished Feb 07 01:52:03 PM PST 24
Peak memory 264044 kb
Host smart-74025538-6d50-431c-85c8-83a7173c6d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286105095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1286105095
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3409180343
Short name T83
Test name
Test status
Simulation time 10043771800 ps
CPU time 78.58 seconds
Started Feb 07 01:51:54 PM PST 24
Finished Feb 07 01:53:14 PM PST 24
Peak memory 264100 kb
Host smart-efbc02d1-4050-40f5-9582-c938de59df31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409180343 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3409180343
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1800555259
Short name T914
Test name
Test status
Simulation time 18816600 ps
CPU time 13.55 seconds
Started Feb 07 01:51:55 PM PST 24
Finished Feb 07 01:52:09 PM PST 24
Peak memory 263960 kb
Host smart-9a235c51-1090-422e-8410-cdef1a7112ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800555259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1800555259
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.2497029115
Short name T521
Test name
Test status
Simulation time 4503445500 ps
CPU time 158.43 seconds
Started Feb 07 01:51:54 PM PST 24
Finished Feb 07 01:54:34 PM PST 24
Peak memory 291944 kb
Host smart-5117cf55-081d-4fe6-b779-7e0a51541da3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497029115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.2497029115
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.240839119
Short name T696
Test name
Test status
Simulation time 17328082200 ps
CPU time 219.18 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:55:37 PM PST 24
Peak memory 283040 kb
Host smart-066c094a-6ebd-4040-8b4e-cbf1814227c3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240839119 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.240839119
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.2241660381
Short name T714
Test name
Test status
Simulation time 8120083700 ps
CPU time 71 seconds
Started Feb 07 01:51:40 PM PST 24
Finished Feb 07 01:52:51 PM PST 24
Peak memory 259064 kb
Host smart-879a585b-e67f-46f9-85e6-d13968a27d70
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241660381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2
241660381
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1775244595
Short name T884
Test name
Test status
Simulation time 15730900 ps
CPU time 13.96 seconds
Started Feb 07 01:51:55 PM PST 24
Finished Feb 07 01:52:10 PM PST 24
Peak memory 264048 kb
Host smart-c9174321-0d5a-4e22-b862-c0cf2d451191
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775244595 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1775244595
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1299476929
Short name T137
Test name
Test status
Simulation time 36092998200 ps
CPU time 525.63 seconds
Started Feb 07 01:51:43 PM PST 24
Finished Feb 07 02:00:30 PM PST 24
Peak memory 272756 kb
Host smart-202581f9-69b6-46b5-8272-408f472ccfc7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299476929 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1299476929
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.3925547502
Short name T89
Test name
Test status
Simulation time 37760200 ps
CPU time 134.42 seconds
Started Feb 07 01:51:38 PM PST 24
Finished Feb 07 01:53:54 PM PST 24
Peak memory 257992 kb
Host smart-762b2778-ecc7-4378-a6e7-c8479939b125
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925547502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.3925547502
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.4276629848
Short name T607
Test name
Test status
Simulation time 263041900 ps
CPU time 329.42 seconds
Started Feb 07 01:51:39 PM PST 24
Finished Feb 07 01:57:10 PM PST 24
Peak memory 264016 kb
Host smart-285fb277-1d12-46be-80b5-d21699dc6199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276629848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.4276629848
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.923052838
Short name T730
Test name
Test status
Simulation time 146490600 ps
CPU time 620.98 seconds
Started Feb 07 01:51:38 PM PST 24
Finished Feb 07 02:02:00 PM PST 24
Peak memory 281464 kb
Host smart-0b06a188-c0c8-4a7f-921d-106a16acdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923052838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.923052838
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.480238833
Short name T631
Test name
Test status
Simulation time 429942300 ps
CPU time 36.78 seconds
Started Feb 07 01:51:56 PM PST 24
Finished Feb 07 01:52:34 PM PST 24
Peak memory 265236 kb
Host smart-3c90878d-2e1a-46c8-9bee-a281812fc74e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480238833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_re_evict.480238833
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.4194362981
Short name T486
Test name
Test status
Simulation time 1911792100 ps
CPU time 98.16 seconds
Started Feb 07 01:52:02 PM PST 24
Finished Feb 07 01:53:41 PM PST 24
Peak memory 279200 kb
Host smart-f1498491-fd84-43f5-b9ab-7ee801f3c403
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194362981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.4194362981
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2223115875
Short name T862
Test name
Test status
Simulation time 6449025900 ps
CPU time 543.32 seconds
Started Feb 07 01:51:54 PM PST 24
Finished Feb 07 02:00:58 PM PST 24
Peak memory 313224 kb
Host smart-1a4dd2a9-499d-4c96-8f44-f739233c2be5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223115875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.2223115875
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.303640753
Short name T718
Test name
Test status
Simulation time 30106800 ps
CPU time 31.51 seconds
Started Feb 07 01:51:55 PM PST 24
Finished Feb 07 01:52:27 PM PST 24
Peak memory 272372 kb
Host smart-59e31ef8-d35b-4319-b763-b1f2d48d23e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303640753 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.303640753
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2628015494
Short name T21
Test name
Test status
Simulation time 1503849200 ps
CPU time 59.19 seconds
Started Feb 07 01:51:53 PM PST 24
Finished Feb 07 01:52:53 PM PST 24
Peak memory 261832 kb
Host smart-87c6b58d-4410-46d9-8d05-6009f3b1f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628015494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2628015494
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.1413519018
Short name T554
Test name
Test status
Simulation time 2183339400 ps
CPU time 169.82 seconds
Started Feb 07 01:51:41 PM PST 24
Finished Feb 07 01:54:32 PM PST 24
Peak memory 264040 kb
Host smart-958977f1-7e5e-4999-825c-397489957111
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413519018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.1413519018
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3279848913
Short name T720
Test name
Test status
Simulation time 137360100 ps
CPU time 13.76 seconds
Started Feb 07 01:52:07 PM PST 24
Finished Feb 07 01:52:21 PM PST 24
Peak memory 264084 kb
Host smart-8642c901-eab6-47e0-a469-c92d5cfc9d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279848913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3279848913
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.1124961125
Short name T676
Test name
Test status
Simulation time 16033100 ps
CPU time 16.24 seconds
Started Feb 07 01:52:04 PM PST 24
Finished Feb 07 01:52:21 PM PST 24
Peak memory 273556 kb
Host smart-8c399e00-3a9f-4304-8bf3-3318eb1164e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124961125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1124961125
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3239361254
Short name T859
Test name
Test status
Simulation time 10017996800 ps
CPU time 82.69 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:53:40 PM PST 24
Peak memory 290076 kb
Host smart-261475bb-9813-44ee-a303-d67b3213a6ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239361254 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3239361254
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2333150716
Short name T400
Test name
Test status
Simulation time 26309500 ps
CPU time 13.77 seconds
Started Feb 07 01:52:04 PM PST 24
Finished Feb 07 01:52:18 PM PST 24
Peak memory 263084 kb
Host smart-6b3681a8-d91b-48f5-ae2f-baed80065e1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333150716 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2333150716
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3286700829
Short name T109
Test name
Test status
Simulation time 40126670200 ps
CPU time 728.16 seconds
Started Feb 07 01:52:00 PM PST 24
Finished Feb 07 02:04:10 PM PST 24
Peak memory 258180 kb
Host smart-2b0fa6f3-2dcd-4efb-b2f4-478b951100f5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286700829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3286700829
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.977587366
Short name T781
Test name
Test status
Simulation time 588859900 ps
CPU time 31.74 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:52:30 PM PST 24
Peak memory 259540 kb
Host smart-66d4b083-f15e-4c4b-a40b-a41c9e83644a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977587366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_h
w_sec_otp.977587366
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.15178879
Short name T41
Test name
Test status
Simulation time 8501624600 ps
CPU time 203.16 seconds
Started Feb 07 01:52:01 PM PST 24
Finished Feb 07 01:55:25 PM PST 24
Peak memory 290272 kb
Host smart-9c93e57c-2a7e-4e51-ae46-57c19e39ad08
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178879 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.15178879
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.598035478
Short name T618
Test name
Test status
Simulation time 978993200 ps
CPU time 78.88 seconds
Started Feb 07 01:52:05 PM PST 24
Finished Feb 07 01:53:25 PM PST 24
Peak memory 258196 kb
Host smart-a1aa9603-4c0a-4298-9c5a-eb92fef19397
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598035478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.598035478
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1685993429
Short name T143
Test name
Test status
Simulation time 15072153700 ps
CPU time 280.54 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:56:38 PM PST 24
Peak memory 272708 kb
Host smart-245fed80-902e-4f1e-9dda-fbd4df51ecd3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685993429 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.1685993429
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.772812874
Short name T432
Test name
Test status
Simulation time 40950700 ps
CPU time 133.93 seconds
Started Feb 07 01:52:00 PM PST 24
Finished Feb 07 01:54:15 PM PST 24
Peak memory 258028 kb
Host smart-d4bf2ed8-a53c-46e0-856c-70b8abe40a7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772812874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.772812874
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3730941607
Short name T854
Test name
Test status
Simulation time 88892400 ps
CPU time 198.48 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:55:16 PM PST 24
Peak memory 263988 kb
Host smart-71151af4-b953-4fe4-ab88-06f4179feecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730941607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3730941607
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3315927117
Short name T606
Test name
Test status
Simulation time 82262300 ps
CPU time 14.15 seconds
Started Feb 07 01:51:57 PM PST 24
Finished Feb 07 01:52:12 PM PST 24
Peak memory 264072 kb
Host smart-0bbbab8d-724c-4cbc-9e96-41eaddcf31fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315927117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.3315927117
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1454128802
Short name T802
Test name
Test status
Simulation time 455772200 ps
CPU time 638.72 seconds
Started Feb 07 01:51:54 PM PST 24
Finished Feb 07 02:02:34 PM PST 24
Peak memory 280532 kb
Host smart-d592df2f-5886-449c-9d2c-23e4b937200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454128802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1454128802
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1343016491
Short name T700
Test name
Test status
Simulation time 1285875900 ps
CPU time 93.46 seconds
Started Feb 07 01:51:52 PM PST 24
Finished Feb 07 01:53:26 PM PST 24
Peak memory 280568 kb
Host smart-7ad078a8-c560-49ab-9e7e-2ea3dfaeda14
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343016491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.1343016491
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.311071589
Short name T805
Test name
Test status
Simulation time 3546468900 ps
CPU time 500.2 seconds
Started Feb 07 01:51:58 PM PST 24
Finished Feb 07 02:00:19 PM PST 24
Peak memory 313288 kb
Host smart-46ffc532-ad9f-413e-96c6-9acf383f7834
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311071589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ct
rl_rw.311071589
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.2174684043
Short name T320
Test name
Test status
Simulation time 1899677700 ps
CPU time 75.01 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:53:32 PM PST 24
Peak memory 262764 kb
Host smart-46dfd8a5-6038-4bb0-ab57-7745e505e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174684043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2174684043
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1170704643
Short name T146
Test name
Test status
Simulation time 59597500 ps
CPU time 123.18 seconds
Started Feb 07 01:51:47 PM PST 24
Finished Feb 07 01:53:51 PM PST 24
Peak memory 274480 kb
Host smart-0da6ab1c-8106-4d99-9d78-b597ab5fd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170704643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1170704643
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1252975608
Short name T765
Test name
Test status
Simulation time 17068200 ps
CPU time 15.65 seconds
Started Feb 07 01:52:13 PM PST 24
Finished Feb 07 01:52:29 PM PST 24
Peak memory 283044 kb
Host smart-198e1db5-bf0f-45b3-9236-cda82ea6aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252975608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1252975608
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3175284047
Short name T512
Test name
Test status
Simulation time 15038300 ps
CPU time 14.11 seconds
Started Feb 07 01:52:17 PM PST 24
Finished Feb 07 01:52:32 PM PST 24
Peak memory 264100 kb
Host smart-004f2a07-b302-436e-b130-35df8cfcf609
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175284047 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3175284047
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.806160644
Short name T738
Test name
Test status
Simulation time 230226554900 ps
CPU time 876.32 seconds
Started Feb 07 01:52:05 PM PST 24
Finished Feb 07 02:06:42 PM PST 24
Peak memory 258272 kb
Host smart-94888055-b0fe-4a0f-b21c-92b1af9caad8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806160644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_hw_rma_reset.806160644
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4231179846
Short name T564
Test name
Test status
Simulation time 8359848100 ps
CPU time 159.18 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:54:56 PM PST 24
Peak memory 259596 kb
Host smart-2216d96f-0739-4b02-9cb1-b5a95f0692c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231179846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.4231179846
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2224870518
Short name T442
Test name
Test status
Simulation time 16518300400 ps
CPU time 187.72 seconds
Started Feb 07 01:52:14 PM PST 24
Finished Feb 07 01:55:22 PM PST 24
Peak memory 283024 kb
Host smart-53640d8c-bd7d-4ce2-85ca-30e363bef737
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224870518 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2224870518
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.856326518
Short name T658
Test name
Test status
Simulation time 6507929200 ps
CPU time 69.63 seconds
Started Feb 07 01:52:05 PM PST 24
Finished Feb 07 01:53:16 PM PST 24
Peak memory 258028 kb
Host smart-3948d28e-888a-4624-9b76-cccfb64eb224
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856326518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.856326518
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1338461711
Short name T632
Test name
Test status
Simulation time 24995700 ps
CPU time 14.06 seconds
Started Feb 07 01:52:11 PM PST 24
Finished Feb 07 01:52:26 PM PST 24
Peak memory 263956 kb
Host smart-f7b26e16-d0cc-4dce-b3d5-bfc23b604015
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338461711 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1338461711
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2932534977
Short name T753
Test name
Test status
Simulation time 23932200 ps
CPU time 13.5 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:52:31 PM PST 24
Peak memory 264032 kb
Host smart-ca42c7d2-aeb8-4321-9291-037a5e205d1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932534977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2932534977
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.3887573215
Short name T849
Test name
Test status
Simulation time 464374900 ps
CPU time 922.19 seconds
Started Feb 07 01:52:09 PM PST 24
Finished Feb 07 02:07:32 PM PST 24
Peak memory 284756 kb
Host smart-e58dd7fc-1cd9-49ab-bae2-1f94ff010d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887573215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3887573215
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.3995703233
Short name T807
Test name
Test status
Simulation time 82701300 ps
CPU time 29.82 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:52:47 PM PST 24
Peak memory 272376 kb
Host smart-599661f0-1223-4f4e-8c27-4fcd740c2f24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995703233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.3995703233
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3252621761
Short name T608
Test name
Test status
Simulation time 2492050500 ps
CPU time 107.62 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 01:54:05 PM PST 24
Peak memory 280536 kb
Host smart-51008f3e-c2b7-42c7-bda7-ba6b986c5909
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252621761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.3252621761
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3053862714
Short name T25
Test name
Test status
Simulation time 3611089600 ps
CPU time 554.33 seconds
Started Feb 07 01:52:16 PM PST 24
Finished Feb 07 02:01:32 PM PST 24
Peak memory 312272 kb
Host smart-4a823c53-2752-462f-b971-1d9261d135f2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053862714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.3053862714
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.693403965
Short name T800
Test name
Test status
Simulation time 151625200 ps
CPU time 30.8 seconds
Started Feb 07 01:52:12 PM PST 24
Finished Feb 07 01:52:43 PM PST 24
Peak memory 272356 kb
Host smart-78741444-69fc-4485-9ed0-976b37e3c5d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693403965 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.693403965
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.4210901495
Short name T825
Test name
Test status
Simulation time 132587800 ps
CPU time 172.6 seconds
Started Feb 07 01:52:06 PM PST 24
Finished Feb 07 01:54:59 PM PST 24
Peak memory 275244 kb
Host smart-ac49e6c7-425e-402b-977f-0c80d96c9451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210901495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.4210901495
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.1508868478
Short name T617
Test name
Test status
Simulation time 8510041000 ps
CPU time 168.55 seconds
Started Feb 07 01:52:14 PM PST 24
Finished Feb 07 01:55:03 PM PST 24
Peak memory 263972 kb
Host smart-64fd6fbd-f1ab-4a21-96f9-212a0b9834f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508868478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.1508868478
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.4027662368
Short name T212
Test name
Test status
Simulation time 158947200 ps
CPU time 14.19 seconds
Started Feb 07 01:52:39 PM PST 24
Finished Feb 07 01:52:54 PM PST 24
Peak memory 264104 kb
Host smart-5ff055b0-a390-4014-ab39-a57ff11950a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027662368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
4027662368
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.3801375276
Short name T18
Test name
Test status
Simulation time 57935100 ps
CPU time 15.84 seconds
Started Feb 07 01:52:44 PM PST 24
Finished Feb 07 01:53:01 PM PST 24
Peak memory 273552 kb
Host smart-00f8c9ca-2ace-4f38-8aaf-ec61c7f8d37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801375276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3801375276
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.2816338159
Short name T675
Test name
Test status
Simulation time 30667900 ps
CPU time 22.07 seconds
Started Feb 07 01:52:39 PM PST 24
Finished Feb 07 01:53:02 PM PST 24
Peak memory 272316 kb
Host smart-e9f0fd64-6d7b-4794-ac80-0447b709ee9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816338159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.2816338159
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3410913569
Short name T666
Test name
Test status
Simulation time 10040989800 ps
CPU time 59.93 seconds
Started Feb 07 01:52:39 PM PST 24
Finished Feb 07 01:53:40 PM PST 24
Peak memory 285948 kb
Host smart-8e0b10e8-2473-4247-a60a-81b80ea3b858
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410913569 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3410913569
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2407703729
Short name T390
Test name
Test status
Simulation time 16958900 ps
CPU time 13.9 seconds
Started Feb 07 01:52:40 PM PST 24
Finished Feb 07 01:52:54 PM PST 24
Peak memory 263952 kb
Host smart-c1c25dd4-05c8-4ca9-aec3-3ecbcb24decd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407703729 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2407703729
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1043391511
Short name T50
Test name
Test status
Simulation time 160193841700 ps
CPU time 798.96 seconds
Started Feb 07 01:52:22 PM PST 24
Finished Feb 07 02:05:42 PM PST 24
Peak memory 258288 kb
Host smart-4a16a2a3-1ac6-4a26-90a0-c12d1144ad51
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043391511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1043391511
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2651331940
Short name T378
Test name
Test status
Simulation time 6787998500 ps
CPU time 53.3 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:53:18 PM PST 24
Peak memory 259388 kb
Host smart-0ffcfd72-4488-40c6-99e8-8256f4facf43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651331940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2651331940
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.576630321
Short name T663
Test name
Test status
Simulation time 9871844300 ps
CPU time 178.09 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:55:22 PM PST 24
Peak memory 292036 kb
Host smart-c375b333-0d36-48ba-82b4-83da31d5dda6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576630321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas
h_ctrl_intr_rd.576630321
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3300724685
Short name T628
Test name
Test status
Simulation time 35790907900 ps
CPU time 236.32 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 282820 kb
Host smart-d04399a5-f632-4270-ae90-10cad52035d9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300724685 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3300724685
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.2661385016
Short name T582
Test name
Test status
Simulation time 4029817900 ps
CPU time 86.81 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:53:51 PM PST 24
Peak memory 258136 kb
Host smart-18a7c5a7-c3fb-4dfc-ada0-a58a6fc4f9fd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661385016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2
661385016
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2115515527
Short name T899
Test name
Test status
Simulation time 48176100 ps
CPU time 13.36 seconds
Started Feb 07 01:52:38 PM PST 24
Finished Feb 07 01:52:52 PM PST 24
Peak memory 264044 kb
Host smart-516f814f-54a7-42d2-853e-e575d0b5083d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115515527 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2115515527
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.872570430
Short name T138
Test name
Test status
Simulation time 160442364800 ps
CPU time 1140.77 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 02:11:26 PM PST 24
Peak memory 273192 kb
Host smart-ac47b644-bd16-4228-bcf8-aba41d39b409
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872570430 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.872570430
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.744138607
Short name T77
Test name
Test status
Simulation time 41181600 ps
CPU time 132.35 seconds
Started Feb 07 01:52:26 PM PST 24
Finished Feb 07 01:54:39 PM PST 24
Peak memory 258008 kb
Host smart-7670b7da-82eb-4755-a75e-5efb1b3e056e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744138607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot
p_reset.744138607
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2475947932
Short name T646
Test name
Test status
Simulation time 777841200 ps
CPU time 176.96 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 01:55:22 PM PST 24
Peak memory 264092 kb
Host smart-40349fa8-3ef0-4e25-9338-5983c863ff8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475947932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2475947932
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2913513709
Short name T722
Test name
Test status
Simulation time 18945000 ps
CPU time 13.74 seconds
Started Feb 07 01:52:25 PM PST 24
Finished Feb 07 01:52:40 PM PST 24
Peak memory 264048 kb
Host smart-57888393-13a2-40fd-9625-361a3cdfc62e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913513709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.2913513709
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1495180232
Short name T830
Test name
Test status
Simulation time 234129100 ps
CPU time 500.34 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 281636 kb
Host smart-dd47dec7-69fa-4186-bc63-c4836aaa7b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495180232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1495180232
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.3225847885
Short name T877
Test name
Test status
Simulation time 127128500 ps
CPU time 37.85 seconds
Started Feb 07 01:52:43 PM PST 24
Finished Feb 07 01:53:22 PM PST 24
Peak memory 272308 kb
Host smart-d1c9d282-8fad-4d1e-8a91-67d40d727438
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225847885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.3225847885
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1730633127
Short name T903
Test name
Test status
Simulation time 8715688000 ps
CPU time 555.82 seconds
Started Feb 07 01:52:24 PM PST 24
Finished Feb 07 02:01:40 PM PST 24
Peak memory 313244 kb
Host smart-c5d05f31-585a-4eeb-9c83-59a9635cede0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730633127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.1730633127
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.1746886275
Short name T697
Test name
Test status
Simulation time 78091700 ps
CPU time 33.09 seconds
Started Feb 07 01:52:28 PM PST 24
Finished Feb 07 01:53:02 PM PST 24
Peak memory 272412 kb
Host smart-a5f1d6e8-9efd-49c5-a91e-bd3b59b6b741
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746886275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.1746886275
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3871494360
Short name T314
Test name
Test status
Simulation time 2859711100 ps
CPU time 68.04 seconds
Started Feb 07 01:52:41 PM PST 24
Finished Feb 07 01:53:50 PM PST 24
Peak memory 262796 kb
Host smart-9386891b-4633-4c23-b05a-156ac704884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871494360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3871494360
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.363701715
Short name T413
Test name
Test status
Simulation time 20131900 ps
CPU time 100.82 seconds
Started Feb 07 01:52:23 PM PST 24
Finished Feb 07 01:54:04 PM PST 24
Peak memory 274728 kb
Host smart-9c72052b-4ca4-4b0a-a911-ab81538579ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363701715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.363701715
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1844037573
Short name T815
Test name
Test status
Simulation time 4364206900 ps
CPU time 187.55 seconds
Started Feb 07 01:52:25 PM PST 24
Finished Feb 07 01:55:34 PM PST 24
Peak memory 264084 kb
Host smart-8430bd33-55b2-4e52-bf58-30eb5e0e1327
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844037573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.1844037573
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2293055725
Short name T818
Test name
Test status
Simulation time 168920200 ps
CPU time 14.01 seconds
Started Feb 07 01:53:00 PM PST 24
Finished Feb 07 01:53:14 PM PST 24
Peak memory 264044 kb
Host smart-662e4f1e-a2e1-4fa1-8aea-906f521e7b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293055725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2293055725
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3616914401
Short name T205
Test name
Test status
Simulation time 16333700 ps
CPU time 15.77 seconds
Started Feb 07 01:53:00 PM PST 24
Finished Feb 07 01:53:17 PM PST 24
Peak memory 273688 kb
Host smart-e92ab9cc-2c54-4a26-b861-fff81883b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616914401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3616914401
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1121913213
Short name T673
Test name
Test status
Simulation time 10034203600 ps
CPU time 57.16 seconds
Started Feb 07 01:52:54 PM PST 24
Finished Feb 07 01:53:52 PM PST 24
Peak memory 290528 kb
Host smart-e823c170-8271-4153-8c68-f18077564aa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121913213 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1121913213
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2838823258
Short name T527
Test name
Test status
Simulation time 25574700 ps
CPU time 13.74 seconds
Started Feb 07 01:52:57 PM PST 24
Finished Feb 07 01:53:11 PM PST 24
Peak memory 264192 kb
Host smart-d00ae6d3-be9f-4eb1-bb73-a543bea86761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838823258 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2838823258
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1608952819
Short name T641
Test name
Test status
Simulation time 2337378100 ps
CPU time 103.62 seconds
Started Feb 07 01:52:45 PM PST 24
Finished Feb 07 01:54:29 PM PST 24
Peak memory 259396 kb
Host smart-cf5e6b66-1139-45cd-9754-98c20f8ac879
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608952819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1608952819
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.274908120
Short name T436
Test name
Test status
Simulation time 175098311700 ps
CPU time 322.56 seconds
Started Feb 07 01:52:47 PM PST 24
Finished Feb 07 01:58:11 PM PST 24
Peak memory 292132 kb
Host smart-e9e001bb-5903-4901-ae31-e31fdadf8521
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274908120 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.274908120
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1498749967
Short name T73
Test name
Test status
Simulation time 47797300 ps
CPU time 13.64 seconds
Started Feb 07 01:52:56 PM PST 24
Finished Feb 07 01:53:10 PM PST 24
Peak memory 264076 kb
Host smart-e35e2d7d-b33f-4c9b-8af5-2b4a26f8eb75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498749967 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1498749967
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.700841256
Short name T152
Test name
Test status
Simulation time 88074200 ps
CPU time 150.07 seconds
Started Feb 07 01:52:37 PM PST 24
Finished Feb 07 01:55:07 PM PST 24
Peak memory 277184 kb
Host smart-d6b8b29d-6de9-4401-8b72-f9757e284112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700841256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.700841256
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3389033380
Short name T44
Test name
Test status
Simulation time 2594974100 ps
CPU time 109.4 seconds
Started Feb 07 01:52:49 PM PST 24
Finished Feb 07 01:54:39 PM PST 24
Peak memory 280500 kb
Host smart-11fdd0fe-b5dc-46a9-b9ea-3ba76ed6d91e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389033380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.3389033380
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.3943185853
Short name T288
Test name
Test status
Simulation time 75380900 ps
CPU time 31.91 seconds
Started Feb 07 01:52:39 PM PST 24
Finished Feb 07 01:53:12 PM PST 24
Peak memory 272324 kb
Host smart-a09451ec-a694-40c2-97ee-ecf273f82d2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943185853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.3943185853
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1566807371
Short name T745
Test name
Test status
Simulation time 104772200 ps
CPU time 31.69 seconds
Started Feb 07 01:52:55 PM PST 24
Finished Feb 07 01:53:27 PM PST 24
Peak memory 270956 kb
Host smart-cfa515a2-eecb-4065-b0a7-728d66dc8a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566807371 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1566807371
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3272189738
Short name T24
Test name
Test status
Simulation time 354818400 ps
CPU time 52.35 seconds
Started Feb 07 01:52:54 PM PST 24
Finished Feb 07 01:53:47 PM PST 24
Peak memory 263820 kb
Host smart-33fba0c8-61ed-4bac-9b80-5042a9815f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272189738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3272189738
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3434438972
Short name T803
Test name
Test status
Simulation time 22463700 ps
CPU time 126.62 seconds
Started Feb 07 01:52:39 PM PST 24
Finished Feb 07 01:54:46 PM PST 24
Peak memory 275596 kb
Host smart-8378b4ff-9655-4c2a-918b-9cb0b3302a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434438972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3434438972
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.982435848
Short name T388
Test name
Test status
Simulation time 8993497800 ps
CPU time 202.77 seconds
Started Feb 07 01:52:48 PM PST 24
Finished Feb 07 01:56:11 PM PST 24
Peak memory 264012 kb
Host smart-66e453f4-9320-4a09-9fb8-54ee5405cb47
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982435848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_wo.982435848
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.1178100983
Short name T755
Test name
Test status
Simulation time 64472600 ps
CPU time 13.82 seconds
Started Feb 07 01:48:01 PM PST 24
Finished Feb 07 01:48:21 PM PST 24
Peak memory 264084 kb
Host smart-aa57ec61-9e9e-40cc-820f-36cdd9b6120e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178100983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1
178100983
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1185329161
Short name T258
Test name
Test status
Simulation time 21873200 ps
CPU time 13.82 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:48:21 PM PST 24
Peak memory 264064 kb
Host smart-29a03881-248c-41ab-9304-d736367fe619
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185329161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1185329161
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.2093371287
Short name T864
Test name
Test status
Simulation time 18751600 ps
CPU time 13.64 seconds
Started Feb 07 01:48:00 PM PST 24
Finished Feb 07 01:48:20 PM PST 24
Peak memory 273672 kb
Host smart-b8ad2854-fff0-41ad-89fc-682a43e4e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093371287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2093371287
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.1362370937
Short name T71
Test name
Test status
Simulation time 195481500 ps
CPU time 106.77 seconds
Started Feb 07 01:48:08 PM PST 24
Finished Feb 07 01:49:57 PM PST 24
Peak memory 280528 kb
Host smart-c2dfa531-8f0a-4bd9-813e-e75d094fe089
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362370937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.1362370937
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.1441367482
Short name T484
Test name
Test status
Simulation time 21774100 ps
CPU time 22 seconds
Started Feb 07 01:47:46 PM PST 24
Finished Feb 07 01:48:10 PM PST 24
Peak memory 272388 kb
Host smart-de4eab3d-7697-492a-aa90-bc992ca489a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441367482 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.1441367482
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.955493557
Short name T135
Test name
Test status
Simulation time 17394609800 ps
CPU time 361.48 seconds
Started Feb 07 01:47:48 PM PST 24
Finished Feb 07 01:53:51 PM PST 24
Peak memory 259544 kb
Host smart-29e28378-5538-4970-a464-e88be423d907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955493557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.955493557
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1619812461
Short name T230
Test name
Test status
Simulation time 12806347100 ps
CPU time 2428.07 seconds
Started Feb 07 01:47:46 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 263964 kb
Host smart-50af320e-5cfb-4614-ad51-1a2f4306efc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619812461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1619812461
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.703063775
Short name T475
Test name
Test status
Simulation time 6462908600 ps
CPU time 2113.13 seconds
Started Feb 07 01:47:55 PM PST 24
Finished Feb 07 02:23:09 PM PST 24
Peak memory 264044 kb
Host smart-18144720-d10c-4788-a36a-a49ce8cc132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703063775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.703063775
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2278056684
Short name T231
Test name
Test status
Simulation time 397023500 ps
CPU time 972.8 seconds
Started Feb 07 01:47:49 PM PST 24
Finished Feb 07 02:04:03 PM PST 24
Peak memory 272180 kb
Host smart-a7752706-e443-460f-9fab-fc4510043527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278056684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2278056684
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.144120265
Short name T642
Test name
Test status
Simulation time 8217569400 ps
CPU time 25.09 seconds
Started Feb 07 01:47:46 PM PST 24
Finished Feb 07 01:48:13 PM PST 24
Peak memory 264072 kb
Host smart-f4e4bcea-2751-47e0-852b-ecbb9a06791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144120265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.144120265
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.668949297
Short name T121
Test name
Test status
Simulation time 1011525600 ps
CPU time 37.54 seconds
Started Feb 07 01:47:59 PM PST 24
Finished Feb 07 01:48:40 PM PST 24
Peak memory 272252 kb
Host smart-09075ec8-88c6-4b48-a8a1-58c3906dea5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668949297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.668949297
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1434768206
Short name T644
Test name
Test status
Simulation time 274710212000 ps
CPU time 2289.05 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 02:25:58 PM PST 24
Peak memory 263984 kb
Host smart-10e5b100-d6b0-4585-a0d4-36a0f08bbc7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434768206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.1434768206
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4267960136
Short name T869
Test name
Test status
Simulation time 59965200 ps
CPU time 46.99 seconds
Started Feb 07 01:47:45 PM PST 24
Finished Feb 07 01:48:34 PM PST 24
Peak memory 262960 kb
Host smart-85e084c1-d607-45c2-a822-506582157c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267960136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4267960136
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1082438109
Short name T165
Test name
Test status
Simulation time 10020142600 ps
CPU time 84.59 seconds
Started Feb 07 01:48:15 PM PST 24
Finished Feb 07 01:49:44 PM PST 24
Peak memory 289988 kb
Host smart-df8b9ce7-4cb2-4966-8976-1aafbe183458
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082438109 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1082438109
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.32229322
Short name T588
Test name
Test status
Simulation time 30314400 ps
CPU time 13.52 seconds
Started Feb 07 01:48:02 PM PST 24
Finished Feb 07 01:48:20 PM PST 24
Peak memory 264236 kb
Host smart-5bdfde1a-8a89-4255-b291-88ec00977786
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32229322 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.32229322
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.234737039
Short name T381
Test name
Test status
Simulation time 27270582200 ps
CPU time 208 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:51:17 PM PST 24
Peak memory 258388 kb
Host smart-049f97e3-07d0-4276-84a7-3cafff712ff6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234737039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.234737039
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1221533336
Short name T573
Test name
Test status
Simulation time 4498824400 ps
CPU time 156.07 seconds
Started Feb 07 01:47:58 PM PST 24
Finished Feb 07 01:50:35 PM PST 24
Peak memory 291240 kb
Host smart-f2ee555d-5486-4238-ac61-9ca4a88ca9a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221533336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1221533336
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.672036253
Short name T332
Test name
Test status
Simulation time 70156063100 ps
CPU time 257.03 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:52:06 PM PST 24
Peak memory 283128 kb
Host smart-654fc726-6577-44b3-93bd-531987a7f052
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672036253 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.672036253
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.917845128
Short name T930
Test name
Test status
Simulation time 7699330600 ps
CPU time 111.63 seconds
Started Feb 07 01:47:51 PM PST 24
Finished Feb 07 01:49:43 PM PST 24
Peak memory 263988 kb
Host smart-d09eb58f-fdba-4d09-9e0e-57ea45b6a743
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917845128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.917845128
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2486012653
Short name T595
Test name
Test status
Simulation time 162889662900 ps
CPU time 454.79 seconds
Started Feb 07 01:47:51 PM PST 24
Finished Feb 07 01:55:27 PM PST 24
Peak memory 263960 kb
Host smart-3e4c1a35-e6b8-47fe-b1b2-2f10d7fc5d7e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248
6012653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2486012653
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3110907588
Short name T795
Test name
Test status
Simulation time 1703597300 ps
CPU time 67.14 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:49:14 PM PST 24
Peak memory 258028 kb
Host smart-1900f8ed-8ec1-47b2-8fb9-5d0e90085794
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110907588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3110907588
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2935599017
Short name T767
Test name
Test status
Simulation time 48482000 ps
CPU time 13.48 seconds
Started Feb 07 01:48:01 PM PST 24
Finished Feb 07 01:48:20 PM PST 24
Peak memory 264076 kb
Host smart-ed429e98-8fc4-4442-ae0b-ed8e7806fba1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935599017 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2935599017
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2670643428
Short name T57
Test name
Test status
Simulation time 7346901400 ps
CPU time 71.44 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:49:18 PM PST 24
Peak memory 257960 kb
Host smart-327295d0-87c0-4916-83a6-41a2553ffec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670643428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2670643428
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.1642749656
Short name T325
Test name
Test status
Simulation time 26475115000 ps
CPU time 541.82 seconds
Started Feb 07 01:48:02 PM PST 24
Finished Feb 07 01:57:09 PM PST 24
Peak memory 272172 kb
Host smart-71ee7dcb-3c81-4b34-895c-d5e60229b40a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642749656 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.1642749656
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2138151468
Short name T79
Test name
Test status
Simulation time 276585400 ps
CPU time 132.75 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:50:01 PM PST 24
Peak memory 257960 kb
Host smart-c86f8892-deb5-40c1-8b52-bfbe4285e929
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138151468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2138151468
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.2044591555
Short name T26
Test name
Test status
Simulation time 1939918300 ps
CPU time 138.34 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:50:06 PM PST 24
Peak memory 293956 kb
Host smart-a64f92e3-763d-4b54-bca3-b873863f4027
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044591555 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2044591555
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.586254324
Short name T423
Test name
Test status
Simulation time 20027300 ps
CPU time 13.9 seconds
Started Feb 07 01:47:57 PM PST 24
Finished Feb 07 01:48:13 PM PST 24
Peak memory 277200 kb
Host smart-dd87dbbd-2df1-41b0-9339-19741f1732cd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=586254324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.586254324
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4021990512
Short name T821
Test name
Test status
Simulation time 2861173100 ps
CPU time 388.01 seconds
Started Feb 07 01:47:43 PM PST 24
Finished Feb 07 01:54:12 PM PST 24
Peak memory 260632 kb
Host smart-14baaf96-1ade-4d21-8ab5-ac5a74a2dd91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021990512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4021990512
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3253007061
Short name T754
Test name
Test status
Simulation time 105355500 ps
CPU time 21.1 seconds
Started Feb 07 01:47:54 PM PST 24
Finished Feb 07 01:48:16 PM PST 24
Peak memory 264268 kb
Host smart-2b2b9001-d2d7-4f73-b767-656502f78cf4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253007061 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3253007061
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2657502191
Short name T40
Test name
Test status
Simulation time 72171200 ps
CPU time 13.65 seconds
Started Feb 07 01:47:53 PM PST 24
Finished Feb 07 01:48:07 PM PST 24
Peak memory 264044 kb
Host smart-e401c815-5dfc-427f-b1e2-b4c9a3fb8973
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657502191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.2657502191
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.3008029636
Short name T780
Test name
Test status
Simulation time 57553300 ps
CPU time 183.55 seconds
Started Feb 07 01:47:45 PM PST 24
Finished Feb 07 01:50:50 PM PST 24
Peak memory 280304 kb
Host smart-041a5c49-11d7-4d85-8ada-458d6bbfff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008029636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3008029636
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2820387636
Short name T155
Test name
Test status
Simulation time 898119700 ps
CPU time 101.15 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:49:30 PM PST 24
Peak memory 263936 kb
Host smart-7ffacae2-e809-4a14-bfc2-ebe75800b2f5
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820387636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2820387636
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2157639215
Short name T457
Test name
Test status
Simulation time 23993600 ps
CPU time 23.03 seconds
Started Feb 07 01:48:08 PM PST 24
Finished Feb 07 01:48:33 PM PST 24
Peak memory 264072 kb
Host smart-16ce404a-1073-4840-8e70-c03fc80e18f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157639215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2157639215
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.3965774818
Short name T441
Test name
Test status
Simulation time 835347600 ps
CPU time 105.43 seconds
Started Feb 07 01:48:02 PM PST 24
Finished Feb 07 01:49:52 PM PST 24
Peak memory 280456 kb
Host smart-f4532700-def9-4134-a9d5-b393fdcb0c22
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965774818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.3965774818
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.349402696
Short name T614
Test name
Test status
Simulation time 6831855400 ps
CPU time 471.32 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:55:58 PM PST 24
Peak memory 313212 kb
Host smart-d1becf68-5339-4a18-9780-df7ca9b73df2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349402696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctr
l_rw.349402696
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.4075846581
Short name T461
Test name
Test status
Simulation time 148056700 ps
CPU time 31.08 seconds
Started Feb 07 01:47:58 PM PST 24
Finished Feb 07 01:48:30 PM PST 24
Peak memory 272388 kb
Host smart-d34399bc-0c6a-44d5-b35b-24d305f027a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075846581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.4075846581
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.477229259
Short name T151
Test name
Test status
Simulation time 35823200 ps
CPU time 29.03 seconds
Started Feb 07 01:47:47 PM PST 24
Finished Feb 07 01:48:17 PM PST 24
Peak memory 272348 kb
Host smart-6e744b37-3171-4af0-a033-46f1e2fa7e42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477229259 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.477229259
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2907228295
Short name T199
Test name
Test status
Simulation time 19553473200 ps
CPU time 606.55 seconds
Started Feb 07 01:47:58 PM PST 24
Finished Feb 07 01:58:06 PM PST 24
Peak memory 311804 kb
Host smart-b07c3e1c-b15c-4641-95c7-65305a2e6d99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907228295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.2907228295
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.2944370250
Short name T16
Test name
Test status
Simulation time 1988853400 ps
CPU time 4704.58 seconds
Started Feb 07 01:47:44 PM PST 24
Finished Feb 07 03:06:10 PM PST 24
Peak memory 281892 kb
Host smart-dda94767-eeec-49a4-837b-4a028bf628fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944370250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2944370250
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.4030225594
Short name T303
Test name
Test status
Simulation time 3298368800 ps
CPU time 66.37 seconds
Started Feb 07 01:47:58 PM PST 24
Finished Feb 07 01:49:06 PM PST 24
Peak memory 262140 kb
Host smart-8dd49223-3d05-4b9e-a5dd-f7d59bbfe46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030225594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.4030225594
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1327526
Short name T453
Test name
Test status
Simulation time 692649600 ps
CPU time 49.19 seconds
Started Feb 07 01:48:08 PM PST 24
Finished Feb 07 01:48:59 PM PST 24
Peak memory 264176 kb
Host smart-35be89f4-95b5-4d71-a4d2-33007add19c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ba
se_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_serr_address.1327526
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3852243540
Short name T219
Test name
Test status
Simulation time 1038103300 ps
CPU time 57.38 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:49:04 PM PST 24
Peak memory 272400 kb
Host smart-abc917e4-d4cd-409d-9dcc-e2dc7987d088
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852243540 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3852243540
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2857113585
Short name T831
Test name
Test status
Simulation time 60446200 ps
CPU time 123.44 seconds
Started Feb 07 01:47:31 PM PST 24
Finished Feb 07 01:49:35 PM PST 24
Peak memory 274484 kb
Host smart-19a6fbf6-c715-4fd7-bd2c-d194db808734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857113585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2857113585
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2377877792
Short name T20
Test name
Test status
Simulation time 16407800 ps
CPU time 25.95 seconds
Started Feb 07 01:47:43 PM PST 24
Finished Feb 07 01:48:10 PM PST 24
Peak memory 257984 kb
Host smart-ddc8d03c-4d70-43e4-9132-66866b35c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377877792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2377877792
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.174049770
Short name T833
Test name
Test status
Simulation time 628744200 ps
CPU time 751.74 seconds
Started Feb 07 01:47:54 PM PST 24
Finished Feb 07 02:00:26 PM PST 24
Peak memory 288676 kb
Host smart-66179f20-33c9-4863-a8e4-0c2e02afc089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174049770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress
_all.174049770
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.35312341
Short name T372
Test name
Test status
Simulation time 101589700 ps
CPU time 24.47 seconds
Started Feb 07 01:47:45 PM PST 24
Finished Feb 07 01:48:10 PM PST 24
Peak memory 260764 kb
Host smart-5a82d746-2202-4130-a1d3-a7e4fc42f4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35312341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.35312341
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2447439168
Short name T140
Test name
Test status
Simulation time 19147319100 ps
CPU time 149.29 seconds
Started Feb 07 01:48:03 PM PST 24
Finished Feb 07 01:50:36 PM PST 24
Peak memory 264020 kb
Host smart-f17f3ef9-dc5c-47dc-905b-debc9c84634f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447439168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2447439168
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2860659938
Short name T10
Test name
Test status
Simulation time 84428100 ps
CPU time 15.02 seconds
Started Feb 07 01:47:58 PM PST 24
Finished Feb 07 01:48:15 PM PST 24
Peak memory 264144 kb
Host smart-797b48d5-1a91-49c7-b915-770859b7174d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860659938 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2860659938
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.4250691369
Short name T625
Test name
Test status
Simulation time 82784700 ps
CPU time 14.07 seconds
Started Feb 07 01:53:11 PM PST 24
Finished Feb 07 01:53:26 PM PST 24
Peak memory 264008 kb
Host smart-3ec9e9bb-a608-486f-93db-40ad9d0a0fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250691369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
4250691369
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.617379212
Short name T702
Test name
Test status
Simulation time 15602200 ps
CPU time 15.84 seconds
Started Feb 07 01:53:07 PM PST 24
Finished Feb 07 01:53:24 PM PST 24
Peak memory 273528 kb
Host smart-c6e6adcd-7913-4a1b-9c25-5c6b63d27924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617379212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.617379212
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2789416605
Short name T397
Test name
Test status
Simulation time 8516840900 ps
CPU time 177.48 seconds
Started Feb 07 01:52:56 PM PST 24
Finished Feb 07 01:55:54 PM PST 24
Peak memory 259600 kb
Host smart-c10b167d-ec74-44eb-9395-e3f93454c22b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789416605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2789416605
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3964795284
Short name T174
Test name
Test status
Simulation time 1071670900 ps
CPU time 148.9 seconds
Started Feb 07 01:52:56 PM PST 24
Finished Feb 07 01:55:25 PM PST 24
Peak memory 292184 kb
Host smart-0a150530-627e-44d1-9e02-b69ddb9369ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964795284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3964795284
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2039056175
Short name T732
Test name
Test status
Simulation time 75108846800 ps
CPU time 271.91 seconds
Started Feb 07 01:52:54 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 283060 kb
Host smart-b07f25a8-3beb-4475-8e9b-36c7257e519c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039056175 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2039056175
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3815739388
Short name T612
Test name
Test status
Simulation time 95695500 ps
CPU time 33.17 seconds
Started Feb 07 01:52:58 PM PST 24
Finished Feb 07 01:53:32 PM PST 24
Peak memory 272316 kb
Host smart-aec34af4-709f-45fa-b23a-711e8784f041
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815739388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3815739388
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.956341057
Short name T188
Test name
Test status
Simulation time 70007300 ps
CPU time 30.7 seconds
Started Feb 07 01:52:57 PM PST 24
Finished Feb 07 01:53:28 PM PST 24
Peak memory 265276 kb
Host smart-c1989b31-26aa-4426-9ea3-ae5d3eeb9a87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956341057 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.956341057
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.753139453
Short name T867
Test name
Test status
Simulation time 5079932500 ps
CPU time 65.49 seconds
Started Feb 07 01:53:09 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 263812 kb
Host smart-3a2cf1bf-b5f3-4983-8f50-a33734cea06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753139453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.753139453
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.435856734
Short name T433
Test name
Test status
Simulation time 105425600 ps
CPU time 169 seconds
Started Feb 07 01:52:56 PM PST 24
Finished Feb 07 01:55:46 PM PST 24
Peak memory 275208 kb
Host smart-69a9a8f1-3d1d-4d00-b144-9d3f69dd14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435856734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.435856734
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2037822050
Short name T786
Test name
Test status
Simulation time 474672100 ps
CPU time 16.23 seconds
Started Feb 07 01:53:10 PM PST 24
Finished Feb 07 01:53:27 PM PST 24
Peak memory 264064 kb
Host smart-e5018e6c-3f87-432e-885f-a9a6013795be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037822050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2037822050
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.175609617
Short name T885
Test name
Test status
Simulation time 112565400 ps
CPU time 16.33 seconds
Started Feb 07 01:53:08 PM PST 24
Finished Feb 07 01:53:25 PM PST 24
Peak memory 273768 kb
Host smart-70260287-5ebe-4c32-affd-b34262206b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175609617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.175609617
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.115397945
Short name T493
Test name
Test status
Simulation time 7210902400 ps
CPU time 122.43 seconds
Started Feb 07 01:53:04 PM PST 24
Finished Feb 07 01:55:08 PM PST 24
Peak memory 258024 kb
Host smart-d7141783-7810-4f13-9b2b-61e72ff732b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115397945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.115397945
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.6785105
Short name T919
Test name
Test status
Simulation time 7003306300 ps
CPU time 157.33 seconds
Started Feb 07 01:53:11 PM PST 24
Finished Feb 07 01:55:49 PM PST 24
Peak memory 291104 kb
Host smart-3dd0bff1-0e00-492c-a050-dc5db433c077
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6785105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_
ctrl_intr_rd.6785105
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3821368349
Short name T852
Test name
Test status
Simulation time 22085938100 ps
CPU time 214.05 seconds
Started Feb 07 01:53:01 PM PST 24
Finished Feb 07 01:56:36 PM PST 24
Peak memory 288608 kb
Host smart-e4f88a84-0f52-4b2b-9a01-03432935c14e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821368349 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3821368349
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.799552464
Short name T878
Test name
Test status
Simulation time 37999300 ps
CPU time 131.43 seconds
Started Feb 07 01:53:09 PM PST 24
Finished Feb 07 01:55:21 PM PST 24
Peak memory 258092 kb
Host smart-4613e72d-7c7f-4d01-85f4-ee51a87e8435
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799552464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.799552464
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.92535173
Short name T538
Test name
Test status
Simulation time 65629000 ps
CPU time 14.1 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:53:21 PM PST 24
Peak memory 264028 kb
Host smart-210595c4-c239-4749-b74e-a3f717ffc5e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92535173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_rese
t.92535173
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.30198167
Short name T520
Test name
Test status
Simulation time 29396000 ps
CPU time 31.23 seconds
Started Feb 07 01:53:04 PM PST 24
Finished Feb 07 01:53:36 PM PST 24
Peak memory 271708 kb
Host smart-d13c680f-67c5-40f8-9c6a-3b9ae5ae9535
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30198167 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.30198167
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.709663075
Short name T110
Test name
Test status
Simulation time 5077327100 ps
CPU time 69.31 seconds
Started Feb 07 01:53:04 PM PST 24
Finished Feb 07 01:54:14 PM PST 24
Peak memory 257108 kb
Host smart-7d693d90-4ee9-4a1f-9ed3-e59c460196c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709663075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.709663075
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2847349550
Short name T470
Test name
Test status
Simulation time 21865300 ps
CPU time 74.84 seconds
Started Feb 07 01:53:04 PM PST 24
Finished Feb 07 01:54:20 PM PST 24
Peak memory 274524 kb
Host smart-85ceab18-ba44-4788-82be-aecd2905f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847349550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2847349550
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.3311790707
Short name T429
Test name
Test status
Simulation time 148411900 ps
CPU time 14.24 seconds
Started Feb 07 01:53:18 PM PST 24
Finished Feb 07 01:53:33 PM PST 24
Peak memory 264000 kb
Host smart-cb874383-bf28-48a8-97de-308432597016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311790707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
3311790707
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3916475342
Short name T876
Test name
Test status
Simulation time 176884500 ps
CPU time 15.78 seconds
Started Feb 07 01:53:15 PM PST 24
Finished Feb 07 01:53:32 PM PST 24
Peak memory 273644 kb
Host smart-5592bdd2-f527-4383-adab-44a23dbbea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916475342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3916475342
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2715208377
Short name T858
Test name
Test status
Simulation time 15163000 ps
CPU time 21.55 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:53:29 PM PST 24
Peak memory 272368 kb
Host smart-1aa957b4-2710-4481-b0e2-de24225d01c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715208377 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2715208377
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1023524459
Short name T408
Test name
Test status
Simulation time 4260219100 ps
CPU time 71.08 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:54:18 PM PST 24
Peak memory 259440 kb
Host smart-1951b8a3-b936-4573-b940-5737202accd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023524459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.1023524459
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.1585243029
Short name T857
Test name
Test status
Simulation time 1078046700 ps
CPU time 148.17 seconds
Started Feb 07 01:53:08 PM PST 24
Finished Feb 07 01:55:37 PM PST 24
Peak memory 291280 kb
Host smart-fee768fa-b428-49d2-97e9-cd5c9bd1031f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585243029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.1585243029
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1761836391
Short name T672
Test name
Test status
Simulation time 7839683200 ps
CPU time 223.87 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:56:51 PM PST 24
Peak memory 282996 kb
Host smart-255d77ac-dbd6-4fd7-b76b-00877570f4e1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761836391 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1761836391
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.683507622
Short name T756
Test name
Test status
Simulation time 42637800 ps
CPU time 110.85 seconds
Started Feb 07 01:53:09 PM PST 24
Finished Feb 07 01:55:01 PM PST 24
Peak memory 258212 kb
Host smart-77b8ab52-a29e-427f-9ecc-fe3229930868
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683507622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot
p_reset.683507622
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2737026135
Short name T70
Test name
Test status
Simulation time 78186600 ps
CPU time 15.03 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:53:22 PM PST 24
Peak memory 264080 kb
Host smart-8b444bec-abc9-4007-b77f-bad0021bbc17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737026135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2737026135
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1491041741
Short name T271
Test name
Test status
Simulation time 157386700 ps
CPU time 31.66 seconds
Started Feb 07 01:53:06 PM PST 24
Finished Feb 07 01:53:39 PM PST 24
Peak memory 272348 kb
Host smart-c877f655-307a-4067-ba4b-a23bf6952b82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491041741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1491041741
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.378539906
Short name T180
Test name
Test status
Simulation time 44626000 ps
CPU time 31.23 seconds
Started Feb 07 01:53:07 PM PST 24
Finished Feb 07 01:53:39 PM PST 24
Peak memory 272428 kb
Host smart-82b33121-fb62-452e-a0e1-57b5fcf51463
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378539906 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.378539906
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1171736984
Short name T921
Test name
Test status
Simulation time 508872000 ps
CPU time 59.42 seconds
Started Feb 07 01:53:15 PM PST 24
Finished Feb 07 01:54:15 PM PST 24
Peak memory 261860 kb
Host smart-7924458a-a072-4223-87ef-f9086e2d9506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171736984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1171736984
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1784387193
Short name T838
Test name
Test status
Simulation time 55256100 ps
CPU time 145.49 seconds
Started Feb 07 01:53:09 PM PST 24
Finished Feb 07 01:55:35 PM PST 24
Peak memory 274776 kb
Host smart-0be993ba-caf2-45a5-9fdb-e034d2c9ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784387193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1784387193
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1230886993
Short name T394
Test name
Test status
Simulation time 107644600 ps
CPU time 13.61 seconds
Started Feb 07 01:53:20 PM PST 24
Finished Feb 07 01:53:34 PM PST 24
Peak memory 264096 kb
Host smart-58c7babe-fb5e-4128-a81b-27bdb9dadfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230886993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1230886993
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2469907547
Short name T207
Test name
Test status
Simulation time 13511800 ps
CPU time 15.66 seconds
Started Feb 07 01:53:17 PM PST 24
Finished Feb 07 01:53:33 PM PST 24
Peak memory 273680 kb
Host smart-48363b3b-072e-4f04-b002-8ba730a565f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469907547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2469907547
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3562067925
Short name T846
Test name
Test status
Simulation time 5475923200 ps
CPU time 159.23 seconds
Started Feb 07 01:53:13 PM PST 24
Finished Feb 07 01:55:53 PM PST 24
Peak memory 288704 kb
Host smart-4aa64c0a-725c-41f2-8766-e1400dddf466
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562067925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3562067925
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1593840869
Short name T503
Test name
Test status
Simulation time 24607492100 ps
CPU time 193.57 seconds
Started Feb 07 01:53:16 PM PST 24
Finished Feb 07 01:56:31 PM PST 24
Peak memory 283044 kb
Host smart-d70a6b20-2aad-4ab1-9dd4-5cbb3d54c9c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593840869 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.1593840869
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.633083421
Short name T775
Test name
Test status
Simulation time 19348800 ps
CPU time 13.42 seconds
Started Feb 07 01:53:20 PM PST 24
Finished Feb 07 01:53:34 PM PST 24
Peak memory 264092 kb
Host smart-b158b567-4007-4a93-9ef1-d0a82a739553
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633083421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_res
et.633083421
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.2861925181
Short name T122
Test name
Test status
Simulation time 203868500 ps
CPU time 31.7 seconds
Started Feb 07 01:53:16 PM PST 24
Finished Feb 07 01:53:49 PM PST 24
Peak memory 272396 kb
Host smart-740ce096-f09f-4808-bfa9-63a9600438bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861925181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.2861925181
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1950117464
Short name T181
Test name
Test status
Simulation time 35096200 ps
CPU time 29.36 seconds
Started Feb 07 01:53:23 PM PST 24
Finished Feb 07 01:53:53 PM PST 24
Peak memory 272384 kb
Host smart-4a114c21-9d9f-4bcf-9fa8-1f816dc906c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950117464 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1950117464
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3623237454
Short name T913
Test name
Test status
Simulation time 18868000 ps
CPU time 98.31 seconds
Started Feb 07 01:53:08 PM PST 24
Finished Feb 07 01:54:47 PM PST 24
Peak memory 274800 kb
Host smart-57a53cef-b84f-4c8c-a6d0-dda91dab6254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623237454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3623237454
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.901327545
Short name T723
Test name
Test status
Simulation time 76840800 ps
CPU time 13.76 seconds
Started Feb 07 01:53:26 PM PST 24
Finished Feb 07 01:53:40 PM PST 24
Peak memory 264036 kb
Host smart-cd3fe6f9-d80b-4fdf-a201-e421a95998f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901327545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.901327545
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.246273140
Short name T402
Test name
Test status
Simulation time 84926900 ps
CPU time 13.67 seconds
Started Feb 07 01:53:27 PM PST 24
Finished Feb 07 01:53:45 PM PST 24
Peak memory 273692 kb
Host smart-cdffc707-4da3-4b1e-bf17-fda653332bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246273140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.246273140
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1676056806
Short name T336
Test name
Test status
Simulation time 8209085300 ps
CPU time 142.86 seconds
Started Feb 07 01:53:19 PM PST 24
Finished Feb 07 01:55:43 PM PST 24
Peak memory 258356 kb
Host smart-a2298c13-e3bc-43ec-baf7-1fda33bfcb8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676056806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1676056806
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.799541100
Short name T599
Test name
Test status
Simulation time 5182200000 ps
CPU time 172.8 seconds
Started Feb 07 01:53:18 PM PST 24
Finished Feb 07 01:56:11 PM PST 24
Peak memory 292268 kb
Host smart-b4fb8114-08c9-48d3-a8f4-9fb0a184606f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799541100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.799541100
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3769841404
Short name T499
Test name
Test status
Simulation time 9057718800 ps
CPU time 199.17 seconds
Started Feb 07 01:53:17 PM PST 24
Finished Feb 07 01:56:37 PM PST 24
Peak memory 283060 kb
Host smart-45bb3252-beb8-448b-bf74-06539e40dbb1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769841404 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3769841404
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.1308944080
Short name T268
Test name
Test status
Simulation time 740553900 ps
CPU time 68.11 seconds
Started Feb 07 01:53:18 PM PST 24
Finished Feb 07 01:54:27 PM PST 24
Peak memory 263996 kb
Host smart-c4de8159-06bb-4259-8380-dc0fc3179527
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308944080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.1308944080
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.2079231655
Short name T4
Test name
Test status
Simulation time 92182200 ps
CPU time 33.2 seconds
Started Feb 07 01:53:31 PM PST 24
Finished Feb 07 01:54:05 PM PST 24
Peak memory 272328 kb
Host smart-b7e7d5a2-c397-4c37-96c9-dfa02cf8cc6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079231655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.2079231655
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.103020577
Short name T760
Test name
Test status
Simulation time 37450500 ps
CPU time 31.29 seconds
Started Feb 07 01:53:31 PM PST 24
Finished Feb 07 01:54:04 PM PST 24
Peak memory 272436 kb
Host smart-56de7c7d-a58d-4ca9-aa10-5edd381f1ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103020577 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.103020577
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2802325712
Short name T937
Test name
Test status
Simulation time 32410710500 ps
CPU time 76.06 seconds
Started Feb 07 01:53:30 PM PST 24
Finished Feb 07 01:54:48 PM PST 24
Peak memory 262772 kb
Host smart-b927f2da-0c3d-4b22-9619-37d13da282e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802325712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2802325712
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2741648544
Short name T712
Test name
Test status
Simulation time 70032300 ps
CPU time 14.37 seconds
Started Feb 07 01:53:41 PM PST 24
Finished Feb 07 01:53:57 PM PST 24
Peak memory 264104 kb
Host smart-18f2b447-d5be-43c1-8581-60ea3efd9b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741648544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2741648544
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.4151201575
Short name T469
Test name
Test status
Simulation time 27090700 ps
CPU time 16.3 seconds
Started Feb 07 01:53:39 PM PST 24
Finished Feb 07 01:53:56 PM PST 24
Peak memory 273576 kb
Host smart-c9ce6270-4ec0-4788-9970-68931d278ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151201575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.4151201575
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.35168603
Short name T519
Test name
Test status
Simulation time 2368987600 ps
CPU time 167.69 seconds
Started Feb 07 01:53:25 PM PST 24
Finished Feb 07 01:56:14 PM PST 24
Peak memory 291384 kb
Host smart-3732cb6d-3e54-44e2-b8f1-b0a7c9255853
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35168603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash
_ctrl_intr_rd.35168603
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1551005387
Short name T334
Test name
Test status
Simulation time 18278082700 ps
CPU time 223.3 seconds
Started Feb 07 01:53:23 PM PST 24
Finished Feb 07 01:57:07 PM PST 24
Peak memory 288676 kb
Host smart-d4b99b3d-26e3-482c-88ba-779e7ccd07e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551005387 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1551005387
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2902693936
Short name T788
Test name
Test status
Simulation time 38428400 ps
CPU time 132.96 seconds
Started Feb 07 01:53:27 PM PST 24
Finished Feb 07 01:55:44 PM PST 24
Peak memory 258104 kb
Host smart-168abd9a-954c-4ecd-b6b8-471b715d577c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902693936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2902693936
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3196859352
Short name T744
Test name
Test status
Simulation time 34272700 ps
CPU time 13.61 seconds
Started Feb 07 01:53:28 PM PST 24
Finished Feb 07 01:53:45 PM PST 24
Peak memory 264076 kb
Host smart-7b547b7f-0028-41ba-bc28-27bc1fd0060d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196859352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3196859352
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2243034463
Short name T187
Test name
Test status
Simulation time 84265200 ps
CPU time 32.02 seconds
Started Feb 07 01:53:33 PM PST 24
Finished Feb 07 01:54:07 PM PST 24
Peak memory 272368 kb
Host smart-c4afc116-c076-41d0-87d3-615356d5cf2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243034463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2243034463
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.3770641940
Short name T447
Test name
Test status
Simulation time 2357858400 ps
CPU time 62.07 seconds
Started Feb 07 01:53:42 PM PST 24
Finished Feb 07 01:54:45 PM PST 24
Peak memory 262760 kb
Host smart-de28bf1a-c851-4c67-b66c-811430b40539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770641940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3770641940
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.208617531
Short name T111
Test name
Test status
Simulation time 98421100 ps
CPU time 126.07 seconds
Started Feb 07 01:53:24 PM PST 24
Finished Feb 07 01:55:31 PM PST 24
Peak memory 273972 kb
Host smart-dcf8275b-7689-4647-b547-0a0461272c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208617531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.208617531
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1375557930
Short name T640
Test name
Test status
Simulation time 25318700 ps
CPU time 13.65 seconds
Started Feb 07 01:53:57 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 264032 kb
Host smart-aab6aaee-fbd5-44b5-8fba-e6ca5b71a0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375557930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1375557930
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.106141811
Short name T837
Test name
Test status
Simulation time 12300700 ps
CPU time 21.82 seconds
Started Feb 07 01:53:40 PM PST 24
Finished Feb 07 01:54:03 PM PST 24
Peak memory 264204 kb
Host smart-0287156c-60f6-4356-be84-5f6701bcdb15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106141811 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.106141811
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3449462242
Short name T717
Test name
Test status
Simulation time 12257477400 ps
CPU time 165.04 seconds
Started Feb 07 01:53:41 PM PST 24
Finished Feb 07 01:56:27 PM PST 24
Peak memory 257880 kb
Host smart-fdc01637-3df0-4ad8-89b8-d90cee6db8ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449462242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3449462242
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3655952343
Short name T615
Test name
Test status
Simulation time 4536859800 ps
CPU time 164.57 seconds
Started Feb 07 01:53:42 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 291012 kb
Host smart-a5dacc46-e6ed-4e35-a019-366af75118a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655952343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3655952343
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1766939606
Short name T330
Test name
Test status
Simulation time 37628886700 ps
CPU time 245.86 seconds
Started Feb 07 01:53:39 PM PST 24
Finished Feb 07 01:57:46 PM PST 24
Peak memory 282904 kb
Host smart-752bc6bd-9db5-46d3-b38c-f2523600414b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766939606 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1766939606
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.4200185982
Short name T777
Test name
Test status
Simulation time 41519300 ps
CPU time 133.43 seconds
Started Feb 07 01:53:39 PM PST 24
Finished Feb 07 01:55:53 PM PST 24
Peak memory 258140 kb
Host smart-e6b1a2d4-c3f4-46b8-a186-085250269e43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200185982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.4200185982
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2032622806
Short name T794
Test name
Test status
Simulation time 66146100 ps
CPU time 13.77 seconds
Started Feb 07 01:53:39 PM PST 24
Finished Feb 07 01:53:54 PM PST 24
Peak memory 264016 kb
Host smart-683a4758-8204-4708-b7df-e0ac72bb87f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032622806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2032622806
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3466529489
Short name T703
Test name
Test status
Simulation time 137182500 ps
CPU time 31.17 seconds
Started Feb 07 01:53:43 PM PST 24
Finished Feb 07 01:54:15 PM PST 24
Peak memory 272384 kb
Host smart-8eaee638-4a61-4620-8e9f-ed33b2d82511
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466529489 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3466529489
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.1431605219
Short name T308
Test name
Test status
Simulation time 2107774500 ps
CPU time 53.09 seconds
Started Feb 07 01:53:42 PM PST 24
Finished Feb 07 01:54:36 PM PST 24
Peak memory 262736 kb
Host smart-a8a5f31b-7f31-4a9f-a9f3-da3cbf31176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431605219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1431605219
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.79157371
Short name T553
Test name
Test status
Simulation time 103759500 ps
CPU time 124.53 seconds
Started Feb 07 01:53:43 PM PST 24
Finished Feb 07 01:55:49 PM PST 24
Peak memory 274524 kb
Host smart-7a75c3ff-e213-48ae-b265-4aa77607a82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79157371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.79157371
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1696951344
Short name T811
Test name
Test status
Simulation time 99781700 ps
CPU time 13.67 seconds
Started Feb 07 01:53:57 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 264068 kb
Host smart-fe058eea-f749-4fbc-940b-f16568064eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696951344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1696951344
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.774049927
Short name T635
Test name
Test status
Simulation time 24914400 ps
CPU time 13.51 seconds
Started Feb 07 01:53:50 PM PST 24
Finished Feb 07 01:54:05 PM PST 24
Peak memory 273392 kb
Host smart-a7ab7cf7-4d34-4b3a-876f-e24eea2a7d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774049927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.774049927
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.702686935
Short name T172
Test name
Test status
Simulation time 2819205900 ps
CPU time 103.18 seconds
Started Feb 07 01:53:58 PM PST 24
Finished Feb 07 01:55:45 PM PST 24
Peak memory 258576 kb
Host smart-cdb18630-c806-4e77-82fe-e25c576ae22f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702686935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.702686935
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.702340718
Short name T906
Test name
Test status
Simulation time 9248132100 ps
CPU time 215.13 seconds
Started Feb 07 01:53:46 PM PST 24
Finished Feb 07 01:57:23 PM PST 24
Peak memory 288748 kb
Host smart-2451cfc0-b595-47bf-97ed-d37b58c50a74
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702340718 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.702340718
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.964477131
Short name T425
Test name
Test status
Simulation time 72854100 ps
CPU time 13.63 seconds
Started Feb 07 01:53:52 PM PST 24
Finished Feb 07 01:54:07 PM PST 24
Peak memory 264104 kb
Host smart-170fbf1e-37da-41aa-9cde-e8f10ac9cc29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964477131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.964477131
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.147915305
Short name T186
Test name
Test status
Simulation time 84043000 ps
CPU time 29.59 seconds
Started Feb 07 01:53:47 PM PST 24
Finished Feb 07 01:54:18 PM PST 24
Peak memory 272292 kb
Host smart-5a68e450-957a-4b76-80eb-06fa237efb6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147915305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.147915305
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2093060530
Short name T443
Test name
Test status
Simulation time 131626800 ps
CPU time 30.95 seconds
Started Feb 07 01:53:58 PM PST 24
Finished Feb 07 01:54:33 PM PST 24
Peak memory 272348 kb
Host smart-3e43785b-f935-4a47-b932-68889c7a85c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093060530 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2093060530
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.565115166
Short name T450
Test name
Test status
Simulation time 2318724200 ps
CPU time 76.08 seconds
Started Feb 07 01:53:47 PM PST 24
Finished Feb 07 01:55:04 PM PST 24
Peak memory 257896 kb
Host smart-c5e0723e-9b8b-4491-8361-bf3751d8299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565115166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.565115166
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3575261645
Short name T416
Test name
Test status
Simulation time 37574900 ps
CPU time 74.77 seconds
Started Feb 07 01:53:45 PM PST 24
Finished Feb 07 01:55:02 PM PST 24
Peak memory 273468 kb
Host smart-dc5f9ba6-bf44-4b4e-8b23-e0ed963c09f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575261645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3575261645
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2370226638
Short name T936
Test name
Test status
Simulation time 46068800 ps
CPU time 14.08 seconds
Started Feb 07 01:53:58 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 264100 kb
Host smart-aac81242-d404-40f7-a8d7-ac120c4af4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370226638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2370226638
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.297903889
Short name T476
Test name
Test status
Simulation time 5013729200 ps
CPU time 81.12 seconds
Started Feb 07 01:53:49 PM PST 24
Finished Feb 07 01:55:12 PM PST 24
Peak memory 258496 kb
Host smart-e2a7c917-554d-4f21-a9f7-e8a6ac4f6284
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297903889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h
w_sec_otp.297903889
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.1766182498
Short name T829
Test name
Test status
Simulation time 3961242000 ps
CPU time 165.44 seconds
Started Feb 07 01:53:54 PM PST 24
Finished Feb 07 01:56:41 PM PST 24
Peak memory 292092 kb
Host smart-887eb898-1371-4577-a4ae-3c00e9b267d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766182498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.1766182498
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3113209670
Short name T428
Test name
Test status
Simulation time 17866400 ps
CPU time 13.69 seconds
Started Feb 07 01:53:56 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 264092 kb
Host smart-b52aa416-0c71-4e3f-8783-eb6e92926c0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113209670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.3113209670
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3337556138
Short name T191
Test name
Test status
Simulation time 77545700 ps
CPU time 31.27 seconds
Started Feb 07 01:53:53 PM PST 24
Finished Feb 07 01:54:26 PM PST 24
Peak memory 272416 kb
Host smart-92d81a33-f11a-4f43-bc31-836bda2eb2f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337556138 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3337556138
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.4246992251
Short name T571
Test name
Test status
Simulation time 3747963800 ps
CPU time 73.15 seconds
Started Feb 07 01:53:56 PM PST 24
Finished Feb 07 01:55:15 PM PST 24
Peak memory 257880 kb
Host smart-ad71b3e9-fb67-4b48-af23-fed68e162a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246992251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4246992251
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2452047387
Short name T806
Test name
Test status
Simulation time 39050500 ps
CPU time 222.96 seconds
Started Feb 07 01:53:50 PM PST 24
Finished Feb 07 01:57:34 PM PST 24
Peak memory 279884 kb
Host smart-2ab53289-9203-4598-b327-571ddee8e65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452047387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2452047387
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2064594229
Short name T774
Test name
Test status
Simulation time 22825200 ps
CPU time 13.82 seconds
Started Feb 07 01:54:13 PM PST 24
Finished Feb 07 01:54:27 PM PST 24
Peak memory 264104 kb
Host smart-030d522c-5b1c-4a42-af5c-5aadcde2b61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064594229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2064594229
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.3824065496
Short name T431
Test name
Test status
Simulation time 25702600 ps
CPU time 15.58 seconds
Started Feb 07 01:54:18 PM PST 24
Finished Feb 07 01:54:35 PM PST 24
Peak memory 273600 kb
Host smart-6680c623-818b-42c2-aa7f-f3dc6b5563f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824065496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3824065496
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3905311531
Short name T98
Test name
Test status
Simulation time 53772900 ps
CPU time 22.2 seconds
Started Feb 07 01:54:09 PM PST 24
Finished Feb 07 01:54:33 PM PST 24
Peak memory 264352 kb
Host smart-027cf74d-25fd-4940-9d6a-f8f422ef9406
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905311531 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3905311531
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3330326247
Short name T543
Test name
Test status
Simulation time 662173000 ps
CPU time 34.14 seconds
Started Feb 07 01:53:56 PM PST 24
Finished Feb 07 01:54:36 PM PST 24
Peak memory 258372 kb
Host smart-30b35cc2-ec36-44ad-a021-3a9087f75d6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330326247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3330326247
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2118443843
Short name T592
Test name
Test status
Simulation time 2516739400 ps
CPU time 141.9 seconds
Started Feb 07 01:54:11 PM PST 24
Finished Feb 07 01:56:34 PM PST 24
Peak memory 288620 kb
Host smart-1f6c208c-f5d8-4f26-b505-55fb9e832955
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118443843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2118443843
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2495566622
Short name T782
Test name
Test status
Simulation time 7727574500 ps
CPU time 219.94 seconds
Started Feb 07 01:54:17 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 283020 kb
Host smart-7811210b-886c-4ef1-9a69-ac5f6e49fffb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495566622 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.2495566622
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2911814271
Short name T139
Test name
Test status
Simulation time 292617700 ps
CPU time 25.07 seconds
Started Feb 07 01:54:10 PM PST 24
Finished Feb 07 01:54:36 PM PST 24
Peak memory 264060 kb
Host smart-30c37498-7643-41ee-a087-bd69d9f28830
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911814271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2911814271
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3494576731
Short name T752
Test name
Test status
Simulation time 87194300 ps
CPU time 32.9 seconds
Started Feb 07 01:54:07 PM PST 24
Finished Feb 07 01:54:42 PM PST 24
Peak memory 272368 kb
Host smart-40f9e752-8cc4-41a9-a6b2-adf0de872d52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494576731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3494576731
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.511316429
Short name T170
Test name
Test status
Simulation time 30209800 ps
CPU time 31.03 seconds
Started Feb 07 01:54:10 PM PST 24
Finished Feb 07 01:54:42 PM PST 24
Peak memory 272428 kb
Host smart-5f898a37-d982-4d00-93ee-203f88f67e38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511316429 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.511316429
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.462019570
Short name T399
Test name
Test status
Simulation time 995722100 ps
CPU time 64.11 seconds
Started Feb 07 01:54:11 PM PST 24
Finished Feb 07 01:55:16 PM PST 24
Peak memory 262064 kb
Host smart-03c90b8f-96ba-4003-b972-0ad18644aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462019570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.462019570
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.1925904122
Short name T434
Test name
Test status
Simulation time 44127300 ps
CPU time 197.99 seconds
Started Feb 07 01:54:01 PM PST 24
Finished Feb 07 01:57:25 PM PST 24
Peak memory 275444 kb
Host smart-70b96af4-0f77-4448-9492-0f317b2a1083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925904122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1925904122
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.3445991872
Short name T380
Test name
Test status
Simulation time 43724800 ps
CPU time 13.39 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:48:49 PM PST 24
Peak memory 264072 kb
Host smart-f73edee6-166b-4593-b517-52fb25a3a2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445991872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3
445991872
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.1481045031
Short name T691
Test name
Test status
Simulation time 51031300 ps
CPU time 15.59 seconds
Started Feb 07 01:48:41 PM PST 24
Finished Feb 07 01:48:58 PM PST 24
Peak memory 273788 kb
Host smart-24ee8538-eeeb-4ef9-921d-41a8622c7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481045031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1481045031
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.3704011105
Short name T69
Test name
Test status
Simulation time 143736800 ps
CPU time 107.45 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:50:08 PM PST 24
Peak memory 268812 kb
Host smart-a581179b-b7e9-4535-813e-179424614417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704011105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.3704011105
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2824800401
Short name T49
Test name
Test status
Simulation time 18626587000 ps
CPU time 564.92 seconds
Started Feb 07 01:48:21 PM PST 24
Finished Feb 07 01:57:49 PM PST 24
Peak memory 259240 kb
Host smart-62588456-4110-4f9d-b107-7be10faf6b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824800401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2824800401
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2730513535
Short name T492
Test name
Test status
Simulation time 16926899000 ps
CPU time 2373.05 seconds
Started Feb 07 01:48:08 PM PST 24
Finished Feb 07 02:27:44 PM PST 24
Peak memory 264016 kb
Host smart-18cad760-64a0-4d06-88e8-8920152da1ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730513535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2730513535
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2730405980
Short name T473
Test name
Test status
Simulation time 1532982600 ps
CPU time 982.23 seconds
Started Feb 07 01:48:08 PM PST 24
Finished Feb 07 02:04:33 PM PST 24
Peak memory 272208 kb
Host smart-a280a886-01d4-4201-936c-93aa49756572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730405980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2730405980
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.586594940
Short name T572
Test name
Test status
Simulation time 1202888500 ps
CPU time 23.97 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:48:44 PM PST 24
Peak memory 264060 kb
Host smart-7c95abd0-b82f-4084-946a-4398b174c354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586594940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.586594940
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2454151125
Short name T324
Test name
Test status
Simulation time 186798449700 ps
CPU time 2520.92 seconds
Started Feb 07 01:48:17 PM PST 24
Finished Feb 07 02:30:21 PM PST 24
Peak memory 264080 kb
Host smart-b41a4045-88ce-459a-97d1-432814521e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454151125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2454151125
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.4075782398
Short name T90
Test name
Test status
Simulation time 468752894100 ps
CPU time 1956.95 seconds
Started Feb 07 01:48:06 PM PST 24
Finished Feb 07 02:20:45 PM PST 24
Peak memory 263716 kb
Host smart-401d61a1-aa56-49f4-a476-fd1b3aa46838
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075782398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.4075782398
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2001802856
Short name T270
Test name
Test status
Simulation time 80808200 ps
CPU time 70.68 seconds
Started Feb 07 01:48:17 PM PST 24
Finished Feb 07 01:49:31 PM PST 24
Peak memory 263912 kb
Host smart-a8eb92c0-656c-48e4-ad84-50255be9a94f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001802856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2001802856
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1488909307
Short name T841
Test name
Test status
Simulation time 10031457500 ps
CPU time 60.11 seconds
Started Feb 07 01:48:45 PM PST 24
Finished Feb 07 01:49:46 PM PST 24
Peak memory 291496 kb
Host smart-412c89a0-1c6b-4665-b07b-7fd1ec390616
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488909307 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1488909307
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.905316950
Short name T376
Test name
Test status
Simulation time 25350600 ps
CPU time 13.49 seconds
Started Feb 07 01:48:32 PM PST 24
Finished Feb 07 01:48:47 PM PST 24
Peak memory 263968 kb
Host smart-0d5b5a94-7c62-4d8f-8d89-0a9a0ae5752a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905316950 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.905316950
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.5334238
Short name T482
Test name
Test status
Simulation time 4413571600 ps
CPU time 150.2 seconds
Started Feb 07 01:48:22 PM PST 24
Finished Feb 07 01:50:55 PM PST 24
Peak memory 258380 kb
Host smart-0e64314e-e167-4dfe-aa24-bcf4d91fbdb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5334238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_s
ec_otp.5334238
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.54903983
Short name T686
Test name
Test status
Simulation time 25462780400 ps
CPU time 509.01 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 330272 kb
Host smart-87f7a834-827d-45db-a718-0666cded8e4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54903983 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.flash_ctrl_integrity.54903983
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.323954730
Short name T602
Test name
Test status
Simulation time 2991770700 ps
CPU time 181.25 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:51:25 PM PST 24
Peak memory 288752 kb
Host smart-fb3f6c7a-a99f-4c29-8f2f-b15476a4bc29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323954730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.323954730
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1456016777
Short name T562
Test name
Test status
Simulation time 35262050000 ps
CPU time 236.88 seconds
Started Feb 07 01:48:41 PM PST 24
Finished Feb 07 01:52:39 PM PST 24
Peak memory 288796 kb
Host smart-0a07a42c-ecab-4cbe-9591-7e570fca77e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456016777 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1456016777
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.4067591696
Short name T392
Test name
Test status
Simulation time 7997889100 ps
CPU time 101.66 seconds
Started Feb 07 01:48:35 PM PST 24
Finished Feb 07 01:50:18 PM PST 24
Peak memory 264044 kb
Host smart-96bc65d6-1fb3-4d1a-89da-bc3232c6cba4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067591696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.4067591696
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.918157698
Short name T419
Test name
Test status
Simulation time 172380289700 ps
CPU time 470.57 seconds
Started Feb 07 01:48:30 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 264096 kb
Host smart-4466d4a8-e0d0-4a0b-8e98-31214717bc2d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918
157698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.918157698
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.885244393
Short name T643
Test name
Test status
Simulation time 19119281400 ps
CPU time 78.2 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:49:42 PM PST 24
Peak memory 258916 kb
Host smart-ffb89a7c-b730-4373-a66f-6c29ba8768a7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885244393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.885244393
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.2039205086
Short name T558
Test name
Test status
Simulation time 51620600 ps
CPU time 13.32 seconds
Started Feb 07 01:48:31 PM PST 24
Finished Feb 07 01:48:45 PM PST 24
Peak memory 264044 kb
Host smart-752a2d9b-a22a-4364-a50c-f2acc37a7a51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039205086 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.2039205086
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.598699714
Short name T59
Test name
Test status
Simulation time 12851151700 ps
CPU time 77.96 seconds
Started Feb 07 01:48:19 PM PST 24
Finished Feb 07 01:49:42 PM PST 24
Peak memory 258244 kb
Host smart-3ff7c527-fe2c-46df-86c1-a6d332be3191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598699714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.598699714
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.2557808384
Short name T145
Test name
Test status
Simulation time 5882471700 ps
CPU time 479.68 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:56:24 PM PST 24
Peak memory 272432 kb
Host smart-011bd142-5521-4d90-b3dc-c6c705cccecb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557808384 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.2557808384
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.4003242951
Short name T510
Test name
Test status
Simulation time 79605700 ps
CPU time 133.86 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:50:34 PM PST 24
Peak memory 258372 kb
Host smart-22cf3d66-3216-4d5e-a3ab-96adc0855fe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003242951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.4003242951
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.349571025
Short name T129
Test name
Test status
Simulation time 77036000 ps
CPU time 13.84 seconds
Started Feb 07 01:48:30 PM PST 24
Finished Feb 07 01:48:44 PM PST 24
Peak memory 277424 kb
Host smart-925bd220-c0ef-43f1-8da3-97aa71035b0a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=349571025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.349571025
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.580670758
Short name T126
Test name
Test status
Simulation time 1896583300 ps
CPU time 322.88 seconds
Started Feb 07 01:48:02 PM PST 24
Finished Feb 07 01:53:30 PM PST 24
Peak memory 264060 kb
Host smart-a00db386-d4d9-452d-8c4e-f5a0173d7358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580670758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.580670758
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1548848218
Short name T227
Test name
Test status
Simulation time 15361300 ps
CPU time 14.34 seconds
Started Feb 07 01:48:29 PM PST 24
Finished Feb 07 01:48:44 PM PST 24
Peak memory 264244 kb
Host smart-07840f54-10da-4625-aa63-bcef48d72bc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548848218 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1548848218
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.4153122355
Short name T315
Test name
Test status
Simulation time 140404400 ps
CPU time 14.47 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:48:50 PM PST 24
Peak memory 263972 kb
Host smart-28986a6c-3be5-4fd8-9e67-46b3a658b59b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153122355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.4153122355
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.3722575222
Short name T881
Test name
Test status
Simulation time 100117200 ps
CPU time 158.46 seconds
Started Feb 07 01:48:14 PM PST 24
Finished Feb 07 01:50:58 PM PST 24
Peak memory 270140 kb
Host smart-c3324915-8b34-4cf5-bf31-59de30b52343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722575222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3722575222
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.559841959
Short name T638
Test name
Test status
Simulation time 84763100 ps
CPU time 100.58 seconds
Started Feb 07 01:47:59 PM PST 24
Finished Feb 07 01:49:46 PM PST 24
Peak memory 263396 kb
Host smart-81480900-0252-40bb-a5f3-e161a83159e4
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=559841959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.559841959
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3159553215
Short name T577
Test name
Test status
Simulation time 23405300 ps
CPU time 21.22 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:48:41 PM PST 24
Peak memory 264184 kb
Host smart-3d66eaed-fca3-4e0f-8ccc-5d1d66e24eed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159553215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3159553215
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.713127069
Short name T183
Test name
Test status
Simulation time 874286000 ps
CPU time 95.09 seconds
Started Feb 07 01:48:19 PM PST 24
Finished Feb 07 01:49:59 PM PST 24
Peak memory 280456 kb
Host smart-551bf20e-e6f7-4c97-a069-f182e264b872
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713127069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_ro.713127069
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.2177592341
Short name T759
Test name
Test status
Simulation time 5995938400 ps
CPU time 135.12 seconds
Started Feb 07 01:48:19 PM PST 24
Finished Feb 07 01:50:39 PM PST 24
Peak memory 292552 kb
Host smart-b97a59fe-8855-43f3-95d9-562cda9cb242
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177592341 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2177592341
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.857394676
Short name T563
Test name
Test status
Simulation time 66499324900 ps
CPU time 599.56 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 312524 kb
Host smart-e0bc0149-3617-4066-be36-b52a08008584
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857394676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctr
l_rw.857394676
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.2039485170
Short name T892
Test name
Test status
Simulation time 306223100 ps
CPU time 31.77 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:49:07 PM PST 24
Peak memory 272336 kb
Host smart-3e59dd1a-62ea-415b-9de8-ea61323f1210
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039485170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.2039485170
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2024764495
Short name T508
Test name
Test status
Simulation time 165157700 ps
CPU time 30.5 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:49:06 PM PST 24
Peak memory 272412 kb
Host smart-ac0e7cb5-cfd5-46d9-b723-59525a471ab3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024764495 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2024764495
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.1122154646
Short name T883
Test name
Test status
Simulation time 7445261300 ps
CPU time 599.55 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 310364 kb
Host smart-e3762490-ca13-4859-98bd-b2e6d602c2da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122154646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.1122154646
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.3147987436
Short name T875
Test name
Test status
Simulation time 1866666000 ps
CPU time 59.42 seconds
Started Feb 07 01:48:20 PM PST 24
Finished Feb 07 01:49:23 PM PST 24
Peak memory 264096 kb
Host smart-eb6ca193-38ed-4959-905a-0ab41cf652cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147987436 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.3147987436
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.1033504627
Short name T525
Test name
Test status
Simulation time 544997700 ps
CPU time 64.98 seconds
Started Feb 07 01:48:18 PM PST 24
Finished Feb 07 01:49:25 PM PST 24
Peak memory 264224 kb
Host smart-e56092e6-ca5f-49c4-936d-107881fba96c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033504627 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.1033504627
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3006325925
Short name T541
Test name
Test status
Simulation time 43615200 ps
CPU time 100.15 seconds
Started Feb 07 01:48:21 PM PST 24
Finished Feb 07 01:50:04 PM PST 24
Peak memory 273768 kb
Host smart-15fef226-446a-40e0-af6a-efdb16a1c2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006325925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3006325925
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.4218195135
Short name T451
Test name
Test status
Simulation time 24070600 ps
CPU time 26.17 seconds
Started Feb 07 01:48:05 PM PST 24
Finished Feb 07 01:48:33 PM PST 24
Peak memory 257944 kb
Host smart-4b030416-e3ae-4e6d-ad52-d46c0794d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218195135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.4218195135
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.3610879539
Short name T743
Test name
Test status
Simulation time 1712547400 ps
CPU time 940.75 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 02:04:16 PM PST 24
Peak memory 291024 kb
Host smart-0065318b-d3e5-4230-9054-b41ebccd7093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610879539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.3610879539
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3779839599
Short name T734
Test name
Test status
Simulation time 29647000 ps
CPU time 26.41 seconds
Started Feb 07 01:48:17 PM PST 24
Finished Feb 07 01:48:46 PM PST 24
Peak memory 260708 kb
Host smart-0b13e13a-85ad-463c-9bed-ff4c8eb2c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779839599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3779839599
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.283048478
Short name T456
Test name
Test status
Simulation time 34307744100 ps
CPU time 145.11 seconds
Started Feb 07 01:48:21 PM PST 24
Finished Feb 07 01:50:49 PM PST 24
Peak memory 263884 kb
Host smart-b18a0be1-252f-49b3-8a0f-8dbb870e1472
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283048478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_wo.283048478
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.983424314
Short name T398
Test name
Test status
Simulation time 109313100 ps
CPU time 13.72 seconds
Started Feb 07 01:54:10 PM PST 24
Finished Feb 07 01:54:26 PM PST 24
Peak memory 264048 kb
Host smart-a56adeaa-9d2c-4bf8-96a0-98941f24fbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983424314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.983424314
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1419775701
Short name T623
Test name
Test status
Simulation time 84364900 ps
CPU time 16.29 seconds
Started Feb 07 01:54:09 PM PST 24
Finished Feb 07 01:54:27 PM PST 24
Peak memory 273624 kb
Host smart-e5137096-99e9-45f6-b919-3747cc482e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419775701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1419775701
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1549039914
Short name T655
Test name
Test status
Simulation time 4032238900 ps
CPU time 125.23 seconds
Started Feb 07 01:54:07 PM PST 24
Finished Feb 07 01:56:14 PM PST 24
Peak memory 258448 kb
Host smart-c79056ba-a30e-43c5-826a-bb0d6b911ff5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549039914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1549039914
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.3052562989
Short name T619
Test name
Test status
Simulation time 1038038900 ps
CPU time 158.78 seconds
Started Feb 07 01:54:09 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 291972 kb
Host smart-81cacef1-bc49-4064-8c42-c80b1abc4608
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052562989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.3052562989
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.422614987
Short name T113
Test name
Test status
Simulation time 28320826900 ps
CPU time 218.73 seconds
Started Feb 07 01:54:08 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 288664 kb
Host smart-6b49e95e-e2e0-4da2-ad81-2aef741a4f71
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422614987 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.422614987
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.4268021023
Short name T941
Test name
Test status
Simulation time 54557100 ps
CPU time 33.41 seconds
Started Feb 07 01:54:09 PM PST 24
Finished Feb 07 01:54:44 PM PST 24
Peak memory 272324 kb
Host smart-99d1c1df-b59d-4f60-93f6-cd590a216677
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268021023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.4268021023
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2135966282
Short name T179
Test name
Test status
Simulation time 165144400 ps
CPU time 31.34 seconds
Started Feb 07 01:54:20 PM PST 24
Finished Feb 07 01:54:53 PM PST 24
Peak memory 270844 kb
Host smart-ed34b399-909c-43ee-be52-908bb95a0e03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135966282 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2135966282
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.3094894009
Short name T313
Test name
Test status
Simulation time 2854029400 ps
CPU time 61.8 seconds
Started Feb 07 01:54:12 PM PST 24
Finished Feb 07 01:55:15 PM PST 24
Peak memory 262744 kb
Host smart-088daa71-96e3-4fca-8bff-cf9133b9d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094894009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.3094894009
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.2168412156
Short name T561
Test name
Test status
Simulation time 26395300 ps
CPU time 194.39 seconds
Started Feb 07 01:54:10 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 278888 kb
Host smart-c021fc9e-609c-4947-9f7e-96654fc19171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168412156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2168412156
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.312038639
Short name T942
Test name
Test status
Simulation time 35320600 ps
CPU time 13.72 seconds
Started Feb 07 01:54:19 PM PST 24
Finished Feb 07 01:54:34 PM PST 24
Peak memory 264104 kb
Host smart-640bdaeb-6484-4321-bcd9-c478025d6a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312038639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.312038639
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3200889078
Short name T504
Test name
Test status
Simulation time 16361400 ps
CPU time 15.85 seconds
Started Feb 07 01:54:20 PM PST 24
Finished Feb 07 01:54:37 PM PST 24
Peak memory 273640 kb
Host smart-0ec697d5-51f4-4d15-b8f6-0e87d2e78430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200889078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3200889078
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3859135092
Short name T772
Test name
Test status
Simulation time 5771759100 ps
CPU time 143.44 seconds
Started Feb 07 01:54:10 PM PST 24
Finished Feb 07 01:56:35 PM PST 24
Peak memory 259312 kb
Host smart-40799563-b25f-4ce1-934e-ab084de05487
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859135092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3859135092
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2693146451
Short name T654
Test name
Test status
Simulation time 17099342900 ps
CPU time 199.04 seconds
Started Feb 07 01:54:22 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 283040 kb
Host smart-3894130d-c6e0-4b90-81c4-d4f25e47c15a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693146451 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2693146451
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.557678423
Short name T746
Test name
Test status
Simulation time 51047200 ps
CPU time 133.77 seconds
Started Feb 07 01:54:24 PM PST 24
Finished Feb 07 01:56:38 PM PST 24
Peak memory 262352 kb
Host smart-35c8e392-48aa-4c63-89da-3af26dedab65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557678423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ot
p_reset.557678423
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3370426822
Short name T652
Test name
Test status
Simulation time 147623100 ps
CPU time 37.09 seconds
Started Feb 07 01:54:19 PM PST 24
Finished Feb 07 01:54:57 PM PST 24
Peak memory 272396 kb
Host smart-c1ccca86-73ed-4e38-960e-3ff5141e8019
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370426822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3370426822
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2183002396
Short name T291
Test name
Test status
Simulation time 28859800 ps
CPU time 31.78 seconds
Started Feb 07 01:54:19 PM PST 24
Finished Feb 07 01:54:53 PM PST 24
Peak memory 272432 kb
Host smart-edd6814c-ddf4-437a-a913-7b3c56d07c49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183002396 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2183002396
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.1389479020
Short name T709
Test name
Test status
Simulation time 397707900 ps
CPU time 58.82 seconds
Started Feb 07 01:54:26 PM PST 24
Finished Feb 07 01:55:26 PM PST 24
Peak memory 262656 kb
Host smart-7cfa1a25-773c-4b22-ba59-859c585f6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389479020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.1389479020
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1345942988
Short name T633
Test name
Test status
Simulation time 21612500 ps
CPU time 102.34 seconds
Started Feb 07 01:54:11 PM PST 24
Finished Feb 07 01:55:55 PM PST 24
Peak memory 275088 kb
Host smart-dbd1ce12-750e-415e-99b4-80a5bab19680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345942988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1345942988
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.1124742919
Short name T1
Test name
Test status
Simulation time 61079200 ps
CPU time 13.41 seconds
Started Feb 07 01:54:23 PM PST 24
Finished Feb 07 01:54:38 PM PST 24
Peak memory 264076 kb
Host smart-8106a456-04ff-4293-90ce-d68acb97b020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124742919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
1124742919
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.277586894
Short name T593
Test name
Test status
Simulation time 16898000 ps
CPU time 13.48 seconds
Started Feb 07 01:54:22 PM PST 24
Finished Feb 07 01:54:37 PM PST 24
Peak memory 283076 kb
Host smart-68015c32-27e8-441c-9270-fb1b77760698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277586894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.277586894
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3131258847
Short name T634
Test name
Test status
Simulation time 9459091400 ps
CPU time 77.23 seconds
Started Feb 07 01:54:17 PM PST 24
Finished Feb 07 01:55:36 PM PST 24
Peak memory 259648 kb
Host smart-e04c7ac3-7c28-4ce3-b3cf-be4d9b2e589a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131258847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3131258847
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.4203977819
Short name T160
Test name
Test status
Simulation time 2651535700 ps
CPU time 162.17 seconds
Started Feb 07 01:54:26 PM PST 24
Finished Feb 07 01:57:10 PM PST 24
Peak memory 288744 kb
Host smart-59c473a5-c735-42a7-b24c-6c36403a5083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203977819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.4203977819
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3718917520
Short name T119
Test name
Test status
Simulation time 16163263300 ps
CPU time 193.94 seconds
Started Feb 07 01:54:20 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 288696 kb
Host smart-e8e9b0ba-d2ef-4915-9253-ffb516601001
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718917520 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.3718917520
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.2472343630
Short name T411
Test name
Test status
Simulation time 69477600 ps
CPU time 111.33 seconds
Started Feb 07 01:54:18 PM PST 24
Finished Feb 07 01:56:11 PM PST 24
Peak memory 258276 kb
Host smart-795a08a6-c0ab-4c74-9308-3f03410091e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472343630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.2472343630
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3349751513
Short name T819
Test name
Test status
Simulation time 76037100 ps
CPU time 31.15 seconds
Started Feb 07 01:54:20 PM PST 24
Finished Feb 07 01:54:53 PM PST 24
Peak memory 272272 kb
Host smart-529ebcc2-9f62-4235-a6fa-cf07ba19baeb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349751513 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3349751513
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.1866533857
Short name T817
Test name
Test status
Simulation time 1792093200 ps
CPU time 60.02 seconds
Started Feb 07 01:54:27 PM PST 24
Finished Feb 07 01:55:28 PM PST 24
Peak memory 261848 kb
Host smart-73b6c625-179c-410d-bba7-5c8818bce77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866533857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1866533857
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.868544809
Short name T865
Test name
Test status
Simulation time 27779200 ps
CPU time 13.97 seconds
Started Feb 07 01:54:33 PM PST 24
Finished Feb 07 01:54:47 PM PST 24
Peak memory 264032 kb
Host smart-c1b1aab3-bfe0-4efb-b75f-748e57b69963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868544809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.868544809
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1702819200
Short name T694
Test name
Test status
Simulation time 15722600 ps
CPU time 16.56 seconds
Started Feb 07 01:54:29 PM PST 24
Finished Feb 07 01:54:46 PM PST 24
Peak memory 273744 kb
Host smart-9d3afde5-683b-4dd3-9bf5-8131b63b0f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702819200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1702819200
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3156500393
Short name T445
Test name
Test status
Simulation time 2312163100 ps
CPU time 161.94 seconds
Started Feb 07 01:54:22 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 292316 kb
Host smart-9bcf685a-a70f-4e48-af76-7f2d9a2d3183
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156500393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3156500393
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3485197093
Short name T465
Test name
Test status
Simulation time 14695202700 ps
CPU time 243.63 seconds
Started Feb 07 01:54:28 PM PST 24
Finished Feb 07 01:58:33 PM PST 24
Peak memory 283068 kb
Host smart-a14f1523-246d-4302-addb-8c296c23987f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485197093 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3485197093
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.4062440178
Short name T80
Test name
Test status
Simulation time 100293400 ps
CPU time 113.07 seconds
Started Feb 07 01:54:23 PM PST 24
Finished Feb 07 01:56:17 PM PST 24
Peak memory 262140 kb
Host smart-d5a7cc5c-e26e-49f3-888b-0267f757a68d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062440178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.4062440178
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1346393049
Short name T421
Test name
Test status
Simulation time 8211173100 ps
CPU time 66.17 seconds
Started Feb 07 01:54:36 PM PST 24
Finished Feb 07 01:55:43 PM PST 24
Peak memory 261848 kb
Host smart-aecfc0e5-faef-45ef-a28d-7b573de09845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346393049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1346393049
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.3930171275
Short name T842
Test name
Test status
Simulation time 145021400 ps
CPU time 147.34 seconds
Started Feb 07 01:54:23 PM PST 24
Finished Feb 07 01:56:51 PM PST 24
Peak memory 274876 kb
Host smart-11850121-8e73-43bf-becb-0068545b28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930171275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3930171275
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.3719879848
Short name T929
Test name
Test status
Simulation time 133252000 ps
CPU time 13.85 seconds
Started Feb 07 01:54:31 PM PST 24
Finished Feb 07 01:54:46 PM PST 24
Peak memory 264148 kb
Host smart-fc2183fe-ef15-496b-a17c-e7c88df92e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719879848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
3719879848
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.2915732061
Short name T731
Test name
Test status
Simulation time 18805800 ps
CPU time 13.56 seconds
Started Feb 07 01:54:33 PM PST 24
Finished Feb 07 01:54:48 PM PST 24
Peak memory 273588 kb
Host smart-ed7b5231-1856-4a1a-9427-d9b8f41dbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915732061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2915732061
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1591379799
Short name T101
Test name
Test status
Simulation time 10224800 ps
CPU time 22.02 seconds
Started Feb 07 01:54:47 PM PST 24
Finished Feb 07 01:55:10 PM PST 24
Peak memory 272440 kb
Host smart-f4f0a124-40f9-4c93-9554-fbd43f17a2af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591379799 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1591379799
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3600735065
Short name T379
Test name
Test status
Simulation time 4151335900 ps
CPU time 151.28 seconds
Started Feb 07 01:54:33 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 258400 kb
Host smart-0a7dcbba-4857-4b0a-8aa9-1512afb558b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600735065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3600735065
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.3062799439
Short name T274
Test name
Test status
Simulation time 1294785300 ps
CPU time 162.46 seconds
Started Feb 07 01:54:47 PM PST 24
Finished Feb 07 01:57:30 PM PST 24
Peak memory 292000 kb
Host smart-fb4dfea6-04f1-418b-a216-382f6583b5a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062799439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.3062799439
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.425398354
Short name T331
Test name
Test status
Simulation time 8198824800 ps
CPU time 181.61 seconds
Started Feb 07 01:54:47 PM PST 24
Finished Feb 07 01:57:50 PM PST 24
Peak memory 283124 kb
Host smart-d7d84a89-9e51-43e2-b356-e824e9d67c5b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425398354 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.425398354
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.330428833
Short name T708
Test name
Test status
Simulation time 80062300 ps
CPU time 110.05 seconds
Started Feb 07 01:54:31 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 258152 kb
Host smart-e133aa25-6edc-44e2-8ab6-c4676a0fad9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330428833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ot
p_reset.330428833
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2658855883
Short name T544
Test name
Test status
Simulation time 84617900 ps
CPU time 30.98 seconds
Started Feb 07 01:54:32 PM PST 24
Finished Feb 07 01:55:04 PM PST 24
Peak memory 272420 kb
Host smart-49e00c92-f437-48b1-95f4-3e4343ed9611
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658855883 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2658855883
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3473589629
Short name T375
Test name
Test status
Simulation time 186986300 ps
CPU time 121.8 seconds
Started Feb 07 01:54:33 PM PST 24
Finished Feb 07 01:56:36 PM PST 24
Peak memory 276120 kb
Host smart-249605a2-cd8b-436c-b14c-895f265d97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473589629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3473589629
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.4185667424
Short name T530
Test name
Test status
Simulation time 341804300 ps
CPU time 13.74 seconds
Started Feb 07 01:54:38 PM PST 24
Finished Feb 07 01:54:52 PM PST 24
Peak memory 264044 kb
Host smart-51261abb-9202-49bc-9744-ce2cb13fba65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185667424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
4185667424
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2776250436
Short name T798
Test name
Test status
Simulation time 74681100 ps
CPU time 15.96 seconds
Started Feb 07 01:54:41 PM PST 24
Finished Feb 07 01:54:58 PM PST 24
Peak memory 273772 kb
Host smart-d50e4ee8-66fc-44df-8e0d-29793f93451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776250436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2776250436
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.1597373654
Short name T96
Test name
Test status
Simulation time 12623200 ps
CPU time 20.69 seconds
Started Feb 07 01:54:38 PM PST 24
Finished Feb 07 01:54:59 PM PST 24
Peak memory 272332 kb
Host smart-0633c207-fe36-431f-b750-b0a893bd788e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597373654 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.1597373654
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.1108504660
Short name T407
Test name
Test status
Simulation time 13033518900 ps
CPU time 210.92 seconds
Started Feb 07 01:54:37 PM PST 24
Finished Feb 07 01:58:09 PM PST 24
Peak memory 257864 kb
Host smart-5fb64084-f868-4a9b-9adb-479087548bf8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108504660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.1108504660
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1514099580
Short name T506
Test name
Test status
Simulation time 4596600800 ps
CPU time 162.35 seconds
Started Feb 07 01:54:37 PM PST 24
Finished Feb 07 01:57:21 PM PST 24
Peak memory 292916 kb
Host smart-fac525e7-c6fb-4ee0-9c9f-c5eb51682bcc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514099580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1514099580
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3066441555
Short name T426
Test name
Test status
Simulation time 8718067700 ps
CPU time 209.41 seconds
Started Feb 07 01:54:36 PM PST 24
Finished Feb 07 01:58:07 PM PST 24
Peak memory 282960 kb
Host smart-510af8c1-ff3d-482e-9fa4-9bb182d667ae
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066441555 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3066441555
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.4021065368
Short name T674
Test name
Test status
Simulation time 53986000 ps
CPU time 31.12 seconds
Started Feb 07 01:54:42 PM PST 24
Finished Feb 07 01:55:13 PM PST 24
Peak memory 272408 kb
Host smart-19292cb9-5559-4c2c-a787-ea173a140494
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021065368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.4021065368
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.477974295
Short name T624
Test name
Test status
Simulation time 33591500 ps
CPU time 29.01 seconds
Started Feb 07 01:54:40 PM PST 24
Finished Feb 07 01:55:10 PM PST 24
Peak memory 272476 kb
Host smart-4ac6e4bc-7cee-432b-b1bd-803db3d50bca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477974295 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.477974295
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1811237785
Short name T289
Test name
Test status
Simulation time 1125816700 ps
CPU time 64.96 seconds
Started Feb 07 01:54:39 PM PST 24
Finished Feb 07 01:55:44 PM PST 24
Peak memory 262824 kb
Host smart-e1e0989c-e82b-4f36-85db-e94a4d463722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811237785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1811237785
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3625722197
Short name T827
Test name
Test status
Simulation time 97403200 ps
CPU time 147.72 seconds
Started Feb 07 01:54:37 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 275976 kb
Host smart-32fe4cb6-4a06-42ca-a433-419eab88cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625722197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3625722197
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1566762349
Short name T928
Test name
Test status
Simulation time 159668800 ps
CPU time 14.1 seconds
Started Feb 07 01:54:52 PM PST 24
Finished Feb 07 01:55:07 PM PST 24
Peak memory 264052 kb
Host smart-a87537b6-035a-454d-9e3d-85222ebd7e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566762349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1566762349
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.2594102681
Short name T684
Test name
Test status
Simulation time 13434800 ps
CPU time 16.18 seconds
Started Feb 07 01:54:46 PM PST 24
Finished Feb 07 01:55:03 PM PST 24
Peak memory 273640 kb
Host smart-d9dfb324-0171-4238-a39a-81a70cb751b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594102681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2594102681
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1815616860
Short name T417
Test name
Test status
Simulation time 2245195100 ps
CPU time 98.33 seconds
Started Feb 07 01:54:45 PM PST 24
Finished Feb 07 01:56:24 PM PST 24
Peak memory 257880 kb
Host smart-693454ed-5c51-4ea9-8d43-a1578fd2ef03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815616860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1815616860
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.1842561044
Short name T721
Test name
Test status
Simulation time 2499786100 ps
CPU time 154.5 seconds
Started Feb 07 01:54:46 PM PST 24
Finished Feb 07 01:57:22 PM PST 24
Peak memory 291132 kb
Host smart-3d20e3a6-b0f8-47f4-bfd2-4bb8aaa3bec7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842561044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.1842561044
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3460207426
Short name T328
Test name
Test status
Simulation time 8267944300 ps
CPU time 247.52 seconds
Started Feb 07 01:54:50 PM PST 24
Finished Feb 07 01:58:58 PM PST 24
Peak memory 283140 kb
Host smart-c8ef8fd2-0d3d-47e0-a613-b39834718f72
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460207426 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3460207426
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2668255622
Short name T403
Test name
Test status
Simulation time 64943900 ps
CPU time 130.97 seconds
Started Feb 07 01:54:45 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 258264 kb
Host smart-35aa7361-224b-4627-b224-67de573c8f93
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668255622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2668255622
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2930343237
Short name T39
Test name
Test status
Simulation time 173192200 ps
CPU time 31.12 seconds
Started Feb 07 01:54:44 PM PST 24
Finished Feb 07 01:55:16 PM PST 24
Peak memory 272388 kb
Host smart-80c7ee82-02bc-4e1d-b438-6617a2a39385
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930343237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2930343237
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1739932076
Short name T449
Test name
Test status
Simulation time 2170467700 ps
CPU time 76.96 seconds
Started Feb 07 01:54:45 PM PST 24
Finished Feb 07 01:56:03 PM PST 24
Peak memory 263812 kb
Host smart-9c78f1d0-3fa5-4d89-9e1a-d7954ed0bd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739932076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1739932076
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2034439270
Short name T529
Test name
Test status
Simulation time 152952500 ps
CPU time 102.12 seconds
Started Feb 07 01:54:49 PM PST 24
Finished Feb 07 01:56:32 PM PST 24
Peak memory 273704 kb
Host smart-c6ab6cf3-e9dc-4a47-83b6-85a3ec388591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034439270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2034439270
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2157997695
Short name T377
Test name
Test status
Simulation time 92882400 ps
CPU time 13.56 seconds
Started Feb 07 01:55:05 PM PST 24
Finished Feb 07 01:55:19 PM PST 24
Peak memory 264100 kb
Host smart-deac0d6c-c151-4061-8d0c-dc9e7c83c836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157997695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2157997695
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.560649389
Short name T335
Test name
Test status
Simulation time 36132543200 ps
CPU time 268.88 seconds
Started Feb 07 01:55:06 PM PST 24
Finished Feb 07 01:59:36 PM PST 24
Peak memory 288676 kb
Host smart-a48894a6-8ddb-4b55-93e3-7c46b6bbb91c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560649389 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.560649389
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.3893291736
Short name T874
Test name
Test status
Simulation time 28806200 ps
CPU time 29.22 seconds
Started Feb 07 01:55:08 PM PST 24
Finished Feb 07 01:55:39 PM PST 24
Peak memory 272408 kb
Host smart-d58ebb07-d8e6-4df0-bcda-676487fc7aba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893291736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.3893291736
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3821804189
Short name T762
Test name
Test status
Simulation time 64021700 ps
CPU time 32.19 seconds
Started Feb 07 01:54:57 PM PST 24
Finished Feb 07 01:55:30 PM PST 24
Peak memory 272408 kb
Host smart-1a4b35d8-fe0b-4017-ba40-06542417d8b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821804189 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3821804189
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.148356765
Short name T318
Test name
Test status
Simulation time 9024122600 ps
CPU time 78.96 seconds
Started Feb 07 01:55:01 PM PST 24
Finished Feb 07 01:56:20 PM PST 24
Peak memory 262720 kb
Host smart-e7ad640b-95d1-4ce2-901f-30cb82f9ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148356765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.148356765
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.271603544
Short name T217
Test name
Test status
Simulation time 20728000 ps
CPU time 124.94 seconds
Started Feb 07 01:54:47 PM PST 24
Finished Feb 07 01:56:53 PM PST 24
Peak memory 275144 kb
Host smart-361fd62a-e2f7-4025-9a5d-6d8c98b22013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271603544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.271603544
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.675368734
Short name T406
Test name
Test status
Simulation time 68047200 ps
CPU time 14.2 seconds
Started Feb 07 01:55:10 PM PST 24
Finished Feb 07 01:55:26 PM PST 24
Peak memory 264084 kb
Host smart-9a75518c-e186-473a-92b4-0ff91b1da2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675368734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.675368734
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.1601861017
Short name T713
Test name
Test status
Simulation time 84335900 ps
CPU time 13.27 seconds
Started Feb 07 01:55:11 PM PST 24
Finished Feb 07 01:55:25 PM PST 24
Peak memory 273656 kb
Host smart-e2518c80-3a36-44f7-8220-b0dd86df69e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601861017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1601861017
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.3624999424
Short name T103
Test name
Test status
Simulation time 10122400 ps
CPU time 21.37 seconds
Started Feb 07 01:54:59 PM PST 24
Finished Feb 07 01:55:21 PM PST 24
Peak memory 272460 kb
Host smart-36be2a20-b661-4aa1-afec-fe8ce0e10083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624999424 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.3624999424
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.87863182
Short name T610
Test name
Test status
Simulation time 5096297600 ps
CPU time 44.77 seconds
Started Feb 07 01:55:09 PM PST 24
Finished Feb 07 01:55:55 PM PST 24
Peak memory 258148 kb
Host smart-c96f439b-d452-4ee7-88ec-b909a1e3b017
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87863182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw
_sec_otp.87863182
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2188609834
Short name T725
Test name
Test status
Simulation time 25598574700 ps
CPU time 204.04 seconds
Started Feb 07 01:55:09 PM PST 24
Finished Feb 07 01:58:33 PM PST 24
Peak memory 283020 kb
Host smart-adfb7223-9a71-4f0a-9cc1-3299886c2574
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188609834 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2188609834
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.878157677
Short name T835
Test name
Test status
Simulation time 1181761400 ps
CPU time 63.77 seconds
Started Feb 07 01:55:20 PM PST 24
Finished Feb 07 01:56:25 PM PST 24
Peak memory 260688 kb
Host smart-3ab452f5-ba9a-40ee-97dc-bd2e6410d5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878157677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.878157677
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3374403419
Short name T603
Test name
Test status
Simulation time 359748200 ps
CPU time 153.38 seconds
Started Feb 07 01:54:58 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 276668 kb
Host smart-d058a2a8-1198-4a5e-8468-05be4a20b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374403419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3374403419
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.1004486664
Short name T915
Test name
Test status
Simulation time 106957300 ps
CPU time 13.96 seconds
Started Feb 07 01:55:19 PM PST 24
Finished Feb 07 01:55:35 PM PST 24
Peak memory 264040 kb
Host smart-99c22f49-ee08-479c-b3aa-a1c0f8017482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004486664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
1004486664
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3733682229
Short name T458
Test name
Test status
Simulation time 13229100 ps
CPU time 16.19 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:55:39 PM PST 24
Peak memory 273684 kb
Host smart-4d76f25a-0123-44bb-b740-9c2eb6857543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733682229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3733682229
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.215938516
Short name T216
Test name
Test status
Simulation time 1074580800 ps
CPU time 95.53 seconds
Started Feb 07 01:55:08 PM PST 24
Finished Feb 07 01:56:45 PM PST 24
Peak memory 259232 kb
Host smart-e3d93697-7ca9-4547-9c1e-351283b47777
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215938516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h
w_sec_otp.215938516
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3478475402
Short name T822
Test name
Test status
Simulation time 20799783000 ps
CPU time 212.78 seconds
Started Feb 07 01:55:16 PM PST 24
Finished Feb 07 01:58:51 PM PST 24
Peak memory 292776 kb
Host smart-d13f09ac-8a81-436f-88b4-ebdb25f9ee9b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478475402 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3478475402
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3438844016
Short name T659
Test name
Test status
Simulation time 427098100 ps
CPU time 33.76 seconds
Started Feb 07 01:55:21 PM PST 24
Finished Feb 07 01:55:56 PM PST 24
Peak memory 272320 kb
Host smart-82282565-cb1f-4097-b383-7abf70819eae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438844016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3438844016
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1822007818
Short name T28
Test name
Test status
Simulation time 9361570700 ps
CPU time 79.02 seconds
Started Feb 07 01:55:15 PM PST 24
Finished Feb 07 01:56:37 PM PST 24
Peak memory 257900 kb
Host smart-dff351ce-78aa-4e79-91cc-034b6faa4b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822007818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1822007818
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.2637109843
Short name T912
Test name
Test status
Simulation time 19865000 ps
CPU time 50.29 seconds
Started Feb 07 01:55:17 PM PST 24
Finished Feb 07 01:56:09 PM PST 24
Peak memory 268848 kb
Host smart-51a03cfc-74d4-462e-a824-291ea43b036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637109843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2637109843
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.476062838
Short name T546
Test name
Test status
Simulation time 37993900 ps
CPU time 14.14 seconds
Started Feb 07 01:48:55 PM PST 24
Finished Feb 07 01:49:10 PM PST 24
Peak memory 264044 kb
Host smart-14786d10-764e-470a-ae48-b07edc2e8b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476062838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.476062838
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1882702345
Short name T184
Test name
Test status
Simulation time 33729400 ps
CPU time 13.87 seconds
Started Feb 07 01:48:51 PM PST 24
Finished Feb 07 01:49:06 PM PST 24
Peak memory 264072 kb
Host smart-7863297b-af96-4aef-b396-8ff6e07e5841
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882702345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1882702345
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.685658588
Short name T596
Test name
Test status
Simulation time 36644100 ps
CPU time 16 seconds
Started Feb 07 01:48:55 PM PST 24
Finished Feb 07 01:49:12 PM PST 24
Peak memory 273704 kb
Host smart-2d81c022-a177-49c9-abe4-0a6bade54b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685658588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.685658588
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.349787358
Short name T924
Test name
Test status
Simulation time 368321700 ps
CPU time 107.94 seconds
Started Feb 07 01:48:52 PM PST 24
Finished Feb 07 01:50:40 PM PST 24
Peak memory 280488 kb
Host smart-88660917-489f-4429-be2f-22748a1ddb93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349787358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_derr_detect.349787358
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3227712274
Short name T48
Test name
Test status
Simulation time 17403154500 ps
CPU time 381.23 seconds
Started Feb 07 01:48:46 PM PST 24
Finished Feb 07 01:55:08 PM PST 24
Peak memory 259624 kb
Host smart-d1c13c0d-e39e-4cc6-bff7-1491dbd62fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227712274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3227712274
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2811000620
Short name T685
Test name
Test status
Simulation time 8303053300 ps
CPU time 2162.78 seconds
Started Feb 07 01:48:40 PM PST 24
Finished Feb 07 02:24:45 PM PST 24
Peak memory 263964 kb
Host smart-bddfc11e-8fb7-4666-82da-e9c8cd45cf3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811000620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.2811000620
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1687384081
Short name T195
Test name
Test status
Simulation time 3433955100 ps
CPU time 2149.28 seconds
Started Feb 07 01:48:44 PM PST 24
Finished Feb 07 02:24:34 PM PST 24
Peak memory 263956 kb
Host smart-b5f656b8-7773-4c1f-9bd5-a6260284e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687384081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1687384081
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.814720978
Short name T710
Test name
Test status
Simulation time 1150675000 ps
CPU time 1066.97 seconds
Started Feb 07 01:48:40 PM PST 24
Finished Feb 07 02:06:29 PM PST 24
Peak memory 272272 kb
Host smart-d2c18bcf-1bc7-4eb8-854f-89d86d36b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814720978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.814720978
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.965826945
Short name T692
Test name
Test status
Simulation time 548137700 ps
CPU time 27.74 seconds
Started Feb 07 01:48:42 PM PST 24
Finished Feb 07 01:49:11 PM PST 24
Peak memory 264048 kb
Host smart-ccb4da3d-7935-4de0-97d2-6788f8e4481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965826945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.965826945
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.4131170115
Short name T850
Test name
Test status
Simulation time 1166714200 ps
CPU time 34.12 seconds
Started Feb 07 01:48:53 PM PST 24
Finished Feb 07 01:49:28 PM PST 24
Peak memory 272264 kb
Host smart-4580631a-cd89-4291-9571-ab83b0c6f548
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131170115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.4131170115
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2813339052
Short name T108
Test name
Test status
Simulation time 1473043899700 ps
CPU time 1638.06 seconds
Started Feb 07 01:48:41 PM PST 24
Finished Feb 07 02:16:00 PM PST 24
Peak memory 264096 kb
Host smart-c11dbaca-2e95-4ce6-b44a-4c35f7503d64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813339052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.2813339052
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.818433588
Short name T739
Test name
Test status
Simulation time 36624900 ps
CPU time 13.53 seconds
Started Feb 07 01:48:57 PM PST 24
Finished Feb 07 01:49:11 PM PST 24
Peak memory 264056 kb
Host smart-315bc5fb-fdee-4123-ac3d-cc434a710b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818433588 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.818433588
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2569238023
Short name T105
Test name
Test status
Simulation time 320269353500 ps
CPU time 853.62 seconds
Started Feb 07 01:48:46 PM PST 24
Finished Feb 07 02:03:01 PM PST 24
Peak memory 258304 kb
Host smart-cbed7d3d-3a7a-4122-bbe7-dbe18853f700
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569238023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2569238023
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.382992055
Short name T523
Test name
Test status
Simulation time 4879955900 ps
CPU time 150.98 seconds
Started Feb 07 01:48:46 PM PST 24
Finished Feb 07 01:51:18 PM PST 24
Peak memory 258404 kb
Host smart-dc3a3daa-14df-49ba-b476-d40009472ba7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382992055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw
_sec_otp.382992055
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.1736332861
Short name T34
Test name
Test status
Simulation time 3531375200 ps
CPU time 588.18 seconds
Started Feb 07 01:48:54 PM PST 24
Finished Feb 07 01:58:43 PM PST 24
Peak memory 322856 kb
Host smart-4ad9e178-9ae7-4abf-9af3-54a6d9d0c38e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736332861 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.1736332861
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1209854029
Short name T542
Test name
Test status
Simulation time 1326527200 ps
CPU time 163.33 seconds
Started Feb 07 01:48:41 PM PST 24
Finished Feb 07 01:51:26 PM PST 24
Peak memory 292196 kb
Host smart-55252a3d-7f8f-4d09-8231-e27266f7f44b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209854029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1209854029
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.732946985
Short name T630
Test name
Test status
Simulation time 87708108300 ps
CPU time 332.03 seconds
Started Feb 07 01:48:54 PM PST 24
Finished Feb 07 01:54:27 PM PST 24
Peak memory 264056 kb
Host smart-7e651ea9-4a13-4d65-b008-94c3742e175a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732
946985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.732946985
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1713835254
Short name T323
Test name
Test status
Simulation time 1017919500 ps
CPU time 92.42 seconds
Started Feb 07 01:48:34 PM PST 24
Finished Feb 07 01:50:07 PM PST 24
Peak memory 257980 kb
Host smart-7c059b90-321f-4e5b-88fd-94f51d745c71
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713835254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1713835254
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2766246810
Short name T715
Test name
Test status
Simulation time 25795600 ps
CPU time 13.69 seconds
Started Feb 07 01:48:53 PM PST 24
Finished Feb 07 01:49:07 PM PST 24
Peak memory 264104 kb
Host smart-fbba23c6-a116-4bef-b268-3a8144a21252
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766246810 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2766246810
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3337707151
Short name T886
Test name
Test status
Simulation time 4462018100 ps
CPU time 173.45 seconds
Started Feb 07 01:48:56 PM PST 24
Finished Feb 07 01:51:50 PM PST 24
Peak memory 292692 kb
Host smart-984f1e8c-c379-4535-aac6-bf3ff5b2dacd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337707151 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3337707151
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3944594905
Short name T908
Test name
Test status
Simulation time 753837500 ps
CPU time 386.37 seconds
Started Feb 07 01:48:41 PM PST 24
Finished Feb 07 01:55:09 PM PST 24
Peak memory 264064 kb
Host smart-e08229fe-a783-42b3-b479-03def7ca27a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944594905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3944594905
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2070107807
Short name T820
Test name
Test status
Simulation time 85152100 ps
CPU time 18.88 seconds
Started Feb 07 01:48:52 PM PST 24
Finished Feb 07 01:49:12 PM PST 24
Peak memory 263280 kb
Host smart-542a8c6b-7d76-400a-b041-b47b00571971
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070107807 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2070107807
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2297758709
Short name T176
Test name
Test status
Simulation time 17190700 ps
CPU time 14.25 seconds
Started Feb 07 01:48:54 PM PST 24
Finished Feb 07 01:49:09 PM PST 24
Peak memory 264244 kb
Host smart-593f5e65-6034-4365-b4c3-e4f95184ea80
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297758709 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2297758709
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.3435718764
Short name T826
Test name
Test status
Simulation time 37434900 ps
CPU time 13.8 seconds
Started Feb 07 01:48:56 PM PST 24
Finished Feb 07 01:49:10 PM PST 24
Peak memory 264052 kb
Host smart-aa86eb59-7e0a-4ed4-af1d-b357d5c487f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435718764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.3435718764
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.683984586
Short name T636
Test name
Test status
Simulation time 109372700 ps
CPU time 462.86 seconds
Started Feb 07 01:48:43 PM PST 24
Finished Feb 07 01:56:27 PM PST 24
Peak memory 280376 kb
Host smart-86765c15-dfe3-4be7-881b-7811fa03dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683984586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.683984586
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3002763768
Short name T264
Test name
Test status
Simulation time 53294100 ps
CPU time 100.1 seconds
Started Feb 07 01:48:49 PM PST 24
Finished Feb 07 01:50:30 PM PST 24
Peak memory 263688 kb
Host smart-77e5254f-37a3-4fc8-a5f0-fecca06ac2dc
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3002763768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3002763768
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.876570770
Short name T366
Test name
Test status
Simulation time 177662700 ps
CPU time 37.96 seconds
Started Feb 07 01:48:53 PM PST 24
Finished Feb 07 01:49:32 PM PST 24
Peak memory 272396 kb
Host smart-c17e91eb-8fac-4fea-8aa9-61e5a0ae224c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876570770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_re_evict.876570770
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.877737313
Short name T166
Test name
Test status
Simulation time 18817900 ps
CPU time 21.6 seconds
Started Feb 07 01:48:46 PM PST 24
Finished Feb 07 01:49:08 PM PST 24
Peak memory 264184 kb
Host smart-6937f3b7-3fd3-4e80-9577-649c024c52cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877737313 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.877737313
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3348175160
Short name T823
Test name
Test status
Simulation time 135507500 ps
CPU time 22.02 seconds
Started Feb 07 01:48:42 PM PST 24
Finished Feb 07 01:49:05 PM PST 24
Peak memory 264120 kb
Host smart-7f78c0d8-b619-4db8-8674-4558b84b94b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348175160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3348175160
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.604697893
Short name T627
Test name
Test status
Simulation time 1662420100 ps
CPU time 104.08 seconds
Started Feb 07 01:48:46 PM PST 24
Finished Feb 07 01:50:31 PM PST 24
Peak memory 280632 kb
Host smart-5056ba8e-e7fe-4ad8-8fc3-5b5c8981aa16
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604697893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_ro.604697893
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1688499252
Short name T540
Test name
Test status
Simulation time 722371900 ps
CPU time 141.55 seconds
Started Feb 07 01:48:43 PM PST 24
Finished Feb 07 01:51:06 PM PST 24
Peak memory 294512 kb
Host smart-9a29e694-f291-4fd5-aba4-86d0b03eaf05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688499252 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1688499252
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.834585645
Short name T468
Test name
Test status
Simulation time 3472785100 ps
CPU time 556.6 seconds
Started Feb 07 01:48:56 PM PST 24
Finished Feb 07 01:58:13 PM PST 24
Peak memory 313236 kb
Host smart-a5a383eb-95ef-4947-8ea0-9558c7877832
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834585645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr
l_rw.834585645
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.68419965
Short name T791
Test name
Test status
Simulation time 41193400 ps
CPU time 30.88 seconds
Started Feb 07 01:48:57 PM PST 24
Finished Feb 07 01:49:28 PM PST 24
Peak memory 274104 kb
Host smart-6628aab6-5e6d-4d76-a4a6-32de1a0994f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68419965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_rw_evict.68419965
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1521675000
Short name T167
Test name
Test status
Simulation time 37779200 ps
CPU time 32.7 seconds
Started Feb 07 01:48:51 PM PST 24
Finished Feb 07 01:49:24 PM PST 24
Peak memory 272416 kb
Host smart-f34e9aa6-1d38-4172-b205-8d72c36a7cc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521675000 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1521675000
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.3820971904
Short name T218
Test name
Test status
Simulation time 16375330600 ps
CPU time 416.82 seconds
Started Feb 07 01:48:42 PM PST 24
Finished Feb 07 01:55:40 PM PST 24
Peak memory 310312 kb
Host smart-109d066b-2dde-40fd-92ad-bf94893320d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820971904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.3820971904
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.2974252733
Short name T154
Test name
Test status
Simulation time 3784706400 ps
CPU time 4700.68 seconds
Started Feb 07 01:48:57 PM PST 24
Finished Feb 07 03:07:19 PM PST 24
Peak memory 284860 kb
Host smart-1df2a1af-7f90-447f-a2ed-606971ff7df9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974252733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2974252733
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.637547214
Short name T386
Test name
Test status
Simulation time 5703334400 ps
CPU time 73.57 seconds
Started Feb 07 01:48:52 PM PST 24
Finished Feb 07 01:50:06 PM PST 24
Peak memory 257816 kb
Host smart-2d0c56c8-0d58-4483-852d-b3b9325a9c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637547214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.637547214
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1365299070
Short name T498
Test name
Test status
Simulation time 421442600 ps
CPU time 55.28 seconds
Started Feb 07 01:48:43 PM PST 24
Finished Feb 07 01:49:39 PM PST 24
Peak memory 264176 kb
Host smart-1d518ea4-868e-4f35-89ae-3dcbc049d9af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365299070 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1365299070
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3225025056
Short name T699
Test name
Test status
Simulation time 42757500 ps
CPU time 101.95 seconds
Started Feb 07 01:48:48 PM PST 24
Finished Feb 07 01:50:31 PM PST 24
Peak memory 274808 kb
Host smart-aed27c6c-fba4-4624-ab44-29f1f9f7d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225025056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3225025056
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1075945234
Short name T766
Test name
Test status
Simulation time 111897000 ps
CPU time 26.49 seconds
Started Feb 07 01:48:43 PM PST 24
Finished Feb 07 01:49:10 PM PST 24
Peak memory 257888 kb
Host smart-6c24830f-85ba-4159-bcdb-681a0dd1650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075945234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1075945234
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.3652096315
Short name T485
Test name
Test status
Simulation time 292650600 ps
CPU time 315.05 seconds
Started Feb 07 01:48:56 PM PST 24
Finished Feb 07 01:54:11 PM PST 24
Peak memory 276196 kb
Host smart-843d02fd-45df-4f0f-96ca-bb8a2dbcc490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652096315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.3652096315
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.1416324187
Short name T446
Test name
Test status
Simulation time 24356900 ps
CPU time 26.86 seconds
Started Feb 07 01:48:32 PM PST 24
Finished Feb 07 01:48:59 PM PST 24
Peak memory 260772 kb
Host smart-367c0251-f736-4b53-b4d5-50d323491655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416324187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1416324187
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1650619447
Short name T373
Test name
Test status
Simulation time 15500878900 ps
CPU time 208.54 seconds
Started Feb 07 01:48:40 PM PST 24
Finished Feb 07 01:52:10 PM PST 24
Peak memory 264000 kb
Host smart-56604717-f33e-43a6-8154-8cad398e3ae3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650619447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_wo.1650619447
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1287959524
Short name T557
Test name
Test status
Simulation time 69179200 ps
CPU time 13.59 seconds
Started Feb 07 01:55:20 PM PST 24
Finished Feb 07 01:55:35 PM PST 24
Peak memory 264092 kb
Host smart-700c5c19-3dd9-4c54-98ee-f59fd823635f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287959524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1287959524
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3400624756
Short name T387
Test name
Test status
Simulation time 27728300 ps
CPU time 15.92 seconds
Started Feb 07 01:55:21 PM PST 24
Finished Feb 07 01:55:38 PM PST 24
Peak memory 273784 kb
Host smart-40dabb69-0f3d-4587-82f9-bd7c86af306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400624756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3400624756
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.2442743034
Short name T688
Test name
Test status
Simulation time 16876500 ps
CPU time 22.03 seconds
Started Feb 07 01:55:23 PM PST 24
Finished Feb 07 01:55:46 PM PST 24
Peak memory 272508 kb
Host smart-ab6f6291-1bb8-4535-bacb-12b9e4abb9f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442743034 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.2442743034
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.982453376
Short name T454
Test name
Test status
Simulation time 5210075500 ps
CPU time 213.43 seconds
Started Feb 07 01:55:16 PM PST 24
Finished Feb 07 01:58:52 PM PST 24
Peak memory 257844 kb
Host smart-9f04dc0e-cb99-434d-b3fa-54cf56e41203
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982453376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h
w_sec_otp.982453376
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.1189905350
Short name T678
Test name
Test status
Simulation time 150420700 ps
CPU time 110.26 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:57:13 PM PST 24
Peak memory 258448 kb
Host smart-e105a2b7-ed85-45fe-8a92-3e1cae536e55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189905350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.1189905350
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1302524535
Short name T816
Test name
Test status
Simulation time 4547888800 ps
CPU time 76.57 seconds
Started Feb 07 01:55:17 PM PST 24
Finished Feb 07 01:56:35 PM PST 24
Peak memory 257876 kb
Host smart-9b769f00-b397-4b6e-a1e7-0f13735c725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302524535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1302524535
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2854039668
Short name T735
Test name
Test status
Simulation time 184059400 ps
CPU time 100.81 seconds
Started Feb 07 01:55:16 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 275224 kb
Host smart-6e92b4b9-c0f8-463f-9f55-986cde9d0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854039668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2854039668
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.3632166986
Short name T382
Test name
Test status
Simulation time 109283400 ps
CPU time 13.64 seconds
Started Feb 07 01:55:25 PM PST 24
Finished Feb 07 01:55:39 PM PST 24
Peak memory 263996 kb
Host smart-8026470c-1057-498d-8ab3-7d1797a6dacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632166986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
3632166986
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2381910192
Short name T898
Test name
Test status
Simulation time 41156400 ps
CPU time 13.33 seconds
Started Feb 07 01:55:23 PM PST 24
Finished Feb 07 01:55:37 PM PST 24
Peak memory 273620 kb
Host smart-24e6e498-45ba-45bf-8e9b-890579e02ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381910192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2381910192
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1252761371
Short name T367
Test name
Test status
Simulation time 1336045900 ps
CPU time 47.78 seconds
Started Feb 07 01:55:24 PM PST 24
Finished Feb 07 01:56:13 PM PST 24
Peak memory 258492 kb
Host smart-94c14bec-d7ee-4075-a877-962f13bebdcd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252761371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1252761371
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.1746659787
Short name T580
Test name
Test status
Simulation time 4662922800 ps
CPU time 65.49 seconds
Started Feb 07 01:55:24 PM PST 24
Finished Feb 07 01:56:31 PM PST 24
Peak memory 262780 kb
Host smart-3ec1ab5d-e4f4-432a-a02a-d4f78382f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746659787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1746659787
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1916344290
Short name T467
Test name
Test status
Simulation time 81757600 ps
CPU time 51.51 seconds
Started Feb 07 01:55:21 PM PST 24
Finished Feb 07 01:56:13 PM PST 24
Peak memory 268936 kb
Host smart-4df26e25-ca6e-4716-bff9-b66fbe3efd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916344290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1916344290
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.597570573
Short name T783
Test name
Test status
Simulation time 116596000 ps
CPU time 16.02 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:55:39 PM PST 24
Peak memory 273676 kb
Host smart-36b1a0ba-b68d-46c6-b17b-ad4891550f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597570573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.597570573
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.3889600683
Short name T705
Test name
Test status
Simulation time 75830600 ps
CPU time 135 seconds
Started Feb 07 01:55:21 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 258204 kb
Host smart-e3d2a348-223a-4997-801a-f949ce7e1cc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889600683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.3889600683
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.1500765264
Short name T727
Test name
Test status
Simulation time 359363600 ps
CPU time 50.95 seconds
Started Feb 07 01:55:28 PM PST 24
Finished Feb 07 01:56:19 PM PST 24
Peak memory 261824 kb
Host smart-e0c183ad-38bb-40b8-9f4b-93503bc589fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500765264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1500765264
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.3411540128
Short name T440
Test name
Test status
Simulation time 1397400000 ps
CPU time 165.78 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 280344 kb
Host smart-9f26063e-cd6d-4575-8188-e456da2e19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411540128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3411540128
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.1538261697
Short name T410
Test name
Test status
Simulation time 92741300 ps
CPU time 13.58 seconds
Started Feb 07 01:55:30 PM PST 24
Finished Feb 07 01:55:45 PM PST 24
Peak memory 264144 kb
Host smart-ae7f481f-012a-48f7-97f1-a00b2c5ae19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538261697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
1538261697
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1203119476
Short name T905
Test name
Test status
Simulation time 25217100 ps
CPU time 15.77 seconds
Started Feb 07 01:55:29 PM PST 24
Finished Feb 07 01:55:46 PM PST 24
Peak memory 273808 kb
Host smart-2bd19eef-6df1-4276-bd4e-8061c04c4514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203119476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1203119476
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.333626110
Short name T935
Test name
Test status
Simulation time 688312800 ps
CPU time 62.54 seconds
Started Feb 07 01:55:22 PM PST 24
Finished Feb 07 01:56:25 PM PST 24
Peak memory 257836 kb
Host smart-dd2ccc27-f0a6-4f48-9670-57db65ae8035
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333626110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.333626110
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2527759179
Short name T310
Test name
Test status
Simulation time 665487900 ps
CPU time 53.66 seconds
Started Feb 07 01:55:26 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 261900 kb
Host smart-6062c43b-aba2-43f5-a456-6aa66635dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527759179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2527759179
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.4148543219
Short name T371
Test name
Test status
Simulation time 144569700 ps
CPU time 201.07 seconds
Started Feb 07 01:55:28 PM PST 24
Finished Feb 07 01:58:50 PM PST 24
Peak memory 276256 kb
Host smart-478ce84f-29bc-4b3a-bfa0-ba10eb78518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148543219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.4148543219
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3004787302
Short name T792
Test name
Test status
Simulation time 136558900 ps
CPU time 13.97 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:55:49 PM PST 24
Peak memory 264048 kb
Host smart-ecddc52c-6151-43a9-8fd9-77ebd55e8d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004787302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3004787302
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2362228390
Short name T609
Test name
Test status
Simulation time 28103000 ps
CPU time 13.47 seconds
Started Feb 07 01:55:32 PM PST 24
Finished Feb 07 01:55:46 PM PST 24
Peak memory 273696 kb
Host smart-09b18424-de41-42eb-bb62-b6bf2d59a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362228390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2362228390
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.384838334
Short name T102
Test name
Test status
Simulation time 26621100 ps
CPU time 21.58 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:55:56 PM PST 24
Peak memory 272360 kb
Host smart-7c45f421-69fd-4db1-be01-7ecea6e01d99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384838334 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.384838334
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.271358113
Short name T656
Test name
Test status
Simulation time 4596175200 ps
CPU time 124.38 seconds
Started Feb 07 01:55:29 PM PST 24
Finished Feb 07 01:57:35 PM PST 24
Peak memory 258612 kb
Host smart-c92e9383-9836-4ae1-89cf-e9cc72b2fa83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271358113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_h
w_sec_otp.271358113
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2859367554
Short name T481
Test name
Test status
Simulation time 4335580400 ps
CPU time 54.5 seconds
Started Feb 07 01:55:31 PM PST 24
Finished Feb 07 01:56:27 PM PST 24
Peak memory 261776 kb
Host smart-b2909348-3863-41ad-a995-f83602b0368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859367554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2859367554
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.2484262757
Short name T524
Test name
Test status
Simulation time 103897900 ps
CPU time 147.78 seconds
Started Feb 07 01:55:31 PM PST 24
Finished Feb 07 01:58:00 PM PST 24
Peak memory 274652 kb
Host smart-8b27bb24-d71b-4b55-9138-9c736773010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484262757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2484262757
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.1634727329
Short name T567
Test name
Test status
Simulation time 94521000 ps
CPU time 13.54 seconds
Started Feb 07 01:55:33 PM PST 24
Finished Feb 07 01:55:48 PM PST 24
Peak memory 264032 kb
Host smart-b59826ca-a8a2-425f-b830-0aa827c82702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634727329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
1634727329
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2692296296
Short name T437
Test name
Test status
Simulation time 15815400 ps
CPU time 13.39 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:55:48 PM PST 24
Peak memory 273576 kb
Host smart-53d2e3df-e390-4a04-a696-569ebe38d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692296296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2692296296
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.3038183298
Short name T104
Test name
Test status
Simulation time 26774200 ps
CPU time 20.59 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:55:56 PM PST 24
Peak memory 272256 kb
Host smart-2ce16e51-33b2-4a4a-a102-0ef647ef6dc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038183298 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.3038183298
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2774513525
Short name T680
Test name
Test status
Simulation time 13375039100 ps
CPU time 212.35 seconds
Started Feb 07 01:55:31 PM PST 24
Finished Feb 07 01:59:04 PM PST 24
Peak memory 257836 kb
Host smart-88dad936-f9ac-4f87-9405-c59d0198b988
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774513525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2774513525
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1857975552
Short name T477
Test name
Test status
Simulation time 1956794500 ps
CPU time 70.69 seconds
Started Feb 07 01:55:31 PM PST 24
Finished Feb 07 01:56:42 PM PST 24
Peak memory 257900 kb
Host smart-6551121f-a9d3-41f9-a8ee-086c5d37ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857975552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1857975552
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.2117602057
Short name T368
Test name
Test status
Simulation time 91658600 ps
CPU time 173.43 seconds
Started Feb 07 01:55:27 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 275324 kb
Host smart-ea4e9406-a028-4f2e-bb89-257ca057e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117602057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2117602057
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.2641119117
Short name T719
Test name
Test status
Simulation time 197481000 ps
CPU time 14.09 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:55:49 PM PST 24
Peak memory 264032 kb
Host smart-a084846d-1929-48d0-abf8-190d29f28eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641119117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
2641119117
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.346852030
Short name T581
Test name
Test status
Simulation time 50948100 ps
CPU time 15.7 seconds
Started Feb 07 01:55:30 PM PST 24
Finished Feb 07 01:55:47 PM PST 24
Peak memory 283108 kb
Host smart-f2b9828d-1ba9-409c-bf93-cafe37ec144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346852030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.346852030
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.472977562
Short name T531
Test name
Test status
Simulation time 3187211400 ps
CPU time 50.28 seconds
Started Feb 07 01:55:33 PM PST 24
Finished Feb 07 01:56:24 PM PST 24
Peak memory 258544 kb
Host smart-28d66e7a-319c-4edb-b474-02af4b047531
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472977562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.472977562
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.4138365648
Short name T412
Test name
Test status
Simulation time 66345800 ps
CPU time 101.65 seconds
Started Feb 07 01:55:34 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 275056 kb
Host smart-61fe3312-64c1-414c-bfdc-bcc50598b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138365648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.4138365648
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3181480953
Short name T925
Test name
Test status
Simulation time 27237800 ps
CPU time 13.2 seconds
Started Feb 07 01:55:40 PM PST 24
Finished Feb 07 01:55:54 PM PST 24
Peak memory 264160 kb
Host smart-b2777a3d-e29e-40e7-82e0-e258c885b74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181480953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3181480953
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.1492859681
Short name T435
Test name
Test status
Simulation time 25421000 ps
CPU time 15.79 seconds
Started Feb 07 01:55:42 PM PST 24
Finished Feb 07 01:55:58 PM PST 24
Peak memory 273788 kb
Host smart-eedfb5f1-a361-4df3-a378-0e2654709679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492859681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1492859681
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2584982494
Short name T340
Test name
Test status
Simulation time 34346600 ps
CPU time 22.32 seconds
Started Feb 07 01:55:51 PM PST 24
Finished Feb 07 01:56:14 PM PST 24
Peak memory 272396 kb
Host smart-2886b1f0-2149-4243-afc8-f0ed87470b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584982494 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2584982494
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3601943289
Short name T370
Test name
Test status
Simulation time 3266824300 ps
CPU time 99.89 seconds
Started Feb 07 01:55:39 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 258032 kb
Host smart-f26482e4-b726-46b5-8704-730b9484a17f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601943289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.3601943289
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2937724997
Short name T560
Test name
Test status
Simulation time 3483581300 ps
CPU time 71.7 seconds
Started Feb 07 01:55:51 PM PST 24
Finished Feb 07 01:57:04 PM PST 24
Peak memory 263808 kb
Host smart-26db585e-92e0-42fb-b6c7-110626412428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937724997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2937724997
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2458280595
Short name T500
Test name
Test status
Simulation time 78141000 ps
CPU time 99.14 seconds
Started Feb 07 01:55:40 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 273832 kb
Host smart-4bba51a3-76d6-4af3-a0bd-e30b27998ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458280595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2458280595
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.3555355147
Short name T910
Test name
Test status
Simulation time 58402400 ps
CPU time 14.1 seconds
Started Feb 07 01:55:51 PM PST 24
Finished Feb 07 01:56:06 PM PST 24
Peak memory 263984 kb
Host smart-ee423dcf-57d7-4d06-9f30-36c53fcc743f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555355147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
3555355147
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1857881271
Short name T704
Test name
Test status
Simulation time 17741400 ps
CPU time 13.63 seconds
Started Feb 07 01:55:40 PM PST 24
Finished Feb 07 01:55:55 PM PST 24
Peak memory 273756 kb
Host smart-0ba19e2c-3d3d-45e4-b4b1-95708f450782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857881271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1857881271
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.4134703750
Short name T460
Test name
Test status
Simulation time 4722955300 ps
CPU time 74.58 seconds
Started Feb 07 01:55:43 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 258456 kb
Host smart-a1c62116-4b04-45e6-9e72-ccf4daa3f026
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134703750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.4134703750
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.563128375
Short name T514
Test name
Test status
Simulation time 3957004700 ps
CPU time 79.34 seconds
Started Feb 07 01:55:51 PM PST 24
Finished Feb 07 01:57:11 PM PST 24
Peak memory 262700 kb
Host smart-7fddaf38-88de-4bfb-be98-2b0a65cc19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563128375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.563128375
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.569557002
Short name T832
Test name
Test status
Simulation time 59103600 ps
CPU time 144.33 seconds
Started Feb 07 01:55:44 PM PST 24
Finished Feb 07 01:58:10 PM PST 24
Peak memory 274856 kb
Host smart-2d1c5975-ae7e-4eff-a3c8-6a3ec8d5d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569557002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.569557002
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.2841094251
Short name T533
Test name
Test status
Simulation time 108598600 ps
CPU time 13.87 seconds
Started Feb 07 01:55:52 PM PST 24
Finished Feb 07 01:56:07 PM PST 24
Peak memory 264000 kb
Host smart-0b567f67-5a87-423f-9f1c-57871776c766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841094251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
2841094251
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.917743831
Short name T604
Test name
Test status
Simulation time 17080300 ps
CPU time 15.97 seconds
Started Feb 07 01:55:48 PM PST 24
Finished Feb 07 01:56:04 PM PST 24
Peak memory 273868 kb
Host smart-55b112dc-4b62-4276-b294-476d0dc5d1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917743831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.917743831
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1002258683
Short name T147
Test name
Test status
Simulation time 4415059600 ps
CPU time 122.8 seconds
Started Feb 07 01:55:50 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 258512 kb
Host smart-cc0e7d1d-883a-44cf-89ab-1fb993195c31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002258683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.1002258683
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.502361410
Short name T321
Test name
Test status
Simulation time 4937317500 ps
CPU time 73.59 seconds
Started Feb 07 01:55:50 PM PST 24
Finished Feb 07 01:57:04 PM PST 24
Peak memory 260964 kb
Host smart-2787fec1-7807-401d-b4d0-42487975f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502361410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.502361410
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.30555540
Short name T285
Test name
Test status
Simulation time 56633700 ps
CPU time 102.1 seconds
Started Feb 07 01:55:49 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 274820 kb
Host smart-03e6c3e4-adf2-4efc-8966-288946c5201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30555540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.30555540
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.712907321
Short name T528
Test name
Test status
Simulation time 24592400 ps
CPU time 15.89 seconds
Started Feb 07 01:49:18 PM PST 24
Finished Feb 07 01:49:35 PM PST 24
Peak memory 273792 kb
Host smart-302a9e2e-078d-4fb0-af76-c7084ddc965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712907321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.712907321
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3451073474
Short name T229
Test name
Test status
Simulation time 16139677500 ps
CPU time 2424.49 seconds
Started Feb 07 01:49:12 PM PST 24
Finished Feb 07 02:29:37 PM PST 24
Peak memory 263944 kb
Host smart-a6fe72b9-8371-4403-9e3b-1dc1bb521e37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451073474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3451073474
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2834229612
Short name T214
Test name
Test status
Simulation time 3332082300 ps
CPU time 865.47 seconds
Started Feb 07 01:49:07 PM PST 24
Finished Feb 07 02:03:34 PM PST 24
Peak memory 264044 kb
Host smart-c17a6d26-bf5d-4935-ad40-a10eea876b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834229612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2834229612
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1153088397
Short name T35
Test name
Test status
Simulation time 344217400 ps
CPU time 24.22 seconds
Started Feb 07 01:49:04 PM PST 24
Finished Feb 07 01:49:29 PM PST 24
Peak memory 264088 kb
Host smart-44c0c414-2961-4b96-b2c0-1d2f3f4a9f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153088397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1153088397
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4131196819
Short name T870
Test name
Test status
Simulation time 10012311600 ps
CPU time 114.02 seconds
Started Feb 07 01:49:16 PM PST 24
Finished Feb 07 01:51:11 PM PST 24
Peak memory 328384 kb
Host smart-e7db9857-7ca4-4e57-9ad9-9492b986bcfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131196819 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4131196819
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1181249479
Short name T645
Test name
Test status
Simulation time 50243700 ps
CPU time 13.72 seconds
Started Feb 07 01:49:20 PM PST 24
Finished Feb 07 01:49:34 PM PST 24
Peak memory 263924 kb
Host smart-ff5f3614-a1e1-4a0a-a9ef-44a1db78de4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181249479 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1181249479
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3473710834
Short name T74
Test name
Test status
Simulation time 160194991100 ps
CPU time 760.33 seconds
Started Feb 07 01:49:08 PM PST 24
Finished Feb 07 02:01:49 PM PST 24
Peak memory 258296 kb
Host smart-e9f7ff4f-68a9-4845-a287-783509ed5e03
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473710834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3473710834
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1873929621
Short name T586
Test name
Test status
Simulation time 3707348400 ps
CPU time 130.58 seconds
Started Feb 07 01:49:09 PM PST 24
Finished Feb 07 01:51:20 PM PST 24
Peak memory 258440 kb
Host smart-2a4c5b48-d73e-4088-9c7b-a8448c39aaa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873929621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1873929621
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1658440232
Short name T584
Test name
Test status
Simulation time 31983331700 ps
CPU time 218.52 seconds
Started Feb 07 01:49:08 PM PST 24
Finished Feb 07 01:52:47 PM PST 24
Peak memory 282892 kb
Host smart-a8211e45-f552-42d6-bf31-dce9a428284d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658440232 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1658440232
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3450003871
Short name T901
Test name
Test status
Simulation time 8694870800 ps
CPU time 113.69 seconds
Started Feb 07 01:49:03 PM PST 24
Finished Feb 07 01:50:58 PM PST 24
Peak memory 264012 kb
Host smart-7c11431d-a45b-450a-9924-6a5a8b86baa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450003871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3450003871
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1494543805
Short name T740
Test name
Test status
Simulation time 45596266500 ps
CPU time 333.14 seconds
Started Feb 07 01:49:07 PM PST 24
Finished Feb 07 01:54:41 PM PST 24
Peak memory 264040 kb
Host smart-b853ff4f-e1a2-49a2-b90c-c3e9e008ed5d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149
4543805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1494543805
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1083676346
Short name T149
Test name
Test status
Simulation time 10205583600 ps
CPU time 65.79 seconds
Started Feb 07 01:49:02 PM PST 24
Finished Feb 07 01:50:09 PM PST 24
Peak memory 259000 kb
Host smart-12477762-6254-4fe6-a6f5-a822379f2ca5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083676346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1083676346
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1125305587
Short name T414
Test name
Test status
Simulation time 15555200 ps
CPU time 14.35 seconds
Started Feb 07 01:49:18 PM PST 24
Finished Feb 07 01:49:34 PM PST 24
Peak memory 264080 kb
Host smart-73496a9b-d2bf-49a8-9994-252acf672fb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125305587 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1125305587
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3728082726
Short name T142
Test name
Test status
Simulation time 3440214900 ps
CPU time 142.38 seconds
Started Feb 07 01:49:11 PM PST 24
Finished Feb 07 01:51:34 PM PST 24
Peak memory 261148 kb
Host smart-6f9099ef-9f8e-43c4-8515-1e01a8c29164
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728082726 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3728082726
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.3670912339
Short name T843
Test name
Test status
Simulation time 141870400 ps
CPU time 239.82 seconds
Started Feb 07 01:49:07 PM PST 24
Finished Feb 07 01:53:07 PM PST 24
Peak memory 260640 kb
Host smart-e19c3bff-408a-4273-9604-307b9a00ac60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670912339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3670912339
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3950871796
Short name T115
Test name
Test status
Simulation time 51245500 ps
CPU time 13.43 seconds
Started Feb 07 01:49:06 PM PST 24
Finished Feb 07 01:49:20 PM PST 24
Peak memory 263944 kb
Host smart-b641243d-19b3-4ce6-863a-dab9f648d9a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950871796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3950871796
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.3210838513
Short name T153
Test name
Test status
Simulation time 1671461600 ps
CPU time 1395.15 seconds
Started Feb 07 01:48:55 PM PST 24
Finished Feb 07 02:12:11 PM PST 24
Peak memory 283916 kb
Host smart-aa4729b9-3f05-48fe-8c1e-29041bf0c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210838513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3210838513
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2027454022
Short name T459
Test name
Test status
Simulation time 128933400 ps
CPU time 37.14 seconds
Started Feb 07 01:49:20 PM PST 24
Finished Feb 07 01:49:58 PM PST 24
Peak memory 272552 kb
Host smart-dc2d934e-a713-4fdd-9e2e-b910b54648fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027454022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2027454022
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2570558382
Short name T422
Test name
Test status
Simulation time 793059200 ps
CPU time 93.93 seconds
Started Feb 07 01:49:11 PM PST 24
Finished Feb 07 01:50:46 PM PST 24
Peak memory 280368 kb
Host smart-124c834c-743f-453d-81d7-0ea05c1eb4c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570558382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.2570558382
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3616492932
Short name T855
Test name
Test status
Simulation time 973518000 ps
CPU time 114.1 seconds
Started Feb 07 01:49:06 PM PST 24
Finished Feb 07 01:51:01 PM PST 24
Peak memory 288804 kb
Host smart-9dea4c01-cb92-4f43-8d65-ccedf511f9c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616492932 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3616492932
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3902235106
Short name T889
Test name
Test status
Simulation time 8149591400 ps
CPU time 553.23 seconds
Started Feb 07 01:49:09 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 313216 kb
Host smart-d73075c9-3cf8-42e8-855e-78a2758ee82c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902235106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw.3902235106
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.310849444
Short name T566
Test name
Test status
Simulation time 30935300 ps
CPU time 31.12 seconds
Started Feb 07 01:49:03 PM PST 24
Finished Feb 07 01:49:35 PM PST 24
Peak memory 274016 kb
Host smart-9beb261c-c115-4df7-a2d3-29f1cd98cfaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310849444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_rw_evict.310849444
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1297239118
Short name T934
Test name
Test status
Simulation time 108329000 ps
CPU time 30.55 seconds
Started Feb 07 01:49:19 PM PST 24
Finished Feb 07 01:49:50 PM PST 24
Peak memory 272440 kb
Host smart-61a92562-2c83-4bef-8ae3-027b2b74a42a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297239118 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.1297239118
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.4032833208
Short name T317
Test name
Test status
Simulation time 1364082500 ps
CPU time 61.8 seconds
Started Feb 07 01:49:20 PM PST 24
Finished Feb 07 01:50:22 PM PST 24
Peak memory 263780 kb
Host smart-5a0ceeb8-88be-4287-8e62-fe67c93ee374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032833208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.4032833208
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2687497872
Short name T814
Test name
Test status
Simulation time 81504000 ps
CPU time 76.63 seconds
Started Feb 07 01:48:53 PM PST 24
Finished Feb 07 01:50:11 PM PST 24
Peak memory 274520 kb
Host smart-b4fc3ff8-2044-4a7e-90fb-951645514d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687497872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2687497872
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1533201824
Short name T894
Test name
Test status
Simulation time 4782981200 ps
CPU time 205.91 seconds
Started Feb 07 01:49:07 PM PST 24
Finished Feb 07 01:52:33 PM PST 24
Peak memory 264032 kb
Host smart-454daded-a07d-44d0-88e7-4ed3cd382599
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533201824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.1533201824
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1479775248
Short name T698
Test name
Test status
Simulation time 21134700 ps
CPU time 16.02 seconds
Started Feb 07 01:55:49 PM PST 24
Finished Feb 07 01:56:06 PM PST 24
Peak memory 273792 kb
Host smart-c7423e4a-fc5d-4113-8f59-bda750134b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479775248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1479775248
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3421315048
Short name T868
Test name
Test status
Simulation time 15280800 ps
CPU time 15.75 seconds
Started Feb 07 01:55:51 PM PST 24
Finished Feb 07 01:56:07 PM PST 24
Peak memory 273652 kb
Host smart-cb6e636f-c91c-46bd-a0d1-2c8865041b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421315048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3421315048
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.889251028
Short name T534
Test name
Test status
Simulation time 15860100 ps
CPU time 15.97 seconds
Started Feb 07 01:55:59 PM PST 24
Finished Feb 07 01:56:15 PM PST 24
Peak memory 273692 kb
Host smart-f5de96d3-fb77-49f0-9185-4028df238e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889251028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.889251028
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2792999708
Short name T76
Test name
Test status
Simulation time 125703100 ps
CPU time 132.91 seconds
Started Feb 07 01:55:50 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 257992 kb
Host smart-836aa743-babb-40cf-8c8d-421bd2b7f54e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792999708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2792999708
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2406921942
Short name T550
Test name
Test status
Simulation time 21922000 ps
CPU time 15.98 seconds
Started Feb 07 01:56:00 PM PST 24
Finished Feb 07 01:56:16 PM PST 24
Peak memory 273700 kb
Host smart-991d4d4e-1fc0-433b-b4de-41dc94873008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406921942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2406921942
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1647074710
Short name T895
Test name
Test status
Simulation time 43420500 ps
CPU time 15.92 seconds
Started Feb 07 01:55:57 PM PST 24
Finished Feb 07 01:56:13 PM PST 24
Peak memory 273800 kb
Host smart-eddb972d-b4a6-4b2b-90b7-314a9df902b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647074710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1647074710
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.2542886320
Short name T626
Test name
Test status
Simulation time 20298900 ps
CPU time 15.89 seconds
Started Feb 07 01:55:55 PM PST 24
Finished Feb 07 01:56:11 PM PST 24
Peak memory 273744 kb
Host smart-00ba314d-a518-40ed-9064-995a7efe25be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542886320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2542886320
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2237234913
Short name T801
Test name
Test status
Simulation time 50035000 ps
CPU time 13.45 seconds
Started Feb 07 01:55:59 PM PST 24
Finished Feb 07 01:56:13 PM PST 24
Peak memory 273684 kb
Host smart-3b56d993-9035-4af5-93a7-37ace90faa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237234913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2237234913
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2704091018
Short name T502
Test name
Test status
Simulation time 34451300 ps
CPU time 13.29 seconds
Started Feb 07 01:56:00 PM PST 24
Finished Feb 07 01:56:14 PM PST 24
Peak memory 273692 kb
Host smart-c8949d71-040d-4bdd-be02-e9e6eca614af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704091018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2704091018
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.627825649
Short name T81
Test name
Test status
Simulation time 86044200 ps
CPU time 135.19 seconds
Started Feb 07 01:55:59 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 259228 kb
Host smart-22fb6ebb-59a5-4154-8d5a-75a1327df743
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627825649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.627825649
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3822127238
Short name T587
Test name
Test status
Simulation time 59018700 ps
CPU time 13.6 seconds
Started Feb 07 01:56:01 PM PST 24
Finished Feb 07 01:56:15 PM PST 24
Peak memory 273568 kb
Host smart-022d63e5-9a6c-480d-b3da-fc48a99892da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822127238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3822127238
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.442708520
Short name T613
Test name
Test status
Simulation time 135824200 ps
CPU time 112.53 seconds
Started Feb 07 01:55:58 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 258208 kb
Host smart-9a17af54-53e6-47fd-9938-9734826aaaf8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442708520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.442708520
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.761690326
Short name T196
Test name
Test status
Simulation time 73346300 ps
CPU time 14.15 seconds
Started Feb 07 01:49:30 PM PST 24
Finished Feb 07 01:49:45 PM PST 24
Peak memory 264088 kb
Host smart-d2f76fb9-99ac-4532-9c91-10a1022fa5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761690326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.761690326
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.4113842348
Short name T933
Test name
Test status
Simulation time 76570700 ps
CPU time 16.3 seconds
Started Feb 07 01:49:28 PM PST 24
Finished Feb 07 01:49:45 PM PST 24
Peak memory 273824 kb
Host smart-e806413d-f5de-4641-85dc-e2a659b175a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113842348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4113842348
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.4191651291
Short name T99
Test name
Test status
Simulation time 36103600 ps
CPU time 22.02 seconds
Started Feb 07 01:49:32 PM PST 24
Finished Feb 07 01:49:55 PM PST 24
Peak memory 272192 kb
Host smart-b9dddfb4-05eb-407b-8b1b-ea437d67c03a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191651291 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.4191651291
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.1664424840
Short name T728
Test name
Test status
Simulation time 27736035000 ps
CPU time 2573 seconds
Started Feb 07 01:49:21 PM PST 24
Finished Feb 07 02:32:15 PM PST 24
Peak memory 264012 kb
Host smart-302d377a-6845-4469-af2d-4242bdf8b4f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664424840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.1664424840
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.312643563
Short name T601
Test name
Test status
Simulation time 549939800 ps
CPU time 25.83 seconds
Started Feb 07 01:49:22 PM PST 24
Finished Feb 07 01:49:49 PM PST 24
Peak memory 264040 kb
Host smart-45ad4c42-6a8a-4900-830b-81efab6ff8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312643563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.312643563
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.999480047
Short name T706
Test name
Test status
Simulation time 10035828500 ps
CPU time 53.83 seconds
Started Feb 07 01:49:32 PM PST 24
Finished Feb 07 01:50:26 PM PST 24
Peak memory 285860 kb
Host smart-a8d92c8a-f08b-4813-8ba5-21788d1d090e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999480047 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.999480047
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3480921236
Short name T939
Test name
Test status
Simulation time 1555634400 ps
CPU time 112.97 seconds
Started Feb 07 01:49:21 PM PST 24
Finished Feb 07 01:51:14 PM PST 24
Peak memory 259392 kb
Host smart-bb5f27e8-173d-4903-acab-81d98c815639
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480921236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3480921236
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.3145399061
Short name T118
Test name
Test status
Simulation time 1076425200 ps
CPU time 161.97 seconds
Started Feb 07 01:49:29 PM PST 24
Finished Feb 07 01:52:12 PM PST 24
Peak memory 291188 kb
Host smart-fb015798-b272-481c-93a0-f9030e11a335
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145399061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.3145399061
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1352614072
Short name T639
Test name
Test status
Simulation time 15203223500 ps
CPU time 105.45 seconds
Started Feb 07 01:49:32 PM PST 24
Finished Feb 07 01:51:18 PM PST 24
Peak memory 263984 kb
Host smart-5b2379da-0512-4e6b-8412-30b4a875b1f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352614072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1352614072
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.980838064
Short name T808
Test name
Test status
Simulation time 51200426900 ps
CPU time 389.54 seconds
Started Feb 07 01:49:29 PM PST 24
Finished Feb 07 01:55:59 PM PST 24
Peak memory 264044 kb
Host smart-0fed99b3-4d8b-4ac5-9018-951d9166703f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980
838064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.980838064
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2298967906
Short name T664
Test name
Test status
Simulation time 14935703200 ps
CPU time 71.74 seconds
Started Feb 07 01:49:22 PM PST 24
Finished Feb 07 01:50:34 PM PST 24
Peak memory 258884 kb
Host smart-c38a3720-cae0-41ba-913c-3eef29a5047c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298967906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2298967906
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3352480466
Short name T940
Test name
Test status
Simulation time 26365400 ps
CPU time 13.59 seconds
Started Feb 07 01:49:27 PM PST 24
Finished Feb 07 01:49:41 PM PST 24
Peak memory 264080 kb
Host smart-308cbad8-44e8-46e2-b3b0-e285321dfdc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352480466 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3352480466
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.4262630584
Short name T136
Test name
Test status
Simulation time 18272086900 ps
CPU time 235.46 seconds
Started Feb 07 01:49:22 PM PST 24
Finished Feb 07 01:53:18 PM PST 24
Peak memory 270936 kb
Host smart-7acf1819-1209-45f1-8912-2801b932a4dc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262630584 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.4262630584
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2293456817
Short name T758
Test name
Test status
Simulation time 36453700 ps
CPU time 108.51 seconds
Started Feb 07 01:49:16 PM PST 24
Finished Feb 07 01:51:06 PM PST 24
Peak memory 263984 kb
Host smart-ab57d112-064d-4a61-9766-2399bfaee0f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293456817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2293456817
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2933852011
Short name T420
Test name
Test status
Simulation time 49577800 ps
CPU time 13.98 seconds
Started Feb 07 01:49:29 PM PST 24
Finished Feb 07 01:49:43 PM PST 24
Peak memory 264008 kb
Host smart-e078f8ef-c0aa-42cb-8089-213bf2b1027c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933852011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.2933852011
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.1330575647
Short name T570
Test name
Test status
Simulation time 183921300 ps
CPU time 371.09 seconds
Started Feb 07 01:49:17 PM PST 24
Finished Feb 07 01:55:29 PM PST 24
Peak memory 280416 kb
Host smart-b36e8a63-bcf7-4c2a-b853-65b8b0909fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330575647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1330575647
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.1702321598
Short name T856
Test name
Test status
Simulation time 247584300 ps
CPU time 38.97 seconds
Started Feb 07 01:49:28 PM PST 24
Finished Feb 07 01:50:07 PM PST 24
Peak memory 275424 kb
Host smart-5a256047-2965-4d85-8c88-a941884e6449
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702321598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.1702321598
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3591370340
Short name T462
Test name
Test status
Simulation time 898618400 ps
CPU time 91.13 seconds
Started Feb 07 01:49:27 PM PST 24
Finished Feb 07 01:50:59 PM PST 24
Peak memory 280560 kb
Host smart-4a5476b9-2063-4cbf-a608-d054c371e4b1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591370340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.3591370340
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.2485710550
Short name T589
Test name
Test status
Simulation time 3188522300 ps
CPU time 133.82 seconds
Started Feb 07 01:49:27 PM PST 24
Finished Feb 07 01:51:41 PM PST 24
Peak memory 292480 kb
Host smart-ba2dc340-96c6-4ec9-9cb7-f3720de7158a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485710550 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.2485710550
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.189520270
Short name T23
Test name
Test status
Simulation time 9341449500 ps
CPU time 537.6 seconds
Started Feb 07 01:49:23 PM PST 24
Finished Feb 07 01:58:21 PM PST 24
Peak memory 307640 kb
Host smart-20457b92-1137-45ac-9908-5bb5edceb912
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189520270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr
l_rw.189520270
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.1220228259
Short name T439
Test name
Test status
Simulation time 45666600 ps
CPU time 30.57 seconds
Started Feb 07 01:49:27 PM PST 24
Finished Feb 07 01:49:58 PM PST 24
Peak memory 272336 kb
Host smart-8feefb9f-4836-467f-9db2-e36c6f4fc53a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220228259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.1220228259
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.4127261003
Short name T882
Test name
Test status
Simulation time 2841524400 ps
CPU time 488 seconds
Started Feb 07 01:49:30 PM PST 24
Finished Feb 07 01:57:39 PM PST 24
Peak memory 318536 kb
Host smart-49f9ecb2-bdb4-4444-8e3e-dd72512da371
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127261003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.4127261003
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.2556993625
Short name T156
Test name
Test status
Simulation time 2177599000 ps
CPU time 74.55 seconds
Started Feb 07 01:49:29 PM PST 24
Finished Feb 07 01:50:44 PM PST 24
Peak memory 257916 kb
Host smart-9fee2644-8b71-4437-bb06-11cf2d770d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556993625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2556993625
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3060961080
Short name T488
Test name
Test status
Simulation time 255372200 ps
CPU time 80.09 seconds
Started Feb 07 01:49:19 PM PST 24
Finished Feb 07 01:50:40 PM PST 24
Peak memory 273600 kb
Host smart-08cc0dad-dc4e-4754-80a4-2ed3485ded23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060961080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3060961080
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.2325146184
Short name T763
Test name
Test status
Simulation time 1990101300 ps
CPU time 164.16 seconds
Started Feb 07 01:49:20 PM PST 24
Finished Feb 07 01:52:05 PM PST 24
Peak memory 263976 kb
Host smart-4628a259-2ba5-454d-af2c-37e9be51bd00
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325146184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.2325146184
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3205463599
Short name T574
Test name
Test status
Simulation time 15436100 ps
CPU time 15.94 seconds
Started Feb 07 01:56:11 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 273636 kb
Host smart-3f0529ac-a507-4371-bd2f-323c390fc1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205463599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3205463599
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2716858956
Short name T834
Test name
Test status
Simulation time 14455300 ps
CPU time 16.43 seconds
Started Feb 07 01:56:04 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 283160 kb
Host smart-758c34a4-fd34-4a50-abe4-ed9b72cfb974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716858956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2716858956
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3274360986
Short name T86
Test name
Test status
Simulation time 41037900 ps
CPU time 133.24 seconds
Started Feb 07 01:56:08 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 258388 kb
Host smart-f86e23be-57a6-40eb-8f5d-0d3c98c87e10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274360986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3274360986
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2426114315
Short name T600
Test name
Test status
Simulation time 15688200 ps
CPU time 15.75 seconds
Started Feb 07 01:56:11 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 273784 kb
Host smart-8daad7cc-eac4-476f-a3cd-8b78bcaac0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426114315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2426114315
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.2334512063
Short name T232
Test name
Test status
Simulation time 112621700 ps
CPU time 15.78 seconds
Started Feb 07 01:56:04 PM PST 24
Finished Feb 07 01:56:21 PM PST 24
Peak memory 273768 kb
Host smart-a637a4f5-b87a-491e-bc8f-742a014e7a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334512063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2334512063
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1933511095
Short name T769
Test name
Test status
Simulation time 193528300 ps
CPU time 134.39 seconds
Started Feb 07 01:56:02 PM PST 24
Finished Feb 07 01:58:18 PM PST 24
Peak memory 258148 kb
Host smart-01831d12-e8b9-417b-9a3c-48c641e8d71b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933511095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1933511095
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.3280758461
Short name T383
Test name
Test status
Simulation time 26066800 ps
CPU time 15.94 seconds
Started Feb 07 01:56:18 PM PST 24
Finished Feb 07 01:56:35 PM PST 24
Peak memory 273740 kb
Host smart-f3f34ce1-3723-417d-b1b6-f15ac469cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280758461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3280758461
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1956872190
Short name T648
Test name
Test status
Simulation time 657234300 ps
CPU time 133.72 seconds
Started Feb 07 01:56:09 PM PST 24
Finished Feb 07 01:58:24 PM PST 24
Peak memory 257928 kb
Host smart-71b77b5b-f3bd-4376-92f9-7b81f601be51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956872190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1956872190
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.1552270632
Short name T751
Test name
Test status
Simulation time 24136700 ps
CPU time 16.25 seconds
Started Feb 07 01:56:10 PM PST 24
Finished Feb 07 01:56:27 PM PST 24
Peak memory 273688 kb
Host smart-cc2b3a27-6286-4ab5-a3ff-19b1021c2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552270632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1552270632
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1620265363
Short name T12
Test name
Test status
Simulation time 51708700 ps
CPU time 110.98 seconds
Started Feb 07 01:56:08 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 258412 kb
Host smart-b9a07802-a083-4aac-b467-388e716e38b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620265363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1620265363
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.660449857
Short name T509
Test name
Test status
Simulation time 24121600 ps
CPU time 15.83 seconds
Started Feb 07 01:56:11 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 273612 kb
Host smart-373d31c7-eacd-4c82-a441-fda2aba0b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660449857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.660449857
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.3132728114
Short name T828
Test name
Test status
Simulation time 58301100 ps
CPU time 13.35 seconds
Started Feb 07 01:56:05 PM PST 24
Finished Feb 07 01:56:20 PM PST 24
Peak memory 273640 kb
Host smart-1020bb90-372c-4abc-9211-8aad8b1cd958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132728114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3132728114
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.3568717815
Short name T409
Test name
Test status
Simulation time 50396100 ps
CPU time 13.67 seconds
Started Feb 07 01:56:15 PM PST 24
Finished Feb 07 01:56:29 PM PST 24
Peak memory 273564 kb
Host smart-00470243-f9b2-4747-8d7c-f92e02f7e49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568717815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3568717815
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.1584238054
Short name T768
Test name
Test status
Simulation time 28792200 ps
CPU time 15.88 seconds
Started Feb 07 01:56:11 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 273792 kb
Host smart-1f85bf20-f54f-47da-a481-a7bcb2e57c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584238054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1584238054
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.3577390749
Short name T813
Test name
Test status
Simulation time 217721500 ps
CPU time 131.39 seconds
Started Feb 07 01:56:14 PM PST 24
Finished Feb 07 01:58:26 PM PST 24
Peak memory 258144 kb
Host smart-886a5ac6-220f-4bca-ab03-83e60e1c33c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577390749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.3577390749
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.523392464
Short name T401
Test name
Test status
Simulation time 49773200 ps
CPU time 13.83 seconds
Started Feb 07 01:49:50 PM PST 24
Finished Feb 07 01:50:05 PM PST 24
Peak memory 264056 kb
Host smart-286f796e-b83c-46c0-b426-7eada9ddd66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523392464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.523392464
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.207285502
Short name T516
Test name
Test status
Simulation time 15884700 ps
CPU time 16 seconds
Started Feb 07 01:49:49 PM PST 24
Finished Feb 07 01:50:07 PM PST 24
Peak memory 283088 kb
Host smart-4b212029-956a-4e8d-a313-5da04facbc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207285502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.207285502
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3310028581
Short name T568
Test name
Test status
Simulation time 3128098300 ps
CPU time 2286.05 seconds
Started Feb 07 01:49:35 PM PST 24
Finished Feb 07 02:27:42 PM PST 24
Peak memory 263960 kb
Host smart-ecf7ecd7-f486-41b4-ba0b-d46ffde592f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310028581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3310028581
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.2634187986
Short name T164
Test name
Test status
Simulation time 865169600 ps
CPU time 907.74 seconds
Started Feb 07 01:49:35 PM PST 24
Finished Feb 07 02:04:43 PM PST 24
Peak memory 264032 kb
Host smart-d4743c54-842c-4a06-98ae-cea9e9fea21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634187986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2634187986
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.3474599603
Short name T911
Test name
Test status
Simulation time 109422500 ps
CPU time 22.76 seconds
Started Feb 07 01:49:36 PM PST 24
Finished Feb 07 01:49:59 PM PST 24
Peak memory 264048 kb
Host smart-254a9615-7fe2-4243-9180-8da3d374c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474599603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3474599603
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2279987768
Short name T647
Test name
Test status
Simulation time 10020030800 ps
CPU time 88.65 seconds
Started Feb 07 01:49:50 PM PST 24
Finished Feb 07 01:51:20 PM PST 24
Peak memory 320640 kb
Host smart-68265f19-67b5-4f2a-b59b-b85d0fcc3ad0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279987768 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2279987768
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.4123014994
Short name T851
Test name
Test status
Simulation time 40124999700 ps
CPU time 780.25 seconds
Started Feb 07 01:49:33 PM PST 24
Finished Feb 07 02:02:34 PM PST 24
Peak memory 258380 kb
Host smart-c7d09f84-40e8-416c-a581-745127e6a168
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123014994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.4123014994
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1117609470
Short name T902
Test name
Test status
Simulation time 3427315400 ps
CPU time 125.96 seconds
Started Feb 07 01:49:33 PM PST 24
Finished Feb 07 01:51:40 PM PST 24
Peak memory 258544 kb
Host smart-f7c6a8c4-6ad3-4a11-a60b-9eade20d9f1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117609470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1117609470
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.3554145830
Short name T578
Test name
Test status
Simulation time 1224450100 ps
CPU time 162.99 seconds
Started Feb 07 01:49:47 PM PST 24
Finished Feb 07 01:52:31 PM PST 24
Peak memory 292096 kb
Host smart-eccd508d-4c8c-40c2-bc03-64a217001ef8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554145830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.3554145830
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.27044814
Short name T575
Test name
Test status
Simulation time 11039950300 ps
CPU time 203.97 seconds
Started Feb 07 01:49:48 PM PST 24
Finished Feb 07 01:53:14 PM PST 24
Peak memory 290520 kb
Host smart-9107ddae-326c-4e31-82e3-ed9d599bb165
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27044814 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.27044814
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.1927389449
Short name T117
Test name
Test status
Simulation time 2994304100 ps
CPU time 87.22 seconds
Started Feb 07 01:49:52 PM PST 24
Finished Feb 07 01:51:20 PM PST 24
Peak memory 264108 kb
Host smart-5130d30d-8bb1-4549-9e7d-5d4bce41914c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927389449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.1927389449
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.4100491889
Short name T6
Test name
Test status
Simulation time 167451939500 ps
CPU time 324.49 seconds
Started Feb 07 01:49:51 PM PST 24
Finished Feb 07 01:55:17 PM PST 24
Peak memory 264016 kb
Host smart-639c672e-cad4-430d-b6ae-1ce5d4c63184
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410
0491889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.4100491889
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.244416081
Short name T687
Test name
Test status
Simulation time 26064000 ps
CPU time 66.31 seconds
Started Feb 07 01:49:30 PM PST 24
Finished Feb 07 01:50:37 PM PST 24
Peak memory 263848 kb
Host smart-44d0454a-9710-45bd-b7f4-de8c578c20ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244416081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.244416081
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.700452008
Short name T866
Test name
Test status
Simulation time 36929900 ps
CPU time 13.86 seconds
Started Feb 07 01:49:49 PM PST 24
Finished Feb 07 01:50:05 PM PST 24
Peak memory 264032 kb
Host smart-7d50e439-0541-49ef-8024-d699af41805f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700452008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_rese
t.700452008
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.1820097961
Short name T844
Test name
Test status
Simulation time 400055700 ps
CPU time 1144.03 seconds
Started Feb 07 01:49:27 PM PST 24
Finished Feb 07 02:08:32 PM PST 24
Peak memory 284836 kb
Host smart-3f45637b-7299-4b29-ab2a-05362014eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820097961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1820097961
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2581579122
Short name T494
Test name
Test status
Simulation time 253215800 ps
CPU time 32.09 seconds
Started Feb 07 01:49:54 PM PST 24
Finished Feb 07 01:50:27 PM PST 24
Peak memory 272356 kb
Host smart-97df4183-6595-477d-9d42-d68ee70aa864
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581579122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2581579122
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3119335027
Short name T511
Test name
Test status
Simulation time 514857200 ps
CPU time 105.82 seconds
Started Feb 07 01:49:38 PM PST 24
Finished Feb 07 01:51:25 PM PST 24
Peak memory 280476 kb
Host smart-30a59ca4-5317-47f0-be71-64a707c024aa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119335027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.3119335027
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.3660274740
Short name T737
Test name
Test status
Simulation time 1921220200 ps
CPU time 125.64 seconds
Started Feb 07 01:49:33 PM PST 24
Finished Feb 07 01:51:40 PM PST 24
Peak memory 288732 kb
Host smart-5bcd32ed-7648-4fb9-94c6-c12eb61f17f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660274740 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3660274740
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.3027803882
Short name T810
Test name
Test status
Simulation time 31474421500 ps
CPU time 585.04 seconds
Started Feb 07 01:49:35 PM PST 24
Finished Feb 07 01:59:21 PM PST 24
Peak memory 313264 kb
Host smart-c74ef72c-e2be-4f7f-a864-00d6b47eb8a3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027803882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.3027803882
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2296884236
Short name T616
Test name
Test status
Simulation time 30563000 ps
CPU time 29.68 seconds
Started Feb 07 01:49:50 PM PST 24
Finished Feb 07 01:50:21 PM PST 24
Peak memory 272380 kb
Host smart-5c716258-24fe-4ff1-825a-65775a56bade
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296884236 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2296884236
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.3058320749
Short name T526
Test name
Test status
Simulation time 4026437700 ps
CPU time 688.19 seconds
Started Feb 07 01:49:53 PM PST 24
Finished Feb 07 02:01:22 PM PST 24
Peak memory 310908 kb
Host smart-50669e38-c4dc-4077-b517-e7b45815f28f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058320749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.3058320749
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1251784277
Short name T304
Test name
Test status
Simulation time 1298724800 ps
CPU time 51.24 seconds
Started Feb 07 01:49:48 PM PST 24
Finished Feb 07 01:50:41 PM PST 24
Peak memory 261660 kb
Host smart-0daba048-d333-43b7-abce-0962187afe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251784277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1251784277
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.4109710129
Short name T665
Test name
Test status
Simulation time 38608100 ps
CPU time 124.88 seconds
Started Feb 07 01:49:28 PM PST 24
Finished Feb 07 01:51:34 PM PST 24
Peak memory 275100 kb
Host smart-dad181ea-5a63-45be-bd15-4de298e04124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109710129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.4109710129
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.1483871315
Short name T369
Test name
Test status
Simulation time 1345019900 ps
CPU time 123.62 seconds
Started Feb 07 01:49:34 PM PST 24
Finished Feb 07 01:51:38 PM PST 24
Peak memory 263980 kb
Host smart-f64f84ce-8a08-40f1-9a1a-6ec29171568e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483871315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.1483871315
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.4257581279
Short name T576
Test name
Test status
Simulation time 15620600 ps
CPU time 15.91 seconds
Started Feb 07 01:56:21 PM PST 24
Finished Feb 07 01:56:37 PM PST 24
Peak memory 273652 kb
Host smart-7a7802ce-fcb3-4541-99ec-82856e0329a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257581279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4257581279
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2738572211
Short name T463
Test name
Test status
Simulation time 14713500 ps
CPU time 13.79 seconds
Started Feb 07 01:56:15 PM PST 24
Finished Feb 07 01:56:30 PM PST 24
Peak memory 273676 kb
Host smart-5e88dfa4-10d3-4457-bb7a-f37ef24b0cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738572211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2738572211
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.3818086494
Short name T716
Test name
Test status
Simulation time 51276500 ps
CPU time 16.25 seconds
Started Feb 07 01:56:11 PM PST 24
Finished Feb 07 01:56:28 PM PST 24
Peak memory 273768 kb
Host smart-014fb0d8-f0ad-45c0-bb04-a17a77df62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818086494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3818086494
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.2019030218
Short name T861
Test name
Test status
Simulation time 249076900 ps
CPU time 131.34 seconds
Started Feb 07 01:56:13 PM PST 24
Finished Feb 07 01:58:25 PM PST 24
Peak memory 258188 kb
Host smart-062cb269-a609-461a-bc82-3668088db4b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019030218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.2019030218
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2375418468
Short name T812
Test name
Test status
Simulation time 86463500 ps
CPU time 13.17 seconds
Started Feb 07 01:56:17 PM PST 24
Finished Feb 07 01:56:31 PM PST 24
Peak memory 273532 kb
Host smart-af622209-28f8-439e-870a-0458e0e400f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375418468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2375418468
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.3420366527
Short name T667
Test name
Test status
Simulation time 41821500 ps
CPU time 15.95 seconds
Started Feb 07 01:56:16 PM PST 24
Finished Feb 07 01:56:32 PM PST 24
Peak memory 273740 kb
Host smart-80232f5c-ff30-4091-8fce-cfc5f39a6670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420366527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3420366527
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.584427189
Short name T339
Test name
Test status
Simulation time 43064900 ps
CPU time 15.7 seconds
Started Feb 07 01:56:17 PM PST 24
Finished Feb 07 01:56:34 PM PST 24
Peak memory 283032 kb
Host smart-6826a6e7-8818-438f-9af3-ad514228dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584427189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.584427189
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.2877485475
Short name T847
Test name
Test status
Simulation time 318798500 ps
CPU time 130.89 seconds
Started Feb 07 01:56:19 PM PST 24
Finished Feb 07 01:58:30 PM PST 24
Peak memory 257856 kb
Host smart-276a41e2-325f-4fcc-ad31-2019dbfb34ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877485475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.2877485475
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3435097063
Short name T733
Test name
Test status
Simulation time 13293100 ps
CPU time 13.61 seconds
Started Feb 07 01:56:20 PM PST 24
Finished Feb 07 01:56:35 PM PST 24
Peak memory 273700 kb
Host smart-97647401-88dd-4fb2-a02f-5f8da1eef1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435097063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3435097063
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1810933449
Short name T75
Test name
Test status
Simulation time 75141600 ps
CPU time 112.19 seconds
Started Feb 07 01:56:17 PM PST 24
Finished Feb 07 01:58:10 PM PST 24
Peak memory 258108 kb
Host smart-0ac8287f-2584-446d-94aa-78e0f302ca68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810933449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1810933449
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.4283892773
Short name T418
Test name
Test status
Simulation time 16960300 ps
CPU time 13.52 seconds
Started Feb 07 01:56:24 PM PST 24
Finished Feb 07 01:56:38 PM PST 24
Peak memory 273784 kb
Host smart-9ae987cc-2ad7-409e-8541-db9a84865680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283892773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.4283892773
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.627319027
Short name T489
Test name
Test status
Simulation time 15188700 ps
CPU time 15.87 seconds
Started Feb 07 01:56:25 PM PST 24
Finished Feb 07 01:56:42 PM PST 24
Peak memory 273764 kb
Host smart-5cb08bde-62cc-4e74-874b-18b3d7f837cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627319027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.627319027
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3759521646
Short name T374
Test name
Test status
Simulation time 98015400 ps
CPU time 13.99 seconds
Started Feb 07 01:50:19 PM PST 24
Finished Feb 07 01:50:35 PM PST 24
Peak memory 264132 kb
Host smart-d74ea558-bb14-42ce-b3ec-f7625e8b58ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759521646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
759521646
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1283923781
Short name T741
Test name
Test status
Simulation time 74312100 ps
CPU time 16.08 seconds
Started Feb 07 01:50:18 PM PST 24
Finished Feb 07 01:50:37 PM PST 24
Peak memory 273700 kb
Host smart-bdea9d70-8ef3-450b-80dd-7cd766e9cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283923781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1283923781
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.4230525441
Short name T144
Test name
Test status
Simulation time 4025220500 ps
CPU time 2187.52 seconds
Started Feb 07 01:50:03 PM PST 24
Finished Feb 07 02:26:33 PM PST 24
Peak memory 262768 kb
Host smart-4f92fd5b-c1a3-4468-9725-d5ac2cf506ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230525441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.4230525441
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2884104910
Short name T927
Test name
Test status
Simulation time 1575729900 ps
CPU time 804.84 seconds
Started Feb 07 01:50:05 PM PST 24
Finished Feb 07 02:03:31 PM PST 24
Peak memory 264024 kb
Host smart-9667e6cc-1e20-480f-9c87-5c78865c8094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884104910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2884104910
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2316722962
Short name T37
Test name
Test status
Simulation time 1178276800 ps
CPU time 23.48 seconds
Started Feb 07 01:49:52 PM PST 24
Finished Feb 07 01:50:16 PM PST 24
Peak memory 264128 kb
Host smart-d3693315-e1a2-4e2d-85c1-42ca87ec6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316722962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2316722962
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3618871186
Short name T605
Test name
Test status
Simulation time 10032972800 ps
CPU time 53.91 seconds
Started Feb 07 01:50:16 PM PST 24
Finished Feb 07 01:51:11 PM PST 24
Peak memory 275836 kb
Host smart-a49504aa-5513-42c2-986a-4a9f0aed46bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618871186 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3618871186
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2356987406
Short name T824
Test name
Test status
Simulation time 26562900 ps
CPU time 13.54 seconds
Started Feb 07 01:50:21 PM PST 24
Finished Feb 07 01:50:36 PM PST 24
Peak memory 264088 kb
Host smart-714f54e7-76a2-4527-b37b-6a9fa35a2340
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356987406 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2356987406
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1533013103
Short name T668
Test name
Test status
Simulation time 160178050500 ps
CPU time 896.94 seconds
Started Feb 07 01:50:03 PM PST 24
Finished Feb 07 02:05:02 PM PST 24
Peak memory 258216 kb
Host smart-f39c7c97-b7c1-42be-a9fb-8d9691dcb0ee
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533013103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.1533013103
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2824287906
Short name T689
Test name
Test status
Simulation time 6152187500 ps
CPU time 52.59 seconds
Started Feb 07 01:50:04 PM PST 24
Finished Feb 07 01:50:58 PM PST 24
Peak memory 258488 kb
Host smart-ead98801-09b1-4f5c-abda-c665c2c537d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824287906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2824287906
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.258353787
Short name T749
Test name
Test status
Simulation time 3823977000 ps
CPU time 149.94 seconds
Started Feb 07 01:49:55 PM PST 24
Finished Feb 07 01:52:25 PM PST 24
Peak memory 291200 kb
Host smart-cb44d1db-267f-4d40-87d4-216a4fdbbb40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258353787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.258353787
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2530791588
Short name T213
Test name
Test status
Simulation time 33673305900 ps
CPU time 237.08 seconds
Started Feb 07 01:50:03 PM PST 24
Finished Feb 07 01:54:02 PM PST 24
Peak memory 283060 kb
Host smart-d4ebe18d-b9c8-44a3-ae58-068aabad917f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530791588 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2530791588
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1927294489
Short name T424
Test name
Test status
Simulation time 58475205000 ps
CPU time 126.9 seconds
Started Feb 07 01:50:15 PM PST 24
Finished Feb 07 01:52:22 PM PST 24
Peak memory 264104 kb
Host smart-db319661-a1c7-48c4-b280-ddcfc0c2cf29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927294489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1927294489
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.448895437
Short name T747
Test name
Test status
Simulation time 6378599800 ps
CPU time 59.32 seconds
Started Feb 07 01:50:00 PM PST 24
Finished Feb 07 01:51:00 PM PST 24
Peak memory 258992 kb
Host smart-68e111e8-8886-404b-ac43-0964060967b0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448895437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.448895437
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2308906158
Short name T629
Test name
Test status
Simulation time 44661400 ps
CPU time 13.25 seconds
Started Feb 07 01:50:15 PM PST 24
Finished Feb 07 01:50:29 PM PST 24
Peak memory 264116 kb
Host smart-c90b141e-e21a-4061-96b4-c8dab5fb18ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308906158 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2308906158
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.1129587051
Short name T132
Test name
Test status
Simulation time 7871317700 ps
CPU time 269.85 seconds
Started Feb 07 01:50:11 PM PST 24
Finished Feb 07 01:54:42 PM PST 24
Peak memory 273220 kb
Host smart-04a4fe6f-0aaa-4f8a-b15b-fe27edaf1e38
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129587051 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.1129587051
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3298683638
Short name T444
Test name
Test status
Simulation time 733561700 ps
CPU time 284.55 seconds
Started Feb 07 01:50:05 PM PST 24
Finished Feb 07 01:54:51 PM PST 24
Peak memory 264104 kb
Host smart-4e87d086-53db-4a83-a576-dd6a96c5e95f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298683638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3298683638
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3421761348
Short name T556
Test name
Test status
Simulation time 20351800 ps
CPU time 13.88 seconds
Started Feb 07 01:50:10 PM PST 24
Finished Feb 07 01:50:25 PM PST 24
Peak memory 264048 kb
Host smart-55ebc873-bcc8-47cf-8a0e-5516abd176c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421761348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.3421761348
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2877883680
Short name T141
Test name
Test status
Simulation time 5589803000 ps
CPU time 1397.18 seconds
Started Feb 07 01:50:04 PM PST 24
Finished Feb 07 02:13:23 PM PST 24
Peak memory 286308 kb
Host smart-cd0135d0-c355-4d97-9238-f55616dbc029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877883680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2877883680
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1684831476
Short name T547
Test name
Test status
Simulation time 259668300 ps
CPU time 40.54 seconds
Started Feb 07 01:50:15 PM PST 24
Finished Feb 07 01:50:56 PM PST 24
Peak memory 272388 kb
Host smart-a7fc9a3e-acf5-4913-ba1c-18eaaa6b213c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684831476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1684831476
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.28115308
Short name T660
Test name
Test status
Simulation time 1621369400 ps
CPU time 92.89 seconds
Started Feb 07 01:50:11 PM PST 24
Finished Feb 07 01:51:45 PM PST 24
Peak memory 280492 kb
Host smart-1cf4a62b-7fa6-41c2-9d66-ea76794953c7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_ro.28115308
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1305297764
Short name T125
Test name
Test status
Simulation time 3913723900 ps
CPU time 586.58 seconds
Started Feb 07 01:49:56 PM PST 24
Finished Feb 07 01:59:43 PM PST 24
Peak memory 313264 kb
Host smart-708f0c2b-4a9c-40eb-9267-041f3db6759b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305297764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.1305297764
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.2110179457
Short name T693
Test name
Test status
Simulation time 30490200 ps
CPU time 31.39 seconds
Started Feb 07 01:50:14 PM PST 24
Finished Feb 07 01:50:46 PM PST 24
Peak memory 272400 kb
Host smart-a15d61a2-fe36-4346-8e16-7da6ff4363c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110179457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.2110179457
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3642194804
Short name T907
Test name
Test status
Simulation time 41834900 ps
CPU time 29.05 seconds
Started Feb 07 01:50:04 PM PST 24
Finished Feb 07 01:50:34 PM PST 24
Peak memory 272384 kb
Host smart-de1b4bfc-623f-4cfc-a580-95a92c662be9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642194804 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3642194804
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.1231788680
Short name T923
Test name
Test status
Simulation time 7886940700 ps
CPU time 613.11 seconds
Started Feb 07 01:49:55 PM PST 24
Finished Feb 07 02:00:09 PM PST 24
Peak memory 313396 kb
Host smart-ddba99fa-16cb-4c0b-8253-74aa8e2e6a2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231788680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.1231788680
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.2264210475
Short name T306
Test name
Test status
Simulation time 4807975900 ps
CPU time 71.85 seconds
Started Feb 07 01:50:16 PM PST 24
Finished Feb 07 01:51:28 PM PST 24
Peak memory 261808 kb
Host smart-5d8849a9-3f97-4d7a-9aa1-2d442bf4da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264210475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2264210475
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3713594406
Short name T670
Test name
Test status
Simulation time 22145700 ps
CPU time 125.51 seconds
Started Feb 07 01:49:59 PM PST 24
Finished Feb 07 01:52:06 PM PST 24
Peak memory 275408 kb
Host smart-cc2115fc-558f-4288-9d9f-7be5560c7dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713594406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3713594406
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1440996738
Short name T863
Test name
Test status
Simulation time 1879812100 ps
CPU time 155.28 seconds
Started Feb 07 01:49:52 PM PST 24
Finished Feb 07 01:52:28 PM PST 24
Peak memory 264116 kb
Host smart-a3bf5e62-a646-4514-b986-74e276d0bfbd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440996738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.1440996738
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.4248962668
Short name T497
Test name
Test status
Simulation time 32443700 ps
CPU time 13.53 seconds
Started Feb 07 01:50:33 PM PST 24
Finished Feb 07 01:50:47 PM PST 24
Peak memory 264056 kb
Host smart-2551dcbd-f796-420d-ab23-fbfe771e0a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248962668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.4
248962668
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1596492773
Short name T637
Test name
Test status
Simulation time 44997600 ps
CPU time 15.85 seconds
Started Feb 07 01:50:35 PM PST 24
Finished Feb 07 01:50:52 PM PST 24
Peak memory 273828 kb
Host smart-5fe8c888-c920-46f9-8920-0f600110a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596492773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1596492773
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.227190218
Short name T522
Test name
Test status
Simulation time 14681718500 ps
CPU time 2401.07 seconds
Started Feb 07 01:50:17 PM PST 24
Finished Feb 07 02:30:21 PM PST 24
Peak memory 263972 kb
Host smart-e2dd7ac7-cf11-4f78-8583-f1368901b881
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227190218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_erro
r_mp.227190218
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.1572914401
Short name T750
Test name
Test status
Simulation time 11956627000 ps
CPU time 1026.53 seconds
Started Feb 07 01:50:25 PM PST 24
Finished Feb 07 02:07:32 PM PST 24
Peak memory 272268 kb
Host smart-1c797963-e59b-4871-975c-5e52107a82fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572914401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1572914401
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1263908630
Short name T276
Test name
Test status
Simulation time 10032935800 ps
CPU time 62.62 seconds
Started Feb 07 01:50:37 PM PST 24
Finished Feb 07 01:51:41 PM PST 24
Peak memory 270032 kb
Host smart-7c3f40f4-943c-4ee7-b321-25d2f698d9fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263908630 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1263908630
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3770821848
Short name T64
Test name
Test status
Simulation time 18843300 ps
CPU time 13.49 seconds
Started Feb 07 01:50:37 PM PST 24
Finished Feb 07 01:50:52 PM PST 24
Peak memory 264052 kb
Host smart-e9442416-7ef7-4bce-9c5d-f52bb5ecb12f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770821848 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3770821848
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1086762952
Short name T796
Test name
Test status
Simulation time 22751960300 ps
CPU time 144.9 seconds
Started Feb 07 01:50:25 PM PST 24
Finished Feb 07 01:52:51 PM PST 24
Peak memory 258608 kb
Host smart-4c8459d0-a871-4c72-8289-5472b02c5d71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086762952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1086762952
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3909015777
Short name T161
Test name
Test status
Simulation time 4768630200 ps
CPU time 179.57 seconds
Started Feb 07 01:50:27 PM PST 24
Finished Feb 07 01:53:28 PM PST 24
Peak memory 292132 kb
Host smart-1933649c-0e3e-4edb-ab36-d1716b629bb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909015777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3909015777
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1728727811
Short name T773
Test name
Test status
Simulation time 16127555300 ps
CPU time 179.62 seconds
Started Feb 07 01:50:24 PM PST 24
Finished Feb 07 01:53:25 PM PST 24
Peak memory 282684 kb
Host smart-79a0b3d0-b959-415e-97fc-96236d334852
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728727811 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1728727811
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.1723503133
Short name T116
Test name
Test status
Simulation time 23410701900 ps
CPU time 114.16 seconds
Started Feb 07 01:50:25 PM PST 24
Finished Feb 07 01:52:20 PM PST 24
Peak memory 264072 kb
Host smart-93d8c7ec-daa2-4aa4-9183-e6b9e2e163f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723503133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.1723503133
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3007755428
Short name T2
Test name
Test status
Simulation time 175936319700 ps
CPU time 443.96 seconds
Started Feb 07 01:50:22 PM PST 24
Finished Feb 07 01:57:47 PM PST 24
Peak memory 264052 kb
Host smart-9c7be94d-0f5d-49a1-9690-2947b5feeb90
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300
7755428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3007755428
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2830683662
Short name T193
Test name
Test status
Simulation time 8641323500 ps
CPU time 72.3 seconds
Started Feb 07 01:50:26 PM PST 24
Finished Feb 07 01:51:39 PM PST 24
Peak memory 258092 kb
Host smart-ead693ab-0b4b-4d4b-b59b-531bb64faf3d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830683662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2830683662
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.745319354
Short name T729
Test name
Test status
Simulation time 101019100 ps
CPU time 14.01 seconds
Started Feb 07 01:50:35 PM PST 24
Finished Feb 07 01:50:49 PM PST 24
Peak memory 264116 kb
Host smart-8434fe1e-ba32-4179-a37c-e239bb619917
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745319354 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.745319354
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3377382262
Short name T58
Test name
Test status
Simulation time 6887134200 ps
CPU time 544.35 seconds
Started Feb 07 01:50:21 PM PST 24
Finished Feb 07 01:59:26 PM PST 24
Peak memory 271960 kb
Host smart-735e4f7e-ad25-4dcf-8010-ea9717e2964d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377382262 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3377382262
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2084749148
Short name T396
Test name
Test status
Simulation time 220071700 ps
CPU time 69.34 seconds
Started Feb 07 01:50:20 PM PST 24
Finished Feb 07 01:51:31 PM PST 24
Peak memory 263692 kb
Host smart-4bccc76a-9e0d-4754-9202-c5b41d66f1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084749148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2084749148
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.64513123
Short name T799
Test name
Test status
Simulation time 21452400 ps
CPU time 13.58 seconds
Started Feb 07 01:50:30 PM PST 24
Finished Feb 07 01:50:45 PM PST 24
Peak memory 264100 kb
Host smart-88a8df73-fd0c-41b3-8d72-d7bbb76d3827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64513123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset
.64513123
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.925779010
Short name T518
Test name
Test status
Simulation time 758141500 ps
CPU time 465.88 seconds
Started Feb 07 01:50:24 PM PST 24
Finished Feb 07 01:58:11 PM PST 24
Peak memory 281284 kb
Host smart-1ca2079c-ae0f-4e98-9c02-336df4a836d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925779010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.925779010
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.1161735515
Short name T559
Test name
Test status
Simulation time 67984800 ps
CPU time 31.61 seconds
Started Feb 07 01:50:22 PM PST 24
Finished Feb 07 01:50:55 PM PST 24
Peak memory 272428 kb
Host smart-2f357bb1-8d06-4de1-83e9-4cb1aaed0b4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161735515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.1161735515
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.1282736459
Short name T594
Test name
Test status
Simulation time 6499418800 ps
CPU time 107.52 seconds
Started Feb 07 01:50:17 PM PST 24
Finished Feb 07 01:52:06 PM PST 24
Peak memory 280532 kb
Host smart-68882a30-1091-4164-9c41-e1c0eb89785c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282736459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.1282736459
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1605494434
Short name T931
Test name
Test status
Simulation time 1081523500 ps
CPU time 120.1 seconds
Started Feb 07 01:50:22 PM PST 24
Finished Feb 07 01:52:23 PM PST 24
Peak memory 280604 kb
Host smart-4b81d5e0-93cc-49b5-988e-3a52e2ebbd21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605494434 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1605494434
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.2787398516
Short name T893
Test name
Test status
Simulation time 7866757600 ps
CPU time 586.14 seconds
Started Feb 07 01:50:20 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 313140 kb
Host smart-a0ec827c-790e-4bc4-9667-5fb6b73fd98f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787398516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.2787398516
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.540714269
Short name T724
Test name
Test status
Simulation time 3721448200 ps
CPU time 491.09 seconds
Started Feb 07 01:50:24 PM PST 24
Finished Feb 07 01:58:37 PM PST 24
Peak memory 317524 kb
Host smart-1c0bd668-4ace-484b-b956-d4347762fce5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540714269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se
rr.540714269
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1591132856
Short name T776
Test name
Test status
Simulation time 2397891800 ps
CPU time 81.47 seconds
Started Feb 07 01:50:24 PM PST 24
Finished Feb 07 01:51:46 PM PST 24
Peak memory 257780 kb
Host smart-c9f6d30f-ec08-4d1e-85c9-4588e4065c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591132856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1591132856
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.190177663
Short name T682
Test name
Test status
Simulation time 49033000 ps
CPU time 128.11 seconds
Started Feb 07 01:50:20 PM PST 24
Finished Feb 07 01:52:30 PM PST 24
Peak memory 276924 kb
Host smart-c3ee3c63-b228-418a-8aaa-7b6cb38d9b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190177663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.190177663
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.4169431879
Short name T897
Test name
Test status
Simulation time 8024414100 ps
CPU time 184.96 seconds
Started Feb 07 01:50:21 PM PST 24
Finished Feb 07 01:53:27 PM PST 24
Peak memory 264052 kb
Host smart-c75db3d8-2549-4bf2-9bbc-688455bebc68
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169431879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.4169431879
Directory /workspace/9.flash_ctrl_wo/latest
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