Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	326258	1		T1	1		T2	2		T3	2
all_values[1]	326258	1		T1	1		T2	2		T3	2
all_values[2]	326258	1		T1	1		T2	2		T3	2
all_values[3]	326258	1		T1	1		T2	2		T3	2
all_values[4]	326258	1		T1	1		T2	2		T3	2
all_values[5]	326258	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9967	1		T1	6		T2	12		T3	12
auto[1]	1947581	1		T7	11868		T30	14286		T20	13650

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1582070	1		T1	6		T2	8		T3	10
auto[1]	375478	1		T2	4		T3	2		T4	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1215	1		T1	1		T2	1		T3	2
all_values[0]	auto[0]	auto[1]	422	1		T2	1		T4	1		T13	1
all_values[0]	auto[1]	auto[0]	255611	1		T7	1978		T30	2381		T20	2275
all_values[0]	auto[1]	auto[1]	69010	1		T120	2990		T60	2080		T168	4208
all_values[1]	auto[0]	auto[0]	1605	1		T1	1		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	59	1		T235	1		T237	3		T308	3
all_values[1]	auto[1]	auto[0]	275591	1		T7	1978		T30	2381		T20	2275
all_values[1]	auto[1]	auto[1]	49003	1		T120	5159		T60	3981		T121	4843
all_values[2]	auto[0]	auto[0]	1529	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	129	1		T2	1		T23	1		T122	1
all_values[2]	auto[1]	auto[0]	316045	1		T7	1570		T30	2368		T20	2275
all_values[2]	auto[1]	auto[1]	8555	1		T7	408		T30	13		T59	1
all_values[3]	auto[0]	auto[0]	1509	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	155	1		T2	1		T23	1		T122	1
all_values[3]	auto[1]	auto[0]	172894	1		T7	936		T30	268		T20	1022
all_values[3]	auto[1]	auto[1]	151700	1		T7	1042		T30	2113		T20	1253
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	543	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	228907	1		T7	991		T30	1223		T20	1253
all_values[4]	auto[1]	auto[1]	95668	1		T7	987		T30	1158		T20	1022
all_values[5]	auto[0]	auto[0]	1506	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	155	1		T3	1		T19	1		T8	1
all_values[5]	auto[1]	auto[0]	324518	1		T7	1978		T30	2381		T20	2275
all_values[5]	auto[1]	auto[1]	79	1		T235	2		T236	1		T308	3