Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T2 |
11 |
|
T27 |
14 |
|
T73 |
1 |
| others[1] |
244 |
1 |
|
T2 |
9 |
|
T27 |
13 |
|
T23 |
10 |
| others[2] |
224 |
1 |
|
T2 |
6 |
|
T27 |
9 |
|
T23 |
7 |
| others[3] |
400 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T7 |
1 |
| false |
120 |
1 |
|
T2 |
5 |
|
T27 |
7 |
|
T23 |
3 |
| true |
13437 |
1 |
|
T1 |
1 |
|
T2 |
59 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T2 |
10 |
|
T27 |
10 |
|
T23 |
7 |
| others[1] |
250 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T27 |
13 |
| others[2] |
226 |
1 |
|
T2 |
9 |
|
T27 |
9 |
|
T46 |
1 |
| others[3] |
370 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T27 |
11 |
| false |
118 |
1 |
|
T2 |
4 |
|
T9 |
2 |
|
T27 |
10 |
| true |
13503 |
1 |
|
T1 |
1 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8989 |
1 |
|
T2 |
16 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
1297 |
1 |
|
T2 |
18 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
1212 |
1 |
|
T2 |
21 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
2091 |
1 |
|
T2 |
34 |
|
T9 |
1 |
|
T27 |
36 |
| false |
660 |
1 |
|
T2 |
12 |
|
T27 |
14 |
|
T23 |
9 |
| true |
416 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9014 |
1 |
|
T2 |
18 |
|
T13 |
2 |
|
T5 |
1 |
| others[1] |
1266 |
1 |
|
T2 |
20 |
|
T27 |
18 |
|
T23 |
18 |
| others[2] |
1245 |
1 |
|
T2 |
16 |
|
T27 |
21 |
|
T73 |
1 |
| others[3] |
2043 |
1 |
|
T2 |
29 |
|
T9 |
1 |
|
T27 |
31 |
| false |
705 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T27 |
9 |
| true |
392 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T2 |
4 |
|
T27 |
8 |
|
T23 |
2 |
| others[1] |
116 |
1 |
|
T2 |
4 |
|
T27 |
5 |
|
T23 |
8 |
| others[2] |
111 |
1 |
|
T2 |
1 |
|
T27 |
4 |
|
T23 |
3 |
| others[3] |
188 |
1 |
|
T2 |
7 |
|
T27 |
7 |
|
T23 |
5 |
| false |
66 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T24 |
7 |
| true |
14069 |
1 |
|
T1 |
1 |
|
T2 |
83 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
9 |
|
T27 |
8 |
|
T49 |
1 |
| others[1] |
246 |
1 |
|
T2 |
15 |
|
T27 |
13 |
|
T131 |
1 |
| others[2] |
234 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T7 |
1 |
| others[3] |
436 |
1 |
|
T2 |
19 |
|
T9 |
1 |
|
T47 |
1 |
| false |
126 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T46 |
1 |
| true |
13394 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8811 |
1 |
|
T2 |
19 |
|
T13 |
2 |
|
T7 |
1 |
| others[1] |
1014 |
1 |
|
T2 |
23 |
|
T3 |
1 |
|
T30 |
1 |
| others[2] |
1075 |
1 |
|
T2 |
25 |
|
T5 |
1 |
|
T9 |
3 |
| others[3] |
1800 |
1 |
|
T1 |
1 |
|
T2 |
28 |
|
T9 |
1 |
| false |
563 |
1 |
|
T2 |
6 |
|
T4 |
1 |
|
T27 |
6 |
| true |
1402 |
1 |
|
T9 |
2 |
|
T19 |
2 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T2 |
15 |
|
T7 |
1 |
|
T27 |
10 |
| others[1] |
216 |
1 |
|
T2 |
6 |
|
T27 |
9 |
|
T23 |
11 |
| others[2] |
247 |
1 |
|
T2 |
5 |
|
T27 |
10 |
|
T73 |
1 |
| others[3] |
349 |
1 |
|
T2 |
13 |
|
T27 |
17 |
|
T23 |
13 |
| false |
127 |
1 |
|
T2 |
5 |
|
T27 |
5 |
|
T23 |
9 |
| true |
13480 |
1 |
|
T1 |
1 |
|
T2 |
57 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T27 |
8 |
| others[1] |
218 |
1 |
|
T2 |
10 |
|
T27 |
7 |
|
T45 |
1 |
| others[2] |
231 |
1 |
|
T2 |
13 |
|
T22 |
1 |
|
T27 |
7 |
| others[3] |
348 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T8 |
1 |
| false |
117 |
1 |
|
T2 |
7 |
|
T27 |
3 |
|
T23 |
6 |
| true |
13519 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8982 |
1 |
|
T2 |
18 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
1262 |
1 |
|
T2 |
28 |
|
T4 |
1 |
|
T8 |
1 |
| others[2] |
1227 |
1 |
|
T2 |
15 |
|
T27 |
22 |
|
T140 |
2 |
| others[3] |
2108 |
1 |
|
T2 |
32 |
|
T5 |
1 |
|
T9 |
1 |
| false |
660 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
9 |
| true |
426 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T2 |
18 |
|
T9 |
2 |
|
T6 |
1 |
| others[1] |
1281 |
1 |
|
T2 |
13 |
|
T27 |
13 |
|
T73 |
1 |
| others[2] |
1254 |
1 |
|
T2 |
22 |
|
T9 |
1 |
|
T27 |
19 |
| others[3] |
2089 |
1 |
|
T2 |
36 |
|
T4 |
1 |
|
T5 |
1 |
| false |
644 |
1 |
|
T2 |
12 |
|
T27 |
12 |
|
T140 |
2 |
| true |
405 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
131 |
1 |
|
T2 |
2 |
|
T27 |
6 |
|
T23 |
4 |
| others[1] |
108 |
1 |
|
T2 |
2 |
|
T27 |
1 |
|
T23 |
4 |
| others[2] |
100 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
5 |
| others[3] |
181 |
1 |
|
T2 |
8 |
|
T27 |
6 |
|
T23 |
3 |
| false |
57 |
1 |
|
T2 |
2 |
|
T23 |
2 |
|
T24 |
2 |
| true |
6375 |
1 |
|
T1 |
1 |
|
T2 |
84 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T2 |
7 |
|
T22 |
1 |
|
T27 |
7 |
| others[1] |
256 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T9 |
2 |
| others[2] |
222 |
1 |
|
T2 |
12 |
|
T27 |
10 |
|
T45 |
1 |
| others[3] |
377 |
1 |
|
T1 |
1 |
|
T2 |
16 |
|
T9 |
2 |
| false |
133 |
1 |
|
T2 |
4 |
|
T27 |
6 |
|
T73 |
1 |
| true |
5741 |
1 |
|
T2 |
49 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1101 |
1 |
|
T2 |
15 |
|
T9 |
3 |
|
T7 |
1 |
| others[1] |
1054 |
1 |
|
T2 |
22 |
|
T47 |
1 |
|
T27 |
17 |
| others[2] |
1062 |
1 |
|
T2 |
19 |
|
T9 |
1 |
|
T27 |
15 |
| others[3] |
1783 |
1 |
|
T1 |
1 |
|
T2 |
33 |
|
T4 |
1 |
| false |
567 |
1 |
|
T2 |
12 |
|
T19 |
2 |
|
T41 |
1 |
| true |
1385 |
1 |
|
T3 |
1 |
|
T9 |
2 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T2 |
13 |
|
T27 |
7 |
|
T45 |
1 |
| others[1] |
224 |
1 |
|
T2 |
10 |
|
T47 |
1 |
|
T27 |
6 |
| others[2] |
244 |
1 |
|
T2 |
8 |
|
T22 |
1 |
|
T27 |
13 |
| others[3] |
399 |
1 |
|
T2 |
19 |
|
T7 |
1 |
|
T27 |
24 |
| false |
140 |
1 |
|
T2 |
7 |
|
T8 |
1 |
|
T27 |
12 |
| true |
5720 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T27 |
5 |
| others[1] |
228 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T27 |
9 |
| others[2] |
216 |
1 |
|
T2 |
10 |
|
T9 |
2 |
|
T27 |
9 |
| others[3] |
389 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T27 |
18 |
| false |
99 |
1 |
|
T2 |
5 |
|
T27 |
2 |
|
T23 |
7 |
| true |
5788 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T2 |
14 |
|
T27 |
19 |
|
T140 |
1 |
| others[1] |
1275 |
1 |
|
T2 |
24 |
|
T27 |
17 |
|
T49 |
1 |
| others[2] |
1249 |
1 |
|
T2 |
21 |
|
T27 |
20 |
|
T140 |
3 |
| others[3] |
2095 |
1 |
|
T2 |
30 |
|
T4 |
1 |
|
T5 |
1 |
| false |
690 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T6 |
1 |
| true |
431 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T2 |
22 |
|
T6 |
1 |
|
T27 |
22 |
| others[1] |
1250 |
1 |
|
T2 |
26 |
|
T5 |
1 |
|
T27 |
18 |
| others[2] |
1302 |
1 |
|
T2 |
16 |
|
T27 |
15 |
|
T140 |
2 |
| others[3] |
2146 |
1 |
|
T2 |
27 |
|
T4 |
1 |
|
T47 |
1 |
| false |
649 |
1 |
|
T2 |
10 |
|
T27 |
8 |
|
T23 |
10 |
| true |
406 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T2 |
4 |
|
T27 |
9 |
|
T45 |
1 |
| others[1] |
103 |
1 |
|
T2 |
3 |
|
T27 |
3 |
|
T23 |
5 |
| others[2] |
110 |
1 |
|
T2 |
1 |
|
T27 |
3 |
|
T23 |
2 |
| others[3] |
184 |
1 |
|
T2 |
3 |
|
T27 |
12 |
|
T23 |
6 |
| false |
74 |
1 |
|
T2 |
2 |
|
T27 |
2 |
|
T23 |
3 |
| true |
6368 |
1 |
|
T1 |
1 |
|
T2 |
88 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T22 |
1 |
| others[1] |
243 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T27 |
8 |
| others[2] |
235 |
1 |
|
T2 |
9 |
|
T30 |
1 |
|
T27 |
5 |
| others[3] |
395 |
1 |
|
T2 |
19 |
|
T7 |
1 |
|
T47 |
1 |
| false |
133 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T27 |
4 |
| true |
5696 |
1 |
|
T2 |
49 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1141 |
1 |
|
T2 |
20 |
|
T22 |
1 |
|
T30 |
1 |
| others[1] |
1105 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T6 |
1 |
| others[2] |
1034 |
1 |
|
T2 |
28 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
1718 |
1 |
|
T1 |
1 |
|
T2 |
26 |
|
T9 |
2 |
| false |
582 |
1 |
|
T2 |
9 |
|
T27 |
11 |
|
T45 |
1 |
| true |
1372 |
1 |
|
T3 |
1 |
|
T9 |
4 |
|
T19 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T2 |
8 |
|
T27 |
10 |
|
T23 |
8 |
| others[1] |
249 |
1 |
|
T2 |
8 |
|
T27 |
10 |
|
T45 |
1 |
| others[2] |
233 |
1 |
|
T2 |
13 |
|
T27 |
11 |
|
T46 |
1 |
| others[3] |
390 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T27 |
16 |
| false |
137 |
1 |
|
T2 |
6 |
|
T7 |
1 |
|
T27 |
9 |
| true |
5721 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T27 |
8 |
| others[1] |
209 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T27 |
6 |
| others[2] |
234 |
1 |
|
T2 |
9 |
|
T9 |
2 |
|
T27 |
11 |
| others[3] |
403 |
1 |
|
T2 |
16 |
|
T9 |
2 |
|
T22 |
1 |
| false |
107 |
1 |
|
T2 |
5 |
|
T27 |
7 |
|
T23 |
2 |
| true |
5770 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T2 |
22 |
|
T27 |
20 |
|
T140 |
1 |
| others[1] |
1246 |
1 |
|
T2 |
17 |
|
T27 |
16 |
|
T140 |
3 |
| others[2] |
1280 |
1 |
|
T2 |
24 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
2054 |
1 |
|
T2 |
30 |
|
T9 |
1 |
|
T41 |
1 |
| false |
666 |
1 |
|
T2 |
8 |
|
T5 |
1 |
|
T6 |
1 |
| true |
427 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1340 |
1 |
|
T2 |
25 |
|
T5 |
1 |
|
T27 |
18 |
| others[1] |
1212 |
1 |
|
T2 |
17 |
|
T6 |
1 |
|
T27 |
21 |
| others[2] |
1266 |
1 |
|
T2 |
24 |
|
T4 |
1 |
|
T27 |
22 |
| others[3] |
2054 |
1 |
|
T2 |
26 |
|
T27 |
32 |
|
T140 |
5 |
| false |
673 |
1 |
|
T2 |
9 |
|
T27 |
8 |
|
T140 |
3 |
| true |
407 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
3 |
| others[1] |
111 |
1 |
|
T2 |
4 |
|
T27 |
2 |
|
T23 |
4 |
| others[2] |
112 |
1 |
|
T2 |
5 |
|
T27 |
2 |
|
T23 |
5 |
| others[3] |
226 |
1 |
|
T2 |
11 |
|
T27 |
6 |
|
T23 |
8 |
| false |
53 |
1 |
|
T2 |
2 |
|
T27 |
2 |
|
T23 |
1 |
| true |
6358 |
1 |
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T9 |
2 |
| others[1] |
249 |
1 |
|
T2 |
9 |
|
T27 |
7 |
|
T23 |
10 |
| others[2] |
248 |
1 |
|
T2 |
9 |
|
T8 |
1 |
|
T27 |
15 |
| others[3] |
393 |
1 |
|
T2 |
21 |
|
T9 |
1 |
|
T27 |
13 |
| false |
122 |
1 |
|
T2 |
6 |
|
T30 |
1 |
|
T27 |
2 |
| true |
5706 |
1 |
|
T2 |
49 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1118 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T5 |
1 |
| others[1] |
1082 |
1 |
|
T1 |
1 |
|
T2 |
20 |
|
T4 |
1 |
| others[2] |
1090 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T41 |
1 |
| others[3] |
1721 |
1 |
|
T2 |
38 |
|
T14 |
1 |
|
T27 |
32 |
| false |
535 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T27 |
9 |
| true |
1406 |
1 |
|
T9 |
1 |
|
T19 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T2 |
12 |
|
T27 |
5 |
|
T45 |
1 |
| others[1] |
237 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T27 |
13 |
| others[2] |
222 |
1 |
|
T2 |
6 |
|
T27 |
12 |
|
T23 |
8 |
| others[3] |
399 |
1 |
|
T2 |
23 |
|
T8 |
1 |
|
T27 |
20 |
| false |
114 |
1 |
|
T2 |
4 |
|
T27 |
5 |
|
T23 |
2 |
| true |
5760 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T27 |
12 |
| others[1] |
238 |
1 |
|
T2 |
15 |
|
T22 |
1 |
|
T27 |
10 |
| others[2] |
231 |
1 |
|
T2 |
6 |
|
T27 |
6 |
|
T23 |
11 |
| others[3] |
372 |
1 |
|
T2 |
10 |
|
T8 |
1 |
|
T27 |
16 |
| false |
115 |
1 |
|
T2 |
5 |
|
T27 |
6 |
|
T23 |
9 |
| true |
5756 |
1 |
|
T1 |
1 |
|
T2 |
50 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T2 |
18 |
|
T5 |
1 |
|
T19 |
1 |
| others[1] |
1260 |
1 |
|
T2 |
18 |
|
T9 |
2 |
|
T27 |
24 |
| others[2] |
1196 |
1 |
|
T2 |
24 |
|
T27 |
19 |
|
T140 |
1 |
| others[3] |
2124 |
1 |
|
T2 |
33 |
|
T4 |
1 |
|
T6 |
1 |
| false |
695 |
1 |
|
T2 |
8 |
|
T27 |
9 |
|
T140 |
1 |
| true |
413 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |