Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T2 |
14 |
|
T27 |
15 |
|
T140 |
1 |
| others[1] |
1297 |
1 |
|
T2 |
19 |
|
T5 |
1 |
|
T27 |
16 |
| others[2] |
1236 |
1 |
|
T2 |
19 |
|
T6 |
1 |
|
T27 |
20 |
| others[3] |
2103 |
1 |
|
T2 |
42 |
|
T4 |
1 |
|
T27 |
37 |
| false |
619 |
1 |
|
T2 |
7 |
|
T27 |
13 |
|
T23 |
8 |
| true |
407 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T2 |
4 |
|
T27 |
1 |
|
T23 |
3 |
| others[1] |
110 |
1 |
|
T2 |
5 |
|
T8 |
1 |
|
T27 |
4 |
| others[2] |
117 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T23 |
2 |
| others[3] |
175 |
1 |
|
T2 |
4 |
|
T27 |
8 |
|
T23 |
9 |
| false |
72 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T23 |
1 |
| true |
6358 |
1 |
|
T1 |
1 |
|
T2 |
80 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
266 |
1 |
|
T2 |
17 |
|
T27 |
13 |
|
T23 |
8 |
| others[1] |
232 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T27 |
10 |
| others[2] |
243 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
9 |
| others[3] |
396 |
1 |
|
T2 |
18 |
|
T22 |
1 |
|
T27 |
15 |
| false |
113 |
1 |
|
T2 |
3 |
|
T9 |
1 |
|
T27 |
1 |
| true |
5702 |
1 |
|
T1 |
1 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T2 |
20 |
|
T6 |
1 |
|
T27 |
14 |
| others[1] |
1055 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T27 |
17 |
| others[2] |
1115 |
1 |
|
T2 |
26 |
|
T27 |
23 |
|
T140 |
3 |
| others[3] |
1770 |
1 |
|
T2 |
32 |
|
T5 |
1 |
|
T9 |
2 |
| false |
544 |
1 |
|
T2 |
7 |
|
T27 |
11 |
|
T23 |
11 |
| true |
1422 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T2 |
9 |
|
T27 |
11 |
|
T23 |
6 |
| others[1] |
235 |
1 |
|
T2 |
5 |
|
T27 |
9 |
|
T46 |
1 |
| others[2] |
251 |
1 |
|
T2 |
13 |
|
T27 |
8 |
|
T23 |
15 |
| others[3] |
385 |
1 |
|
T2 |
17 |
|
T47 |
1 |
|
T8 |
1 |
| false |
120 |
1 |
|
T2 |
8 |
|
T27 |
6 |
|
T23 |
7 |
| true |
5736 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T2 |
10 |
|
T9 |
1 |
|
T27 |
10 |
| others[1] |
220 |
1 |
|
T2 |
9 |
|
T27 |
12 |
|
T23 |
9 |
| others[2] |
231 |
1 |
|
T2 |
9 |
|
T3 |
1 |
|
T27 |
14 |
| others[3] |
381 |
1 |
|
T2 |
21 |
|
T9 |
3 |
|
T22 |
1 |
| false |
109 |
1 |
|
T2 |
5 |
|
T27 |
1 |
|
T45 |
1 |
| true |
5801 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T2 |
14 |
|
T27 |
15 |
|
T140 |
3 |
| others[1] |
1228 |
1 |
|
T2 |
23 |
|
T5 |
1 |
|
T27 |
18 |
| others[2] |
1274 |
1 |
|
T2 |
20 |
|
T19 |
1 |
|
T27 |
22 |
| others[3] |
2101 |
1 |
|
T2 |
35 |
|
T4 |
1 |
|
T9 |
2 |
| false |
657 |
1 |
|
T2 |
9 |
|
T6 |
1 |
|
T27 |
12 |
| true |
423 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T27 |
18 |
| others[1] |
1255 |
1 |
|
T2 |
17 |
|
T27 |
21 |
|
T140 |
2 |
| others[2] |
1196 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2206 |
1 |
|
T2 |
44 |
|
T9 |
1 |
|
T27 |
27 |
| false |
620 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T27 |
11 |
| true |
410 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T2 |
5 |
|
T27 |
3 |
|
T24 |
6 |
| others[1] |
119 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
5 |
| others[2] |
126 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
5 |
| others[3] |
192 |
1 |
|
T2 |
4 |
|
T8 |
1 |
|
T27 |
6 |
| false |
61 |
1 |
|
T27 |
2 |
|
T23 |
1 |
|
T24 |
2 |
| true |
6363 |
1 |
|
T1 |
1 |
|
T2 |
87 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T27 |
10 |
| others[1] |
249 |
1 |
|
T2 |
10 |
|
T47 |
1 |
|
T27 |
9 |
| others[2] |
231 |
1 |
|
T2 |
9 |
|
T7 |
1 |
|
T30 |
1 |
| others[3] |
428 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T8 |
1 |
| false |
118 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T9 |
1 |
| true |
5699 |
1 |
|
T2 |
44 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1072 |
1 |
|
T2 |
28 |
|
T9 |
1 |
|
T47 |
1 |
| others[1] |
1079 |
1 |
|
T2 |
17 |
|
T19 |
1 |
|
T6 |
1 |
| others[2] |
1081 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T27 |
17 |
| others[3] |
1759 |
1 |
|
T2 |
28 |
|
T9 |
1 |
|
T19 |
1 |
| false |
584 |
1 |
|
T2 |
10 |
|
T5 |
1 |
|
T9 |
1 |
| true |
1377 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
9 |
|
T47 |
1 |
|
T27 |
9 |
| others[1] |
238 |
1 |
|
T2 |
8 |
|
T27 |
11 |
|
T73 |
1 |
| others[2] |
233 |
1 |
|
T2 |
10 |
|
T8 |
1 |
|
T27 |
8 |
| others[3] |
406 |
1 |
|
T2 |
19 |
|
T30 |
1 |
|
T27 |
18 |
| false |
118 |
1 |
|
T2 |
6 |
|
T27 |
2 |
|
T23 |
4 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T27 |
11 |
| others[1] |
233 |
1 |
|
T2 |
11 |
|
T22 |
1 |
|
T27 |
12 |
| others[2] |
232 |
1 |
|
T2 |
9 |
|
T3 |
1 |
|
T27 |
13 |
| others[3] |
372 |
1 |
|
T2 |
16 |
|
T9 |
2 |
|
T8 |
1 |
| false |
124 |
1 |
|
T2 |
6 |
|
T27 |
4 |
|
T23 |
4 |
| true |
5777 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T2 |
25 |
|
T5 |
1 |
|
T9 |
1 |
| others[1] |
1246 |
1 |
|
T2 |
18 |
|
T27 |
30 |
|
T140 |
3 |
| others[2] |
1231 |
1 |
|
T2 |
19 |
|
T27 |
19 |
|
T140 |
1 |
| others[3] |
2118 |
1 |
|
T2 |
28 |
|
T19 |
1 |
|
T6 |
1 |
| false |
674 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T27 |
5 |
| true |
417 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T27 |
20 |
| others[1] |
1256 |
1 |
|
T2 |
19 |
|
T4 |
1 |
|
T27 |
22 |
| others[2] |
1302 |
1 |
|
T2 |
20 |
|
T27 |
18 |
|
T140 |
2 |
| others[3] |
2077 |
1 |
|
T2 |
31 |
|
T9 |
1 |
|
T6 |
1 |
| false |
627 |
1 |
|
T2 |
14 |
|
T27 |
4 |
|
T49 |
1 |
| true |
409 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
4 |
| others[1] |
104 |
1 |
|
T2 |
4 |
|
T27 |
4 |
|
T23 |
5 |
| others[2] |
108 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T27 |
2 |
| others[3] |
189 |
1 |
|
T2 |
7 |
|
T27 |
8 |
|
T23 |
11 |
| false |
62 |
1 |
|
T2 |
3 |
|
T27 |
3 |
|
T23 |
1 |
| true |
6369 |
1 |
|
T1 |
1 |
|
T2 |
82 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
6 |
|
T9 |
2 |
|
T8 |
1 |
| others[1] |
242 |
1 |
|
T2 |
8 |
|
T22 |
1 |
|
T27 |
8 |
| others[2] |
251 |
1 |
|
T2 |
14 |
|
T9 |
1 |
|
T47 |
1 |
| others[3] |
407 |
1 |
|
T2 |
19 |
|
T3 |
1 |
|
T9 |
1 |
| false |
122 |
1 |
|
T2 |
3 |
|
T9 |
1 |
|
T30 |
1 |
| true |
5699 |
1 |
|
T1 |
1 |
|
T2 |
51 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1072 |
1 |
|
T2 |
24 |
|
T9 |
1 |
|
T14 |
1 |
| others[1] |
1100 |
1 |
|
T2 |
19 |
|
T9 |
1 |
|
T19 |
1 |
| others[2] |
1054 |
1 |
|
T2 |
17 |
|
T6 |
1 |
|
T27 |
20 |
| others[3] |
1776 |
1 |
|
T1 |
1 |
|
T2 |
34 |
|
T4 |
1 |
| false |
564 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T5 |
1 |
| true |
1386 |
1 |
|
T9 |
2 |
|
T8 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T2 |
9 |
|
T27 |
10 |
|
T46 |
1 |
| others[1] |
238 |
1 |
|
T2 |
13 |
|
T27 |
10 |
|
T23 |
10 |
| others[2] |
253 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T7 |
1 |
| others[3] |
360 |
1 |
|
T2 |
13 |
|
T27 |
17 |
|
T23 |
12 |
| false |
107 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
6 |
| true |
5755 |
1 |
|
T1 |
1 |
|
T2 |
53 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T2 |
10 |
|
T9 |
1 |
|
T27 |
8 |
| others[1] |
220 |
1 |
|
T2 |
10 |
|
T27 |
11 |
|
T23 |
12 |
| others[2] |
224 |
1 |
|
T2 |
11 |
|
T27 |
7 |
|
T45 |
1 |
| others[3] |
339 |
1 |
|
T2 |
16 |
|
T27 |
17 |
|
T23 |
11 |
| false |
113 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T27 |
5 |
| true |
5820 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T27 |
15 |
| others[1] |
1270 |
1 |
|
T2 |
27 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
1297 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T27 |
24 |
| others[3] |
2051 |
1 |
|
T2 |
29 |
|
T6 |
1 |
|
T27 |
29 |
| false |
666 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T27 |
10 |
| true |
413 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T2 |
18 |
|
T27 |
30 |
|
T140 |
4 |
| others[1] |
1248 |
1 |
|
T2 |
19 |
|
T27 |
26 |
|
T140 |
2 |
| others[2] |
1313 |
1 |
|
T2 |
25 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2047 |
1 |
|
T2 |
33 |
|
T9 |
2 |
|
T47 |
1 |
| false |
678 |
1 |
|
T2 |
6 |
|
T27 |
6 |
|
T49 |
1 |
| true |
399 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
129 |
1 |
|
T2 |
7 |
|
T27 |
2 |
|
T23 |
4 |
| others[1] |
109 |
1 |
|
T27 |
3 |
|
T23 |
5 |
|
T24 |
2 |
| others[2] |
118 |
1 |
|
T2 |
5 |
|
T27 |
4 |
|
T23 |
6 |
| others[3] |
194 |
1 |
|
T2 |
6 |
|
T27 |
5 |
|
T23 |
3 |
| false |
62 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
2 |
| true |
6340 |
1 |
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T2 |
10 |
|
T8 |
1 |
|
T27 |
10 |
| others[1] |
228 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T27 |
12 |
| others[2] |
221 |
1 |
|
T2 |
4 |
|
T27 |
6 |
|
T45 |
1 |
| others[3] |
431 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T27 |
15 |
| false |
145 |
1 |
|
T2 |
4 |
|
T27 |
8 |
|
T49 |
1 |
| true |
5711 |
1 |
|
T2 |
56 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1101 |
1 |
|
T2 |
21 |
|
T9 |
3 |
|
T8 |
1 |
| others[1] |
1100 |
1 |
|
T2 |
25 |
|
T5 |
1 |
|
T6 |
1 |
| others[2] |
1070 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T14 |
1 |
| others[3] |
1806 |
1 |
|
T2 |
33 |
|
T4 |
1 |
|
T27 |
30 |
| false |
547 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T7 |
1 |
| true |
1328 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T2 |
13 |
|
T27 |
9 |
|
T23 |
12 |
| others[1] |
228 |
1 |
|
T2 |
15 |
|
T3 |
1 |
|
T27 |
9 |
| others[2] |
247 |
1 |
|
T2 |
14 |
|
T47 |
1 |
|
T27 |
9 |
| others[3] |
405 |
1 |
|
T2 |
13 |
|
T7 |
1 |
|
T27 |
14 |
| false |
120 |
1 |
|
T2 |
2 |
|
T22 |
1 |
|
T27 |
5 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T2 |
15 |
|
T9 |
2 |
|
T27 |
11 |
| others[1] |
254 |
1 |
|
T2 |
9 |
|
T8 |
1 |
|
T27 |
14 |
| others[2] |
199 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T9 |
2 |
| others[3] |
380 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T27 |
14 |
| false |
113 |
1 |
|
T2 |
2 |
|
T27 |
7 |
|
T23 |
6 |
| true |
5797 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T2 |
16 |
|
T19 |
1 |
|
T27 |
21 |
| others[1] |
1245 |
1 |
|
T2 |
17 |
|
T4 |
1 |
|
T27 |
16 |
| others[2] |
1211 |
1 |
|
T2 |
20 |
|
T9 |
1 |
|
T27 |
16 |
| others[3] |
2194 |
1 |
|
T2 |
35 |
|
T5 |
1 |
|
T6 |
1 |
| false |
657 |
1 |
|
T2 |
13 |
|
T27 |
10 |
|
T140 |
1 |
| true |
419 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T2 |
16 |
|
T27 |
18 |
|
T23 |
19 |
| others[1] |
1280 |
1 |
|
T2 |
16 |
|
T27 |
23 |
|
T140 |
2 |
| others[2] |
1311 |
1 |
|
T2 |
17 |
|
T4 |
1 |
|
T27 |
20 |
| others[3] |
2041 |
1 |
|
T2 |
41 |
|
T5 |
1 |
|
T47 |
1 |
| false |
647 |
1 |
|
T2 |
11 |
|
T27 |
13 |
|
T23 |
7 |
| true |
400 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
128 |
1 |
|
T2 |
5 |
|
T22 |
1 |
|
T27 |
3 |
| others[1] |
110 |
1 |
|
T2 |
4 |
|
T27 |
5 |
|
T23 |
3 |
| others[2] |
117 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T23 |
5 |
| others[3] |
189 |
1 |
|
T2 |
5 |
|
T27 |
9 |
|
T23 |
8 |
| false |
68 |
1 |
|
T2 |
1 |
|
T27 |
2 |
|
T23 |
2 |
| true |
6340 |
1 |
|
T1 |
1 |
|
T2 |
82 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T9 |
1 |
| others[1] |
247 |
1 |
|
T2 |
10 |
|
T27 |
6 |
|
T23 |
12 |
| others[2] |
224 |
1 |
|
T2 |
14 |
|
T9 |
1 |
|
T27 |
10 |
| others[3] |
416 |
1 |
|
T2 |
25 |
|
T9 |
2 |
|
T27 |
26 |
| false |
144 |
1 |
|
T2 |
2 |
|
T22 |
1 |
|
T27 |
2 |
| true |
5688 |
1 |
|
T1 |
1 |
|
T2 |
43 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |