Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1054 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T4 |
1 |
| others[1] |
1098 |
1 |
|
T2 |
21 |
|
T9 |
1 |
|
T22 |
1 |
| others[2] |
1071 |
1 |
|
T2 |
28 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
1774 |
1 |
|
T2 |
32 |
|
T9 |
3 |
|
T27 |
36 |
| false |
554 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
8 |
| true |
1401 |
1 |
|
T3 |
1 |
|
T9 |
1 |
|
T19 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T2 |
19 |
|
T7 |
1 |
|
T22 |
1 |
| others[1] |
235 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T27 |
11 |
| others[2] |
219 |
1 |
|
T2 |
8 |
|
T27 |
5 |
|
T45 |
1 |
| others[3] |
419 |
1 |
|
T2 |
10 |
|
T27 |
14 |
|
T23 |
20 |
| false |
109 |
1 |
|
T2 |
4 |
|
T27 |
7 |
|
T23 |
3 |
| true |
5723 |
1 |
|
T1 |
1 |
|
T2 |
50 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T2 |
9 |
|
T27 |
9 |
|
T23 |
7 |
| others[1] |
248 |
1 |
|
T2 |
19 |
|
T27 |
7 |
|
T46 |
1 |
| others[2] |
213 |
1 |
|
T2 |
12 |
|
T27 |
14 |
|
T23 |
8 |
| others[3] |
338 |
1 |
|
T2 |
9 |
|
T22 |
1 |
|
T27 |
12 |
| false |
112 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T27 |
6 |
| true |
5819 |
1 |
|
T1 |
1 |
|
T2 |
45 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T2 |
26 |
|
T27 |
27 |
|
T140 |
2 |
| others[1] |
1256 |
1 |
|
T2 |
12 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
1244 |
1 |
|
T2 |
16 |
|
T27 |
14 |
|
T140 |
2 |
| others[3] |
2125 |
1 |
|
T2 |
35 |
|
T9 |
1 |
|
T6 |
1 |
| false |
677 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T27 |
10 |
| true |
414 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T2 |
18 |
|
T47 |
1 |
|
T27 |
13 |
| others[1] |
1250 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T6 |
1 |
| others[2] |
1330 |
1 |
|
T2 |
19 |
|
T27 |
18 |
|
T73 |
1 |
| others[3] |
2104 |
1 |
|
T2 |
40 |
|
T5 |
1 |
|
T27 |
32 |
| false |
626 |
1 |
|
T2 |
8 |
|
T4 |
1 |
|
T27 |
10 |
| true |
393 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T27 |
3 |
| others[1] |
121 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
1 |
| others[2] |
113 |
1 |
|
T2 |
3 |
|
T27 |
5 |
|
T23 |
3 |
| others[3] |
199 |
1 |
|
T2 |
6 |
|
T27 |
6 |
|
T23 |
3 |
| false |
54 |
1 |
|
T2 |
1 |
|
T27 |
4 |
|
T23 |
1 |
| true |
6349 |
1 |
|
T1 |
1 |
|
T2 |
85 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
12 |
|
T9 |
2 |
|
T27 |
10 |
| others[1] |
256 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T47 |
1 |
| others[2] |
243 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T9 |
1 |
| others[3] |
375 |
1 |
|
T2 |
16 |
|
T27 |
15 |
|
T49 |
1 |
| false |
122 |
1 |
|
T2 |
1 |
|
T9 |
1 |
|
T27 |
8 |
| true |
5729 |
1 |
|
T2 |
56 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1132 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1044 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T9 |
3 |
| others[2] |
1072 |
1 |
|
T2 |
20 |
|
T9 |
2 |
|
T47 |
1 |
| others[3] |
1763 |
1 |
|
T2 |
32 |
|
T30 |
1 |
|
T27 |
31 |
| false |
546 |
1 |
|
T2 |
12 |
|
T14 |
1 |
|
T27 |
12 |
| true |
1395 |
1 |
|
T3 |
1 |
|
T9 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
13 |
|
T8 |
1 |
|
T27 |
11 |
| others[1] |
212 |
1 |
|
T2 |
6 |
|
T22 |
1 |
|
T27 |
6 |
| others[2] |
246 |
1 |
|
T2 |
10 |
|
T27 |
8 |
|
T23 |
11 |
| others[3] |
402 |
1 |
|
T2 |
19 |
|
T7 |
1 |
|
T27 |
21 |
| false |
109 |
1 |
|
T2 |
5 |
|
T27 |
3 |
|
T23 |
4 |
| true |
5756 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T27 |
15 |
| others[1] |
212 |
1 |
|
T2 |
11 |
|
T9 |
2 |
|
T22 |
1 |
| others[2] |
215 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T8 |
1 |
| others[3] |
405 |
1 |
|
T2 |
24 |
|
T9 |
2 |
|
T27 |
24 |
| false |
117 |
1 |
|
T2 |
7 |
|
T27 |
5 |
|
T23 |
5 |
| true |
5786 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T9 |
1 |
| others[1] |
1244 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T27 |
23 |
| others[2] |
1257 |
1 |
|
T2 |
16 |
|
T19 |
1 |
|
T27 |
13 |
| others[3] |
2167 |
1 |
|
T2 |
44 |
|
T5 |
1 |
|
T27 |
34 |
| false |
642 |
1 |
|
T2 |
9 |
|
T6 |
1 |
|
T27 |
8 |
| true |
427 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T2 |
13 |
|
T5 |
1 |
|
T6 |
1 |
| others[1] |
1263 |
1 |
|
T2 |
18 |
|
T27 |
20 |
|
T140 |
2 |
| others[2] |
1254 |
1 |
|
T2 |
23 |
|
T27 |
19 |
|
T140 |
1 |
| others[3] |
2101 |
1 |
|
T2 |
37 |
|
T9 |
1 |
|
T27 |
33 |
| false |
666 |
1 |
|
T2 |
10 |
|
T4 |
1 |
|
T9 |
1 |
| true |
409 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
127 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T27 |
4 |
| others[1] |
108 |
1 |
|
T2 |
6 |
|
T27 |
7 |
|
T23 |
9 |
| others[2] |
106 |
1 |
|
T2 |
1 |
|
T27 |
6 |
|
T23 |
6 |
| others[3] |
197 |
1 |
|
T2 |
10 |
|
T8 |
1 |
|
T27 |
7 |
| false |
46 |
1 |
|
T2 |
4 |
|
T23 |
2 |
|
T24 |
2 |
| true |
6368 |
1 |
|
T1 |
1 |
|
T2 |
76 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T2 |
15 |
|
T27 |
8 |
|
T23 |
7 |
| others[1] |
223 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T27 |
8 |
| others[2] |
224 |
1 |
|
T2 |
9 |
|
T27 |
4 |
|
T131 |
1 |
| others[3] |
407 |
1 |
|
T2 |
9 |
|
T3 |
1 |
|
T9 |
3 |
| false |
121 |
1 |
|
T2 |
6 |
|
T27 |
9 |
|
T45 |
1 |
| true |
5732 |
1 |
|
T1 |
1 |
|
T2 |
53 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T2 |
15 |
|
T5 |
1 |
|
T19 |
2 |
| others[1] |
1099 |
1 |
|
T2 |
20 |
|
T9 |
1 |
|
T6 |
1 |
| others[2] |
1138 |
1 |
|
T2 |
22 |
|
T9 |
2 |
|
T27 |
25 |
| others[3] |
1785 |
1 |
|
T2 |
32 |
|
T4 |
1 |
|
T22 |
1 |
| false |
518 |
1 |
|
T2 |
12 |
|
T27 |
11 |
|
T23 |
8 |
| true |
1339 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T2 |
8 |
|
T27 |
11 |
|
T23 |
15 |
| others[1] |
244 |
1 |
|
T2 |
6 |
|
T7 |
1 |
|
T30 |
1 |
| others[2] |
217 |
1 |
|
T2 |
10 |
|
T27 |
11 |
|
T23 |
11 |
| others[3] |
408 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T27 |
12 |
| false |
116 |
1 |
|
T2 |
5 |
|
T27 |
3 |
|
T23 |
5 |
| true |
5721 |
1 |
|
T1 |
1 |
|
T2 |
55 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
5 |
|
T9 |
2 |
|
T27 |
8 |
| others[1] |
229 |
1 |
|
T2 |
10 |
|
T27 |
7 |
|
T45 |
1 |
| others[2] |
216 |
1 |
|
T2 |
17 |
|
T27 |
5 |
|
T23 |
7 |
| others[3] |
360 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T9 |
2 |
| false |
117 |
1 |
|
T2 |
7 |
|
T27 |
7 |
|
T46 |
1 |
| true |
5797 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T2 |
15 |
|
T4 |
1 |
|
T27 |
15 |
| others[1] |
1265 |
1 |
|
T2 |
21 |
|
T6 |
1 |
|
T27 |
17 |
| others[2] |
1256 |
1 |
|
T2 |
14 |
|
T27 |
21 |
|
T140 |
1 |
| others[3] |
2119 |
1 |
|
T2 |
41 |
|
T5 |
1 |
|
T19 |
1 |
| false |
660 |
1 |
|
T2 |
10 |
|
T27 |
10 |
|
T140 |
1 |
| true |
416 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T27 |
18 |
| others[1] |
1282 |
1 |
|
T2 |
20 |
|
T27 |
20 |
|
T23 |
21 |
| others[2] |
1283 |
1 |
|
T2 |
17 |
|
T9 |
1 |
|
T6 |
1 |
| others[3] |
2047 |
1 |
|
T2 |
33 |
|
T5 |
1 |
|
T27 |
28 |
| false |
667 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T27 |
11 |
| true |
404 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T2 |
3 |
|
T27 |
6 |
|
T23 |
7 |
| others[1] |
107 |
1 |
|
T2 |
4 |
|
T27 |
2 |
|
T23 |
4 |
| others[2] |
116 |
1 |
|
T2 |
5 |
|
T27 |
5 |
|
T23 |
1 |
| others[3] |
180 |
1 |
|
T2 |
7 |
|
T27 |
9 |
|
T23 |
10 |
| false |
66 |
1 |
|
T2 |
2 |
|
T27 |
1 |
|
T23 |
3 |
| true |
6364 |
1 |
|
T1 |
1 |
|
T2 |
80 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T27 |
7 |
| others[1] |
236 |
1 |
|
T2 |
9 |
|
T9 |
2 |
|
T22 |
1 |
| others[2] |
249 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T8 |
1 |
| others[3] |
404 |
1 |
|
T2 |
13 |
|
T30 |
1 |
|
T27 |
18 |
| false |
114 |
1 |
|
T2 |
5 |
|
T27 |
8 |
|
T23 |
5 |
| true |
5708 |
1 |
|
T1 |
1 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1103 |
1 |
|
T1 |
1 |
|
T2 |
24 |
|
T6 |
1 |
| others[1] |
1052 |
1 |
|
T2 |
21 |
|
T5 |
1 |
|
T27 |
13 |
| others[2] |
1101 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T9 |
2 |
| others[3] |
1829 |
1 |
|
T2 |
26 |
|
T3 |
1 |
|
T19 |
1 |
| false |
489 |
1 |
|
T2 |
8 |
|
T27 |
6 |
|
T140 |
1 |
| true |
1378 |
1 |
|
T9 |
4 |
|
T14 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
13 |
|
T47 |
1 |
|
T27 |
10 |
| others[1] |
228 |
1 |
|
T2 |
10 |
|
T27 |
8 |
|
T23 |
9 |
| others[2] |
240 |
1 |
|
T2 |
6 |
|
T27 |
5 |
|
T45 |
1 |
| others[3] |
406 |
1 |
|
T2 |
14 |
|
T27 |
13 |
|
T23 |
15 |
| false |
109 |
1 |
|
T2 |
6 |
|
T30 |
1 |
|
T27 |
4 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T9 |
1 |
| others[1] |
209 |
1 |
|
T2 |
9 |
|
T27 |
9 |
|
T45 |
1 |
| others[2] |
218 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
14 |
| others[3] |
373 |
1 |
|
T2 |
15 |
|
T9 |
4 |
|
T27 |
12 |
| false |
136 |
1 |
|
T2 |
3 |
|
T27 |
6 |
|
T23 |
7 |
| true |
5786 |
1 |
|
T1 |
1 |
|
T2 |
55 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T27 |
20 |
| others[1] |
1241 |
1 |
|
T2 |
17 |
|
T19 |
1 |
|
T27 |
21 |
| others[2] |
1306 |
1 |
|
T2 |
20 |
|
T4 |
1 |
|
T27 |
18 |
| others[3] |
2130 |
1 |
|
T2 |
38 |
|
T5 |
1 |
|
T9 |
1 |
| false |
618 |
1 |
|
T2 |
13 |
|
T27 |
8 |
|
T140 |
3 |
| true |
404 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T2 |
20 |
|
T4 |
1 |
|
T6 |
1 |
| others[1] |
1256 |
1 |
|
T2 |
21 |
|
T27 |
27 |
|
T49 |
1 |
| others[2] |
1260 |
1 |
|
T2 |
18 |
|
T27 |
15 |
|
T140 |
2 |
| others[3] |
2136 |
1 |
|
T2 |
31 |
|
T5 |
1 |
|
T27 |
26 |
| false |
630 |
1 |
|
T2 |
11 |
|
T27 |
12 |
|
T131 |
1 |
| true |
408 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
5 |
| others[1] |
105 |
1 |
|
T2 |
8 |
|
T27 |
4 |
|
T23 |
3 |
| others[2] |
113 |
1 |
|
T2 |
4 |
|
T27 |
6 |
|
T23 |
7 |
| others[3] |
198 |
1 |
|
T2 |
8 |
|
T27 |
9 |
|
T23 |
4 |
| false |
55 |
1 |
|
T2 |
3 |
|
T27 |
3 |
|
T23 |
2 |
| true |
6362 |
1 |
|
T1 |
1 |
|
T2 |
75 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T27 |
12 |
| others[1] |
223 |
1 |
|
T2 |
14 |
|
T27 |
4 |
|
T49 |
1 |
| others[2] |
240 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T47 |
1 |
| others[3] |
395 |
1 |
|
T2 |
17 |
|
T22 |
1 |
|
T27 |
20 |
| false |
128 |
1 |
|
T2 |
4 |
|
T9 |
1 |
|
T30 |
1 |
| true |
5709 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T2 |
21 |
|
T5 |
1 |
|
T19 |
2 |
| others[1] |
1046 |
1 |
|
T2 |
24 |
|
T6 |
1 |
|
T27 |
21 |
| others[2] |
1117 |
1 |
|
T2 |
17 |
|
T9 |
1 |
|
T14 |
1 |
| others[3] |
1830 |
1 |
|
T2 |
26 |
|
T4 |
1 |
|
T27 |
28 |
| false |
510 |
1 |
|
T2 |
13 |
|
T9 |
2 |
|
T30 |
1 |
| true |
1359 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T47 |
1 |
| others[1] |
207 |
1 |
|
T2 |
12 |
|
T8 |
1 |
|
T27 |
8 |
| others[2] |
240 |
1 |
|
T2 |
8 |
|
T27 |
10 |
|
T23 |
8 |
| others[3] |
395 |
1 |
|
T2 |
19 |
|
T30 |
1 |
|
T27 |
16 |
| false |
133 |
1 |
|
T2 |
4 |
|
T22 |
1 |
|
T27 |
8 |
| true |
5738 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
9 |
|
T22 |
1 |
|
T27 |
9 |
| others[1] |
240 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T27 |
12 |
| others[2] |
227 |
1 |
|
T2 |
13 |
|
T27 |
7 |
|
T23 |
11 |
| others[3] |
383 |
1 |
|
T2 |
22 |
|
T9 |
1 |
|
T27 |
12 |
| false |
102 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
6 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |