Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T2 |
18 |
|
T27 |
23 |
|
T131 |
1 |
| others[1] |
1271 |
1 |
|
T2 |
14 |
|
T6 |
1 |
|
T27 |
14 |
| others[2] |
1293 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
2067 |
1 |
|
T2 |
40 |
|
T5 |
1 |
|
T27 |
36 |
| false |
650 |
1 |
|
T2 |
7 |
|
T27 |
7 |
|
T140 |
2 |
| true |
415 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T2 |
13 |
|
T27 |
20 |
|
T23 |
25 |
| others[1] |
1279 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
1275 |
1 |
|
T2 |
25 |
|
T27 |
20 |
|
T140 |
3 |
| others[3] |
2099 |
1 |
|
T2 |
34 |
|
T5 |
1 |
|
T27 |
28 |
| false |
643 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T47 |
1 |
| true |
410 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T2 |
3 |
|
T27 |
5 |
|
T23 |
4 |
| others[1] |
104 |
1 |
|
T2 |
2 |
|
T27 |
5 |
|
T23 |
3 |
| others[2] |
101 |
1 |
|
T2 |
6 |
|
T27 |
2 |
|
T23 |
2 |
| others[3] |
204 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
3 |
| false |
52 |
1 |
|
T27 |
1 |
|
T23 |
3 |
|
T24 |
1 |
| true |
6387 |
1 |
|
T1 |
1 |
|
T2 |
88 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T9 |
1 |
| others[1] |
256 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
8 |
| others[2] |
240 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T27 |
7 |
| others[3] |
392 |
1 |
|
T2 |
19 |
|
T30 |
1 |
|
T27 |
15 |
| false |
116 |
1 |
|
T2 |
3 |
|
T27 |
4 |
|
T23 |
2 |
| true |
5715 |
1 |
|
T2 |
52 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1032 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T27 |
21 |
| others[1] |
1117 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
1100 |
1 |
|
T2 |
16 |
|
T30 |
1 |
|
T27 |
22 |
| others[3] |
1821 |
1 |
|
T2 |
37 |
|
T3 |
1 |
|
T5 |
1 |
| false |
553 |
1 |
|
T2 |
13 |
|
T9 |
2 |
|
T47 |
1 |
| true |
1329 |
1 |
|
T1 |
1 |
|
T9 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T2 |
8 |
|
T27 |
15 |
|
T23 |
8 |
| others[1] |
236 |
1 |
|
T2 |
15 |
|
T47 |
1 |
|
T27 |
9 |
| others[2] |
228 |
1 |
|
T2 |
6 |
|
T27 |
6 |
|
T46 |
1 |
| others[3] |
385 |
1 |
|
T2 |
21 |
|
T27 |
19 |
|
T23 |
19 |
| false |
131 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T27 |
6 |
| true |
5712 |
1 |
|
T1 |
1 |
|
T2 |
50 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T2 |
13 |
|
T27 |
9 |
|
T46 |
1 |
| others[1] |
210 |
1 |
|
T2 |
10 |
|
T9 |
1 |
|
T27 |
8 |
| others[2] |
248 |
1 |
|
T2 |
5 |
|
T9 |
1 |
|
T27 |
14 |
| others[3] |
371 |
1 |
|
T2 |
20 |
|
T27 |
16 |
|
T23 |
17 |
| false |
108 |
1 |
|
T2 |
4 |
|
T9 |
1 |
|
T27 |
5 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T2 |
21 |
|
T5 |
1 |
|
T9 |
1 |
| others[1] |
1276 |
1 |
|
T2 |
24 |
|
T4 |
1 |
|
T27 |
17 |
| others[2] |
1324 |
1 |
|
T2 |
19 |
|
T27 |
22 |
|
T140 |
2 |
| others[3] |
2048 |
1 |
|
T2 |
34 |
|
T9 |
1 |
|
T27 |
33 |
| false |
614 |
1 |
|
T2 |
3 |
|
T27 |
9 |
|
T131 |
1 |
| true |
432 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1315 |
1 |
|
T2 |
11 |
|
T5 |
1 |
|
T27 |
23 |
| others[1] |
1247 |
1 |
|
T2 |
23 |
|
T6 |
1 |
|
T27 |
23 |
| others[2] |
1239 |
1 |
|
T2 |
21 |
|
T27 |
17 |
|
T140 |
4 |
| others[3] |
2061 |
1 |
|
T2 |
37 |
|
T4 |
1 |
|
T27 |
27 |
| false |
680 |
1 |
|
T2 |
9 |
|
T27 |
11 |
|
T73 |
1 |
| true |
410 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T2 |
5 |
|
T27 |
2 |
|
T23 |
1 |
| others[1] |
106 |
1 |
|
T2 |
5 |
|
T27 |
2 |
|
T23 |
3 |
| others[2] |
101 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
6 |
| others[3] |
196 |
1 |
|
T2 |
2 |
|
T27 |
11 |
|
T23 |
5 |
| false |
59 |
1 |
|
T2 |
1 |
|
T27 |
3 |
|
T23 |
4 |
| true |
6374 |
1 |
|
T1 |
1 |
|
T2 |
86 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T27 |
11 |
| others[1] |
241 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T27 |
8 |
| others[2] |
248 |
1 |
|
T2 |
11 |
|
T27 |
5 |
|
T23 |
8 |
| others[3] |
396 |
1 |
|
T2 |
17 |
|
T30 |
1 |
|
T27 |
24 |
| false |
125 |
1 |
|
T2 |
3 |
|
T27 |
7 |
|
T49 |
1 |
| true |
5688 |
1 |
|
T2 |
52 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1010 |
1 |
|
T2 |
20 |
|
T6 |
1 |
|
T41 |
1 |
| others[1] |
1122 |
1 |
|
T2 |
20 |
|
T5 |
1 |
|
T9 |
1 |
| others[2] |
1088 |
1 |
|
T2 |
27 |
|
T27 |
18 |
|
T140 |
1 |
| others[3] |
1749 |
1 |
|
T2 |
20 |
|
T9 |
3 |
|
T19 |
2 |
| false |
586 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T8 |
1 |
| true |
1397 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T2 |
6 |
|
T27 |
9 |
|
T23 |
12 |
| others[1] |
244 |
1 |
|
T2 |
10 |
|
T27 |
15 |
|
T73 |
1 |
| others[2] |
259 |
1 |
|
T2 |
11 |
|
T22 |
1 |
|
T27 |
15 |
| others[3] |
393 |
1 |
|
T2 |
20 |
|
T27 |
15 |
|
T23 |
13 |
| false |
124 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T8 |
1 |
| true |
5685 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
261 |
1 |
|
T2 |
11 |
|
T8 |
1 |
|
T27 |
14 |
| others[1] |
215 |
1 |
|
T2 |
10 |
|
T27 |
12 |
|
T23 |
13 |
| others[2] |
208 |
1 |
|
T2 |
8 |
|
T27 |
9 |
|
T23 |
5 |
| others[3] |
347 |
1 |
|
T2 |
20 |
|
T9 |
3 |
|
T22 |
1 |
| false |
111 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T27 |
1 |
| true |
5810 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T2 |
27 |
|
T19 |
1 |
|
T41 |
1 |
| others[1] |
1230 |
1 |
|
T2 |
13 |
|
T27 |
21 |
|
T140 |
4 |
| others[2] |
1299 |
1 |
|
T2 |
22 |
|
T5 |
1 |
|
T27 |
20 |
| others[3] |
2075 |
1 |
|
T2 |
32 |
|
T4 |
1 |
|
T6 |
1 |
| false |
668 |
1 |
|
T2 |
7 |
|
T27 |
12 |
|
T23 |
11 |
| true |
414 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T2 |
19 |
|
T27 |
19 |
|
T140 |
5 |
| others[1] |
1278 |
1 |
|
T2 |
30 |
|
T5 |
1 |
|
T9 |
1 |
| others[2] |
1235 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T27 |
21 |
| others[3] |
2174 |
1 |
|
T2 |
29 |
|
T6 |
1 |
|
T27 |
36 |
| false |
615 |
1 |
|
T2 |
8 |
|
T4 |
1 |
|
T27 |
8 |
| true |
406 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T2 |
3 |
|
T27 |
5 |
|
T23 |
3 |
| others[1] |
115 |
1 |
|
T2 |
4 |
|
T27 |
5 |
|
T23 |
2 |
| others[2] |
106 |
1 |
|
T2 |
5 |
|
T22 |
1 |
|
T27 |
3 |
| others[3] |
202 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T27 |
6 |
| false |
51 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T23 |
1 |
| true |
6359 |
1 |
|
T1 |
1 |
|
T2 |
79 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T27 |
8 |
| others[1] |
236 |
1 |
|
T2 |
14 |
|
T9 |
1 |
|
T27 |
11 |
| others[2] |
271 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T9 |
1 |
| others[3] |
385 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T9 |
1 |
| false |
122 |
1 |
|
T2 |
4 |
|
T27 |
5 |
|
T23 |
8 |
| true |
5718 |
1 |
|
T2 |
46 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T2 |
20 |
|
T27 |
18 |
|
T140 |
5 |
| others[1] |
1054 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T6 |
1 |
| others[2] |
1150 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
1781 |
1 |
|
T2 |
39 |
|
T3 |
1 |
|
T4 |
1 |
| false |
570 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T47 |
1 |
| true |
1358 |
1 |
|
T9 |
3 |
|
T14 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T2 |
10 |
|
T47 |
1 |
|
T8 |
1 |
| others[1] |
226 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T30 |
1 |
| others[2] |
222 |
1 |
|
T2 |
9 |
|
T27 |
11 |
|
T73 |
1 |
| others[3] |
410 |
1 |
|
T2 |
16 |
|
T3 |
1 |
|
T22 |
1 |
| false |
116 |
1 |
|
T2 |
5 |
|
T27 |
5 |
|
T23 |
4 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T2 |
56 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
14 |
|
T9 |
1 |
|
T27 |
12 |
| others[1] |
223 |
1 |
|
T2 |
7 |
|
T27 |
9 |
|
T23 |
8 |
| others[2] |
220 |
1 |
|
T2 |
10 |
|
T27 |
7 |
|
T23 |
8 |
| others[3] |
371 |
1 |
|
T2 |
14 |
|
T22 |
1 |
|
T27 |
20 |
| false |
120 |
1 |
|
T2 |
5 |
|
T27 |
2 |
|
T45 |
1 |
| true |
5787 |
1 |
|
T1 |
1 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1192 |
1 |
|
T2 |
17 |
|
T27 |
19 |
|
T140 |
2 |
| others[1] |
1253 |
1 |
|
T2 |
14 |
|
T6 |
1 |
|
T27 |
15 |
| others[2] |
1217 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2168 |
1 |
|
T2 |
47 |
|
T19 |
1 |
|
T27 |
28 |
| false |
687 |
1 |
|
T2 |
10 |
|
T27 |
12 |
|
T140 |
2 |
| true |
435 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T2 |
10 |
|
T9 |
1 |
|
T27 |
28 |
| others[1] |
1279 |
1 |
|
T2 |
13 |
|
T27 |
25 |
|
T140 |
2 |
| others[2] |
1213 |
1 |
|
T2 |
21 |
|
T9 |
2 |
|
T27 |
14 |
| others[3] |
2148 |
1 |
|
T2 |
38 |
|
T4 |
1 |
|
T5 |
1 |
| false |
664 |
1 |
|
T2 |
19 |
|
T27 |
4 |
|
T140 |
1 |
| true |
398 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T2 |
4 |
|
T22 |
1 |
|
T27 |
6 |
| others[1] |
94 |
1 |
|
T2 |
2 |
|
T27 |
4 |
|
T23 |
3 |
| others[2] |
126 |
1 |
|
T2 |
3 |
|
T27 |
5 |
|
T23 |
1 |
| others[3] |
178 |
1 |
|
T2 |
8 |
|
T27 |
11 |
|
T23 |
8 |
| false |
49 |
1 |
|
T2 |
1 |
|
T23 |
1 |
|
T24 |
3 |
| true |
6386 |
1 |
|
T1 |
1 |
|
T2 |
83 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
12 |
|
T27 |
8 |
|
T23 |
10 |
| others[1] |
238 |
1 |
|
T2 |
10 |
|
T47 |
1 |
|
T27 |
5 |
| others[2] |
250 |
1 |
|
T2 |
15 |
|
T22 |
1 |
|
T27 |
10 |
| others[3] |
384 |
1 |
|
T1 |
1 |
|
T2 |
19 |
|
T9 |
1 |
| false |
108 |
1 |
|
T2 |
3 |
|
T27 |
5 |
|
T23 |
7 |
| true |
5731 |
1 |
|
T2 |
42 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1117 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T9 |
1 |
| others[1] |
1011 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T47 |
1 |
| others[2] |
1074 |
1 |
|
T2 |
21 |
|
T19 |
1 |
|
T27 |
20 |
| others[3] |
1843 |
1 |
|
T2 |
32 |
|
T5 |
1 |
|
T9 |
2 |
| false |
540 |
1 |
|
T2 |
8 |
|
T7 |
1 |
|
T8 |
1 |
| true |
1367 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T2 |
9 |
|
T27 |
14 |
|
T23 |
9 |
| others[1] |
234 |
1 |
|
T2 |
4 |
|
T27 |
13 |
|
T23 |
12 |
| others[2] |
223 |
1 |
|
T2 |
11 |
|
T27 |
7 |
|
T23 |
8 |
| others[3] |
401 |
1 |
|
T2 |
14 |
|
T3 |
1 |
|
T7 |
1 |
| false |
108 |
1 |
|
T2 |
5 |
|
T27 |
3 |
|
T23 |
4 |
| true |
5742 |
1 |
|
T1 |
1 |
|
T2 |
58 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T2 |
13 |
|
T27 |
13 |
|
T46 |
1 |
| others[1] |
222 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T27 |
8 |
| others[2] |
221 |
1 |
|
T2 |
9 |
|
T9 |
3 |
|
T27 |
8 |
| others[3] |
393 |
1 |
|
T2 |
13 |
|
T27 |
21 |
|
T23 |
16 |
| false |
125 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T27 |
5 |
| true |
5766 |
1 |
|
T1 |
1 |
|
T2 |
50 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T2 |
22 |
|
T5 |
1 |
|
T27 |
21 |
| others[1] |
1294 |
1 |
|
T2 |
16 |
|
T6 |
1 |
|
T27 |
17 |
| others[2] |
1252 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T27 |
22 |
| others[3] |
2064 |
1 |
|
T2 |
32 |
|
T4 |
1 |
|
T9 |
1 |
| false |
660 |
1 |
|
T2 |
13 |
|
T27 |
10 |
|
T23 |
6 |
| true |
416 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T160 |
1 |
|
T338 |
1 |
|
T339 |
1 |
| others[1] |
2 |
1 |
|
T340 |
1 |
|
T341 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T342 |
1 |
|
T343 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T344 |
1 |
|
T345 |
1 |
|
T346 |
1 |
| false |
6 |
1 |
|
T210 |
1 |
|
T347 |
1 |
|
T348 |
1 |
| true |
25 |
1 |
|
T153 |
1 |
|
T159 |
1 |
|
T349 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T210 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
1 |
1 |
|
T350 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
5 |
1 |
|
T153 |
1 |
|
T349 |
1 |
|
T351 |
1 |
| others[3] |
5 |
1 |
|
T343 |
1 |
|
T352 |
1 |
|
T339 |
1 |
| false |
8 |
1 |
|
T353 |
1 |
|
T354 |
1 |
|
T355 |
1 |
| true |
25 |
1 |
|
T159 |
1 |
|
T160 |
1 |
|
T342 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |