Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10896 |
1 |
|
T2 |
17 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
826 |
1 |
|
T2 |
20 |
|
T6 |
1 |
|
T27 |
19 |
| others[2] |
798 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T9 |
2 |
| others[3] |
1330 |
1 |
|
T2 |
45 |
|
T5 |
1 |
|
T27 |
27 |
| false |
407 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T27 |
11 |
| true |
528 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2566 |
1 |
|
T2 |
6 |
|
T48 |
32 |
|
T6 |
1 |
| others[1] |
2518 |
1 |
|
T2 |
10 |
|
T13 |
1 |
|
T48 |
29 |
| others[2] |
2520 |
1 |
|
T2 |
9 |
|
T4 |
1 |
|
T48 |
21 |
| others[3] |
4338 |
1 |
|
T2 |
16 |
|
T48 |
39 |
|
T33 |
56 |
| false |
1267 |
1 |
|
T2 |
5 |
|
T13 |
1 |
|
T5 |
1 |
| true |
1576 |
1 |
|
T1 |
1 |
|
T2 |
55 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10288 |
1 |
|
T2 |
7 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
301 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T8 |
1 |
| others[2] |
292 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T27 |
11 |
| others[3] |
468 |
1 |
|
T2 |
22 |
|
T27 |
15 |
|
T49 |
1 |
| false |
130 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T6 |
1 |
| true |
3306 |
1 |
|
T1 |
1 |
|
T2 |
42 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10560 |
1 |
|
T2 |
13 |
|
T13 |
2 |
|
T5 |
1 |
| others[1] |
501 |
1 |
|
T2 |
6 |
|
T4 |
1 |
|
T27 |
6 |
| others[2] |
491 |
1 |
|
T2 |
10 |
|
T19 |
1 |
|
T27 |
7 |
| others[3] |
780 |
1 |
|
T2 |
17 |
|
T9 |
1 |
|
T19 |
1 |
| false |
251 |
1 |
|
T2 |
2 |
|
T27 |
8 |
|
T140 |
2 |
| true |
2202 |
1 |
|
T1 |
1 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10286 |
1 |
|
T2 |
10 |
|
T13 |
2 |
|
T47 |
1 |
| others[1] |
271 |
1 |
|
T2 |
8 |
|
T8 |
1 |
|
T22 |
1 |
| others[2] |
251 |
1 |
|
T2 |
7 |
|
T7 |
1 |
|
T30 |
1 |
| others[3] |
420 |
1 |
|
T2 |
22 |
|
T5 |
1 |
|
T27 |
11 |
| false |
161 |
1 |
|
T4 |
1 |
|
T27 |
13 |
|
T23 |
9 |
| true |
3396 |
1 |
|
T1 |
1 |
|
T2 |
54 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10314 |
1 |
|
T2 |
10 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
286 |
1 |
|
T2 |
13 |
|
T9 |
2 |
|
T27 |
7 |
| others[2] |
271 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T27 |
10 |
| others[3] |
395 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T6 |
1 |
| false |
142 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T27 |
5 |
| true |
3377 |
1 |
|
T1 |
1 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10876 |
1 |
|
T2 |
18 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
793 |
1 |
|
T2 |
25 |
|
T47 |
1 |
|
T27 |
24 |
| others[2] |
812 |
1 |
|
T2 |
19 |
|
T5 |
1 |
|
T27 |
21 |
| others[3] |
1404 |
1 |
|
T2 |
29 |
|
T4 |
1 |
|
T19 |
1 |
| false |
405 |
1 |
|
T2 |
10 |
|
T27 |
15 |
|
T140 |
1 |
| true |
495 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10836 |
1 |
|
T2 |
20 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
737 |
1 |
|
T2 |
13 |
|
T27 |
21 |
|
T140 |
2 |
| others[2] |
869 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T27 |
18 |
| others[3] |
1375 |
1 |
|
T2 |
36 |
|
T4 |
1 |
|
T6 |
1 |
| false |
413 |
1 |
|
T2 |
15 |
|
T27 |
10 |
|
T140 |
1 |
| true |
517 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2574 |
1 |
|
T2 |
8 |
|
T48 |
31 |
|
T6 |
1 |
| others[1] |
2521 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T13 |
1 |
| others[2] |
2523 |
1 |
|
T2 |
11 |
|
T48 |
19 |
|
T33 |
36 |
| others[3] |
4292 |
1 |
|
T2 |
17 |
|
T4 |
1 |
|
T13 |
1 |
| false |
1280 |
1 |
|
T2 |
5 |
|
T48 |
20 |
|
T33 |
16 |
| true |
1557 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10288 |
1 |
|
T2 |
8 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
287 |
1 |
|
T2 |
5 |
|
T9 |
1 |
|
T27 |
12 |
| others[2] |
259 |
1 |
|
T2 |
7 |
|
T9 |
1 |
|
T27 |
11 |
| others[3] |
445 |
1 |
|
T2 |
16 |
|
T3 |
1 |
|
T5 |
1 |
| false |
123 |
1 |
|
T2 |
2 |
|
T47 |
1 |
|
T27 |
3 |
| true |
3345 |
1 |
|
T1 |
1 |
|
T2 |
63 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10516 |
1 |
|
T2 |
18 |
|
T13 |
2 |
|
T9 |
2 |
| others[1] |
544 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T27 |
8 |
| others[2] |
469 |
1 |
|
T2 |
9 |
|
T19 |
1 |
|
T27 |
13 |
| others[3] |
794 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T27 |
11 |
| false |
216 |
1 |
|
T2 |
3 |
|
T30 |
1 |
|
T27 |
5 |
| true |
2208 |
1 |
|
T1 |
1 |
|
T2 |
40 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10296 |
1 |
|
T2 |
8 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
281 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T27 |
7 |
| others[2] |
251 |
1 |
|
T2 |
6 |
|
T8 |
1 |
|
T22 |
1 |
| others[3] |
420 |
1 |
|
T2 |
20 |
|
T7 |
1 |
|
T27 |
15 |
| false |
156 |
1 |
|
T2 |
8 |
|
T27 |
4 |
|
T23 |
3 |
| true |
3343 |
1 |
|
T1 |
1 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10281 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T13 |
2 |
| others[1] |
253 |
1 |
|
T2 |
13 |
|
T27 |
10 |
|
T23 |
5 |
| others[2] |
256 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
467 |
1 |
|
T2 |
12 |
|
T9 |
3 |
|
T6 |
1 |
| false |
137 |
1 |
|
T2 |
10 |
|
T27 |
5 |
|
T23 |
5 |
| true |
3353 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10872 |
1 |
|
T2 |
16 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
788 |
1 |
|
T2 |
24 |
|
T9 |
1 |
|
T27 |
19 |
| others[2] |
763 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T19 |
1 |
| others[3] |
1389 |
1 |
|
T2 |
37 |
|
T5 |
1 |
|
T6 |
1 |
| false |
442 |
1 |
|
T2 |
9 |
|
T4 |
1 |
|
T9 |
1 |
| true |
493 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10795 |
1 |
|
T2 |
14 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
823 |
1 |
|
T2 |
20 |
|
T9 |
1 |
|
T6 |
1 |
| others[2] |
846 |
1 |
|
T2 |
20 |
|
T5 |
1 |
|
T27 |
13 |
| others[3] |
1343 |
1 |
|
T2 |
37 |
|
T4 |
1 |
|
T27 |
43 |
| false |
427 |
1 |
|
T2 |
10 |
|
T27 |
11 |
|
T23 |
12 |
| true |
513 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2545 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T48 |
27 |
| others[1] |
2476 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T13 |
1 |
| others[2] |
2520 |
1 |
|
T2 |
7 |
|
T48 |
23 |
|
T33 |
31 |
| others[3] |
4299 |
1 |
|
T2 |
17 |
|
T13 |
1 |
|
T48 |
46 |
| false |
1346 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T48 |
10 |
| true |
1561 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10306 |
1 |
|
T2 |
9 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
275 |
1 |
|
T2 |
7 |
|
T7 |
1 |
|
T27 |
14 |
| others[2] |
265 |
1 |
|
T2 |
8 |
|
T27 |
10 |
|
T23 |
9 |
| others[3] |
468 |
1 |
|
T1 |
1 |
|
T2 |
18 |
|
T9 |
2 |
| false |
158 |
1 |
|
T2 |
6 |
|
T47 |
1 |
|
T27 |
7 |
| true |
3275 |
1 |
|
T2 |
53 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10495 |
1 |
|
T2 |
13 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
514 |
1 |
|
T2 |
14 |
|
T3 |
1 |
|
T5 |
1 |
| others[2] |
497 |
1 |
|
T2 |
14 |
|
T9 |
1 |
|
T30 |
1 |
| others[3] |
790 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T14 |
1 |
| false |
216 |
1 |
|
T2 |
2 |
|
T9 |
1 |
|
T27 |
3 |
| true |
2235 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10288 |
1 |
|
T2 |
9 |
|
T13 |
2 |
|
T5 |
1 |
| others[1] |
266 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T7 |
1 |
| others[2] |
276 |
1 |
|
T2 |
8 |
|
T4 |
1 |
|
T27 |
13 |
| others[3] |
457 |
1 |
|
T2 |
20 |
|
T22 |
1 |
|
T27 |
21 |
| false |
152 |
1 |
|
T2 |
3 |
|
T27 |
3 |
|
T23 |
9 |
| true |
3308 |
1 |
|
T1 |
1 |
|
T2 |
54 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10282 |
1 |
|
T2 |
8 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
243 |
1 |
|
T2 |
9 |
|
T27 |
6 |
|
T45 |
1 |
| others[2] |
298 |
1 |
|
T2 |
9 |
|
T9 |
1 |
|
T27 |
12 |
| others[3] |
400 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T27 |
21 |
| false |
128 |
1 |
|
T2 |
5 |
|
T9 |
1 |
|
T8 |
1 |
| true |
3396 |
1 |
|
T1 |
1 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10838 |
1 |
|
T2 |
18 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
806 |
1 |
|
T2 |
21 |
|
T6 |
1 |
|
T27 |
19 |
| others[2] |
794 |
1 |
|
T2 |
19 |
|
T9 |
1 |
|
T27 |
20 |
| others[3] |
1382 |
1 |
|
T2 |
32 |
|
T4 |
1 |
|
T5 |
1 |
| false |
436 |
1 |
|
T2 |
11 |
|
T19 |
1 |
|
T27 |
10 |
| true |
491 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10829 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T13 |
2 |
| others[1] |
813 |
1 |
|
T2 |
22 |
|
T6 |
1 |
|
T27 |
17 |
| others[2] |
815 |
1 |
|
T2 |
17 |
|
T9 |
2 |
|
T27 |
18 |
| others[3] |
1338 |
1 |
|
T2 |
33 |
|
T5 |
1 |
|
T27 |
28 |
| false |
439 |
1 |
|
T2 |
11 |
|
T9 |
1 |
|
T27 |
18 |
| true |
513 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2552 |
1 |
|
T2 |
14 |
|
T48 |
30 |
|
T6 |
1 |
| others[1] |
2541 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T48 |
26 |
| others[2] |
2625 |
1 |
|
T2 |
7 |
|
T13 |
1 |
|
T48 |
23 |
| others[3] |
4131 |
1 |
|
T2 |
19 |
|
T4 |
1 |
|
T13 |
1 |
| false |
1360 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T48 |
14 |
| true |
1538 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10315 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T13 |
2 |
| others[1] |
256 |
1 |
|
T2 |
7 |
|
T8 |
1 |
|
T27 |
9 |
| others[2] |
265 |
1 |
|
T2 |
10 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
498 |
1 |
|
T2 |
14 |
|
T9 |
2 |
|
T27 |
12 |
| false |
146 |
1 |
|
T2 |
6 |
|
T7 |
1 |
|
T27 |
9 |
| true |
3267 |
1 |
|
T2 |
55 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10483 |
1 |
|
T2 |
8 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
483 |
1 |
|
T2 |
4 |
|
T27 |
18 |
|
T140 |
1 |
| others[2] |
460 |
1 |
|
T2 |
6 |
|
T9 |
3 |
|
T14 |
1 |
| others[3] |
815 |
1 |
|
T2 |
15 |
|
T3 |
1 |
|
T4 |
1 |
| false |
229 |
1 |
|
T2 |
9 |
|
T27 |
6 |
|
T46 |
1 |
| true |
2277 |
1 |
|
T1 |
1 |
|
T2 |
59 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10295 |
1 |
|
T2 |
11 |
|
T13 |
2 |
|
T5 |
1 |
| others[1] |
290 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T30 |
1 |
| others[2] |
252 |
1 |
|
T2 |
9 |
|
T27 |
11 |
|
T23 |
7 |
| others[3] |
478 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
| false |
144 |
1 |
|
T2 |
5 |
|
T27 |
6 |
|
T23 |
5 |
| true |
3288 |
1 |
|
T1 |
1 |
|
T2 |
55 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10280 |
1 |
|
T2 |
11 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
258 |
1 |
|
T2 |
13 |
|
T5 |
1 |
|
T27 |
9 |
| others[2] |
246 |
1 |
|
T2 |
10 |
|
T9 |
3 |
|
T27 |
11 |
| others[3] |
427 |
1 |
|
T2 |
17 |
|
T27 |
14 |
|
T45 |
1 |
| false |
121 |
1 |
|
T2 |
6 |
|
T27 |
6 |
|
T23 |
5 |
| true |
3415 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10859 |
1 |
|
T2 |
23 |
|
T13 |
2 |
|
T5 |
1 |
| others[1] |
788 |
1 |
|
T2 |
18 |
|
T27 |
19 |
|
T140 |
2 |
| others[2] |
820 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
1359 |
1 |
|
T2 |
31 |
|
T27 |
31 |
|
T23 |
26 |
| false |
430 |
1 |
|
T2 |
16 |
|
T27 |
8 |
|
T140 |
1 |
| true |
491 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10869 |
1 |
|
T2 |
16 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
850 |
1 |
|
T2 |
22 |
|
T9 |
2 |
|
T6 |
1 |
| others[2] |
781 |
1 |
|
T2 |
16 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
1333 |
1 |
|
T2 |
37 |
|
T4 |
1 |
|
T9 |
1 |
| false |
413 |
1 |
|
T2 |
10 |
|
T9 |
1 |
|
T27 |
10 |
| true |
501 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2611 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T48 |
24 |
| others[1] |
2503 |
1 |
|
T2 |
5 |
|
T48 |
34 |
|
T33 |
32 |
| others[2] |
2619 |
1 |
|
T2 |
10 |
|
T48 |
28 |
|
T33 |
42 |
| others[3] |
4183 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T13 |
2 |
| false |
1272 |
1 |
|
T2 |
7 |
|
T4 |
1 |
|
T48 |
11 |
| true |
1559 |
1 |
|
T1 |
1 |
|
T2 |
50 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10317 |
1 |
|
T2 |
7 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
259 |
1 |
|
T2 |
10 |
|
T7 |
1 |
|
T27 |
7 |
| others[2] |
294 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
9 |
| others[3] |
469 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T9 |
1 |
| false |
164 |
1 |
|
T2 |
12 |
|
T9 |
1 |
|
T30 |
1 |
| true |
3244 |
1 |
|
T1 |
1 |
|
T2 |
46 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |